WO2008053160A1 - Translating a simulation-target memory access to a simulation-host memory access - Google Patents

Translating a simulation-target memory access to a simulation-host memory access Download PDF

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Publication number
WO2008053160A1
WO2008053160A1 PCT/GB2007/004045 GB2007004045W WO2008053160A1 WO 2008053160 A1 WO2008053160 A1 WO 2008053160A1 GB 2007004045 W GB2007004045 W GB 2007004045W WO 2008053160 A1 WO2008053160 A1 WO 2008053160A1
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Prior art keywords
entry
target
look
host
section
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PCT/GB2007/004045
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French (fr)
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Nigel Peter Topham
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The University Court Of The University Of Edinburgh
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Publication of WO2008053160A1 publication Critical patent/WO2008053160A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking

Definitions

  • Embodiments of the present invention relate to translating, in a simulation, a target memory access to a host memory access.
  • Software simulators are used in the semiconductor IP industry to predict the behavior of new chip architectures during software development.
  • the inventor has recognized that the processing speed of these simulators is typically constrained by the need to map a memory space of a simulation target to a memory space in a simulation host.
  • a translation lookaside buffer may be simulated. However this is a complex and slow procedure.
  • a method of simulating the operation of a target computer system at a host computer system comprising: parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and using a second value stored in the accessed entry as a host reference if the access check is successful.
  • a host computer system for simulating the operation of a target computer system: means for parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; means for accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; means for performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and means for using a second value stored in the accessed entry as a host reference if the access check is successful.
  • a look-up table data structure for translating a target reference, having an intermediate portion that separates first and second extreme portions to a host reference comprising a plurality of entries, wherein each entry is accessed using a different value of the intermediate portion of a target reference and comprises a first extreme portion of the target reference as an access check and a host reference as a return value for the access.
  • a method of translating a target reference to a host reference comprising: performing a look- up operation in which any one of a sub-set of the possible target references return a respective different host reference; and performing a simulation to map the target reference to a host reference if the look-up fails.
  • a look-up table data structure for translating a target reference for a target memory space that has n sections each of which has m sub-sections, the look-up table comprising m entries, one and only one for each sub-section, wherein a jth entry is associated with a jth sub-section of a section identified in the entry and the jth entry comprises a section identifier and a return value.
  • a method of controlling the translation of a target reference to a host reference when simulating the operation of a target computer system at a host computer system comprising: dividing a target memory space into n regular sections; dividing each section into m regular sub-sections; creating a look-up table that has m entries, one and only one for each sub-section, wherein a jth entry is associated with a jth sub-section of a section identified in the entry and the jth entry comprises a section identifier and a return value.
  • FIG. 1 illustrates a host computer system that is operable to simulate computer processes on a target system
  • Fig. 2 schematically illustrates one feature of the operation of the host system
  • Fig 3 schematically illustrates the components of a target address
  • Figs 4A and 4B schematically illustrates the target memory space and its associated addresses respectively
  • Fig 5 schematically illustrates a lookup table suitable for translating a target address
  • Fig 6 schematically illustrates a constrained target memory space
  • Fig 7 illustrates permission look-up tables
  • Fig 8 illustrates the address translation process 40.
  • Fig. 1 illustrates a host computer system 2 that is operable to simulate computer processes on a target system 6.
  • the host computer system 2 comprises processing circuitry 3 and a memory 4.
  • the processing circuitry 3 may be one or more programmable processors that operate under the control of computer program instructions 7 or may be an application specific processor.
  • the processing circuitry 3 is arranged to read from and write to the memory 4.
  • the memory 4 stores the computer program instructions 7 and also a look-up table 30 as a data structure 8.
  • the memory 4 includes a portion that may be used to emulate the target's memory space. This portion need not be a particular part of the memory 4 but may be composed of many parts of the memory which may be arbitrarily assigned.
  • the host computer system 2 simulates the processes of the target system. Some of these processes may involve accesses to the memory space (physical or virtual) of the target system 6.
  • the host system 2 is arranged to effectively simulate such accesses.
  • the computer program instructions 7 control the operation of the host system simulation when loaded into the processing circuitry 3.
  • the computer program instructions 7 provide the logic and routines that enables the host system 2 to maintain a lookup table (or tables) and perform the process illustrated in Fig 8.
  • the computer program instructions may arrive at the host system 2 via an electromagnetic carrier signal or be copied from a physical entity 11 such as a computer program product, a memory device or a record medium such as a CD- ROM or DVD.
  • a physical entity 11 such as a computer program product, a memory device or a record medium such as a CD- ROM or DVD.
  • a physical entity 11 may also be used to embody the data structure 8 defining a look-up table (or tables) 30.
  • the operation of the host system 2 is schematically illustrated in Fig 2.
  • the host system 2 uses a software implemented translation engine 9 to translate an address in the target memory space (target address 10) to an address (virtual or physical) in the host system (host address 32).
  • Fig 3 schematically illustrates the components of a target address.
  • the target address 10 is comprised of three contiguous portions. Two extreme portions 12, 16 sandwich an intermediate portion 14.
  • the leftmost extreme portion 12 is used for the most significant bit(s) (MSB) of the target address 10.
  • MSB 12 are used in the example below as a check when a lookup is made to a lookup table 30.
  • the rightmost extreme portion 16 is used for the least significant bit(s) (MSB) of the target address 10.
  • the LSB defines any one of a plurality of offset values for individual data blocks with a base memory unit common to the host and target memory systems.
  • the intermediate portion 14 is used for the intermediate significant bit(s) (ISB).
  • the ISB is used as a table index when the lookup table 30 is accessed.
  • Fig 4A schematically illustrates the target memory space 20
  • Fig 5 schematically illustrates a lookup table suitable for translating a target address from the target memory space 20 to a host address 32.
  • a table entry 34 S comprises a first value 36 which is used to check whether an access to an entry using a table index is valid and a second value 38 which is a value returned when an access to an entry using a table index is valid.
  • the first value 36 in this example, is one of the possible values for MSB 12.
  • the second value 38 is a host reference 32. It may be an address such as a physical address or a virtual address. It may be metadata, as explained later.
  • the first value 36 in the lookup table is used to identify a section 22 using its MSB 12.
  • the first value can take a value between 1 and n.
  • Fig 4A 1 4B m is 4. The ordered sequence is repeated in each section 22.
  • Each sub-section has a different value of ISB 14.
  • Fig 4B illustrates the MSB 12 and ISB 14 associated with each section 22 and sub-section 24 of the memory space 20.
  • the possible sub-sections an entry 34 may relate to are separated by a predetermined and fixed separation. These sub-sections are illustrated using consistent shading in Fig 4A. Addresses that use the same subsection 24 either refer to a single sub-section 24 or to sub-sections separated by some multiple of sections 22.
  • the look-up table 30 has m entries 34, one and only one for each sub-section 24.
  • Ayth entry 34 j is associated with a/th sub-section 24 j of a section identified by the first value 36 of the jth entry.
  • An entry for a particular sub-section is accessed using as a table index the ISB 14 for that sub-section.
  • the use of the ISB 14 as a table index avoids clustering.
  • the lookup table 30 is a data structure used to lookup a value 32 using a key as a table index 14.
  • the key is an ISB portion of the target address 10. The size of the portion of the target address used may vary with circumstances.
  • the lookup table 30 is a form of hash table which provides a simple and fast lookup.
  • the table index 14 is derived from the target address using an index generation function.
  • the index generation function is such that a difference between a first table index (created from a first target address by the index generation function) and a second table index (created from a second target address by the index generation function) indicates a difference between the first and second target addresses.
  • the index generation function may be a form of hash function.
  • the index generation function in the described example is the extraction of the ISB 14 from the target reference.
  • Fig 6 schematically illustrates the constraints on which portions of the target memory space 20 may simultaneously be associated with a host address via the look-up table 30.
  • the Figure illustrates the target memory space as a cuboid.
  • the cuboid has three orthogonal axes x, y, z.
  • the x-axis is associated with possible values of the MSB 12.
  • the y-axis is associated with possible values of the ISB 14.
  • the z-axis is associated with possible values of the LSB 16.
  • a portion of the cuboid referenced by a value (x, y) may be associated via the look-up table 30 with a host address space.
  • the size of the host address space unit matches the size of the target memory space base unit, so that the offset value LSB 16 referencing a particular data block in a base unit can also be used in the host memory space.
  • the constraints imposed by the look-up table 30 are that there cannot be degeneracy in ISB 14 but there can in MSB 12. That is, taking a horizontal slice (row) only one base unit in the target memory space can be linked to a base unit in the host memory space via the look-up table 30.
  • Fig 7 illustrates a particularly advantageous implementation.
  • a separate look-up table 30 is maintained for each different access type.
  • the access types are read, write and execute and there are associated respective look-up tables 30 r , 30 w and 30 e .
  • Permissions concerning which types of access are allowed to which target memory space 20 are controlled by controlling the entries in the respective look- up table. For example, if a portion of the target memory space 20 should not be written to, it is forbidden to make an entry in the look-up table 30 w that relates to that portion.
  • Fig 8 illustrates the address translation process 40.
  • the process is illustrated as a series of blocks. Each block may be considered to be a step in a method or a section of code in a computer program 7.
  • an instruction is parsed to identify whether it specifies an access type (read, write, execute) and whether it specifies a target address.
  • the access type and target address 10 are identified.
  • the target address 10 is parsed to extract ISB 14 and MSB 12.
  • the extracted ISB 14 is used as a table index to access an entry 34 in the lookup table 30 associated with the access type.
  • the first value 36 in the accessed entry 34 is compared to the extracted MSB 12.
  • the process 40 determines whether a TLB is simulated. If it is not, the process returns a TLB miss error at block 47. If it is, the process continues to block 48 where a TLB simulation is performed to identify subject host address and access the required host memory space. This typically requires a search.
  • the lookup table is updated at block 49 to enable a future reference to that host memory space to be made via the lookup table 30.
  • the entry 34 in the lookup table that was accessed at block 44 is replaced with a new entry 34 that has as its second value 38 the subject host address.
  • the look-up table 30 therefore operates as a constrained cache. It is a cache in that it stores recently accessed information. It is constrained in that it is effectively a group of m mini caches - one for each possible value of ISB 14 where each cache stores only the last access.
  • one field 37 may be a bit used to indicate whether the entry is a valid entry that is in use.
  • another field 39 may used as a flag indicating whether the host reference 38 stored in the second field 38 is a host address or metadata for an input/output process.
  • the field 39 may be check to determine whether the access relates to metadata in the simulation or a register value used in a processing instruction.
  • the process branches to block 53 where an entry validity check is performed, if it has not been done previously, using the field 37 (if present). If this check is successful, the process moves to block 54 where the value of the second field 38 returned by the host table is used as a pointer to metadata within the simulation. If the access relates to a processing instruction, the process branches to block 51 where an entry validity check is performed, if it has not been done previously, using the field 37 (if present). If this check is successful, the process moves to block 52 where the value of the second field 38 returned by the host table is used to access the host memory to obtain the simulated register value.
  • Embodiments of the invention find particular application in semiconductor design and manufacture.
  • software or hardware implemented design applications such as computer aided design software packages.

Abstract

A method of simulating the operation of a target computer system at a host computer system comprising: parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and using a second value stored in the accessed entry as a host reference if the access check is successful.

Description

TITLE
Translating a simulation-target memory access to a simulation-host memory access
FIELD OF THE INVENTION
Embodiments of the present invention relate to translating, in a simulation, a target memory access to a host memory access.
BACKGROUND TO THE INVENTION
Software simulators are used in the semiconductor IP industry to predict the behavior of new chip architectures during software development.
The inventor has recognized that the processing speed of these simulators is typically constrained by the need to map a memory space of a simulation target to a memory space in a simulation host.
A translation lookaside buffer may be simulated. However this is a complex and slow procedure.
It would be desirable to improve the simulation speed of target memory referencing instructions on a simulation host.
BRIEF DESCRIPTION OF THE INVENTION
According to one embodiment of the invention there is provided a method of simulating the operation of a target computer system at a host computer system comprising: parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and using a second value stored in the accessed entry as a host reference if the access check is successful.
According to another embodiment of the invention there is provided a host computer system for simulating the operation of a target computer system: means for parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; means for accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; means for performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and means for using a second value stored in the accessed entry as a host reference if the access check is successful.
According to a further embodiment of the invention there is provided a look-up table data structure for translating a target reference, having an intermediate portion that separates first and second extreme portions to a host reference comprising a plurality of entries, wherein each entry is accessed using a different value of the intermediate portion of a target reference and comprises a first extreme portion of the target reference as an access check and a host reference as a return value for the access.
According to another embodiment of the invention there is provided a method of translating a target reference to a host reference comprising: performing a look- up operation in which any one of a sub-set of the possible target references return a respective different host reference; and performing a simulation to map the target reference to a host reference if the look-up fails.
According to a further embodiment of the invention there is provided a look-up table data structure for translating a target reference for a target memory space that has n sections each of which has m sub-sections, the look-up table comprising m entries, one and only one for each sub-section, wherein a jth entry is associated with a jth sub-section of a section identified in the entry and the jth entry comprises a section identifier and a return value.
According to another embodiment of the invention there is provided a method of controlling the translation of a target reference to a host reference when simulating the operation of a target computer system at a host computer system comprising: dividing a target memory space into n regular sections; dividing each section into m regular sub-sections; creating a look-up table that has m entries, one and only one for each sub-section, wherein a jth entry is associated with a jth sub-section of a section identified in the entry and the jth entry comprises a section identifier and a return value.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention reference will now be made by way of example only to the accompanying drawings in which: Fig. 1 illustrates a host computer system that is operable to simulate computer processes on a target system;
Fig. 2 schematically illustrates one feature of the operation of the host system Fig 3 schematically illustrates the components of a target address Figs 4A and 4B schematically illustrates the target memory space and its associated addresses respectively; Fig 5 schematically illustrates a lookup table suitable for translating a target address
Fig 6 schematically illustrates a constrained target memory space; Fig 7 illustrates permission look-up tables; and Fig 8 illustrates the address translation process 40.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
Fig. 1 illustrates a host computer system 2 that is operable to simulate computer processes on a target system 6.
The host computer system 2 comprises processing circuitry 3 and a memory 4. The processing circuitry 3 may be one or more programmable processors that operate under the control of computer program instructions 7 or may be an application specific processor.
The processing circuitry 3 is arranged to read from and write to the memory 4. The memory 4 stores the computer program instructions 7 and also a look-up table 30 as a data structure 8. The memory 4 includes a portion that may be used to emulate the target's memory space. This portion need not be a particular part of the memory 4 but may be composed of many parts of the memory which may be arbitrarily assigned.
The host computer system 2 simulates the processes of the target system. Some of these processes may involve accesses to the memory space (physical or virtual) of the target system 6. The host system 2 is arranged to effectively simulate such accesses.
The computer program instructions 7 control the operation of the host system simulation when loaded into the processing circuitry 3. The computer program instructions 7 provide the logic and routines that enables the host system 2 to maintain a lookup table (or tables) and perform the process illustrated in Fig 8.
The computer program instructions may arrive at the host system 2 via an electromagnetic carrier signal or be copied from a physical entity 11 such as a computer program product, a memory device or a record medium such as a CD- ROM or DVD.
A physical entity 11 may also be used to embody the data structure 8 defining a look-up table (or tables) 30.
The operation of the host system 2 is schematically illustrated in Fig 2. The host system 2 uses a software implemented translation engine 9 to translate an address in the target memory space (target address 10) to an address (virtual or physical) in the host system (host address 32).
Fig 3 schematically illustrates the components of a target address. In this example, the target address 10 is comprised of three contiguous portions. Two extreme portions 12, 16 sandwich an intermediate portion 14.
The leftmost extreme portion 12 is used for the most significant bit(s) (MSB) of the target address 10. The MSB 12 are used in the example below as a check when a lookup is made to a lookup table 30.
The rightmost extreme portion 16 is used for the least significant bit(s) (MSB) of the target address 10. The LSB defines any one of a plurality of offset values for individual data blocks with a base memory unit common to the host and target memory systems. The intermediate portion 14 is used for the intermediate significant bit(s) (ISB). The ISB is used as a table index when the lookup table 30 is accessed.
Fig 4A schematically illustrates the target memory space 20 and Fig 5 schematically illustrates a lookup table suitable for translating a target address from the target memory space 20 to a host address 32.
The lookup table 30 has m entries 34j where i=1, 2..m. Each entry is accessed using a table index 14 corresponding to an ISB value. There is one entry and one entry only for each possible value of ISB 14.
A table entry 34S comprises a first value 36 which is used to check whether an access to an entry using a table index is valid and a second value 38 which is a value returned when an access to an entry using a table index is valid.
The first value 36, in this example, is one of the possible values for MSB 12. The second value 38 is a host reference 32. It may be an address such as a physical address or a virtual address. It may be metadata, as explained later.
The target memory space 30 is logically divided into an ordered sequence of n regular non-overlapping sections 22j for i= 1 , 2...n. Each section has a different value for MSB 12.
The first value 36 in the lookup table is used to identify a section 22 using its MSB 12. The first value can take a value between 1 and n.
Each section 22j is divided into an ordered sequence of m regular non- overlapping sub-sections 24j for i= 1 , 2...m. In Fig 4A1 4B m is 4. The ordered sequence is repeated in each section 22. Each sub-section has a different value of ISB 14. Fig 4B illustrates the MSB 12 and ISB 14 associated with each section 22 and sub-section 24 of the memory space 20.
The possible sub-sections an entry 34 may relate to are separated by a predetermined and fixed separation. These sub-sections are illustrated using consistent shading in Fig 4A. Addresses that use the same subsection 24 either refer to a single sub-section 24 or to sub-sections separated by some multiple of sections 22.
The look-up table 30 has m entries 34, one and only one for each sub-section 24. Ayth entry 34j is associated with a/th sub-section 24j of a section identified by the first value 36 of the jth entry. An entry for a particular sub-section is accessed using as a table index the ISB 14 for that sub-section.
The use of the ISB 14 as a table index avoids clustering.
The lookup table 30 is a data structure used to lookup a value 32 using a key as a table index 14. The key is an ISB portion of the target address 10. The size of the portion of the target address used may vary with circumstances.
The lookup table 30 is a form of hash table which provides a simple and fast lookup.
The table index 14 is derived from the target address using an index generation function. The index generation function is such that a difference between a first table index (created from a first target address by the index generation function) and a second table index (created from a second target address by the index generation function) indicates a difference between the first and second target addresses. The index generation function may be a form of hash function. The index generation function in the described example is the extraction of the ISB 14 from the target reference.
Fig 6 schematically illustrates the constraints on which portions of the target memory space 20 may simultaneously be associated with a host address via the look-up table 30.
The Figure illustrates the target memory space as a cuboid. The cuboid has three orthogonal axes x, y, z. The x-axis is associated with possible values of the MSB 12.
The y-axis is associated with possible values of the ISB 14. The z-axis is associated with possible values of the LSB 16.
A portion of the cuboid referenced by a value (x, y) may be associated via the look-up table 30 with a host address space. The size of the host address space unit matches the size of the target memory space base unit, so that the offset value LSB 16 referencing a particular data block in a base unit can also be used in the host memory space.
Considering the x-y plane, the constraints imposed by the look-up table 30 are that there cannot be degeneracy in ISB 14 but there can in MSB 12. That is, taking a horizontal slice (row) only one base unit in the target memory space can be linked to a base unit in the host memory space via the look-up table 30.
Fig 7 illustrates a particularly advantageous implementation. In this implementation a separate look-up table 30 is maintained for each different access type. In the example illustrated, the access types are read, write and execute and there are associated respective look-up tables 30r , 30w and 30e . Permissions concerning which types of access are allowed to which target memory space 20 are controlled by controlling the entries in the respective look- up table. For example, if a portion of the target memory space 20 should not be written to, it is forbidden to make an entry in the look-up table 30w that relates to that portion.
Fig 8 illustrates the address translation process 40. The process is illustrated as a series of blocks. Each block may be considered to be a step in a method or a section of code in a computer program 7.
At block 41 an instruction is parsed to identify whether it specifies an access type (read, write, execute) and whether it specifies a target address. The access type and target address 10 are identified.
At block 42 the target address 10 is parsed to extract ISB 14 and MSB 12.
At block 43, the extracted ISB 14 is used as a table index to access an entry 34 in the lookup table 30 associated with the access type.
At block 44, the first value 36 in the accessed entry 34 is compared to the extracted MSB 12.
If there is a match between the first value 36 in the accessed entry and the extracted MSB 12 then the access is valid and the process continues to block 45.
If there is no match between the first value 36 in the accessed entry and the extracted MSB 12 then the process continues to block 46.
At block 46, the process 40 determines whether a TLB is simulated. If it is not, the process returns a TLB miss error at block 47. If it is, the process continues to block 48 where a TLB simulation is performed to identify subject host address and access the required host memory space. This typically requires a search.
Having identified the subject host address and accessed the referenced host memory space, the lookup table is updated at block 49 to enable a future reference to that host memory space to be made via the lookup table 30. The entry 34 in the lookup table that was accessed at block 44 is replaced with a new entry 34 that has as its second value 38 the subject host address.
The look-up table 30 therefore operates as a constrained cache. It is a cache in that it stores recently accessed information. It is constrained in that it is effectively a group of m mini caches - one for each possible value of ISB 14 where each cache stores only the last access.
It is possible to include within the first field 36 of an entry additional control information in addition to the MSB value 12 used as a check. For example, one field 37 may be a bit used to indicate whether the entry is a valid entry that is in use. For example, another field 39 may used as a flag indicating whether the host reference 38 stored in the second field 38 is a host address or metadata for an input/output process.
At block 45, the field 39 may be check to determine whether the access relates to metadata in the simulation or a register value used in a processing instruction.
If the access relates to metadata, the process branches to block 53 where an entry validity check is performed, if it has not been done previously, using the field 37 (if present). If this check is successful, the process moves to block 54 where the value of the second field 38 returned by the host table is used as a pointer to metadata within the simulation. If the access relates to a processing instruction, the process branches to block 51 where an entry validity check is performed, if it has not been done previously, using the field 37 (if present). If this check is successful, the process moves to block 52 where the value of the second field 38 returned by the host table is used to access the host memory to obtain the simulated register value.
Embodiments of the invention find particular application in semiconductor design and manufacture. In particular, in software or hardware implemented design applications such as computer aided design software packages.
Although embodiments of the present invention have been described in the preceding paragraphs with reference to various examples, it should be appreciated that modifications to the examples given can be made without departing from the scope of the invention as claimed.
Whilst endeavoring in the foregoing specification to draw attention to those features of the invention believed to be of particular importance it should be understood that the Applicant claims protection in respect of any patentable feature or combination of features hereinbefore referred to and/or shown in the drawings whether or not particular emphasis has been placed thereon.
I/we claim:

Claims

1. A method of simulating the operation of a target computer system at a host computer system comprising: parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and using a second value stored in the accessed entry as a host reference if the access check is successful.
2. A method as claimed in claim 1 , wherein the target reference is an address.
3. A method table as claimed in claim 1 or 2, wherein a target memory space has an ordered sequence of n regular sections and each section has an ordered sequence of m regular sub-sections 24 that is repeated in each section and the look-up table that has m entries, one and only one for each sub-section.
4. A method as claimed in claim 3, wherein a jth entry is associated with a jth sub-section of a section identified in the entry by the first extreme portion.
5. A method as claimed in any preceding claim, wherein an entry may be updated to include a different first extreme portion and a different host reference but remains accessible using the same value of the intermediate portion of a target reference.
6. A method as claimed in any preceding claim, wherein the possible target references, by which an entry may be accessed, are separated by a predetermined and fixed separation in a target memory space.
7. A method as claimed in any preceding claim, wherein the second value is used as a host address.
8. A method as claimed in any one of claims 1 to 6, wherein the second value is used as a pointer, in the host, to metadata.
9. A method as claimed in any preceding claim, comprising checking a third value stored by the accessed entry to determine a type of host reference provided by the second value.
10. A method as claimed in any preceding claim, comprising checking a fourth value stored by the accessed entry to determine whether the entry is valid or invalid.
11. A method as claimed in any preceding claim further comprising identifying which one of a plurality of processes the target reference relates to and accessing a look-up table that is associated with the identified process.
12. A method as claimed in claim 11 , wherein each process has independently controllable permissions.
13. A method as claimed in claim 11 or 12, wherein the processes include read, write and execute and there is a read lookup table, a write lookup table and an execute lookup table.
14. A host computer system for simulating the operation of a target computer system: means for parsing a target reference, having an intermediate portion that separates first and second extreme portions, to obtain the intermediate portion and the first extreme portion; means for accessing a look-up table using the obtained intermediate portion, wherein the look-up table comprises a plurality of entries and each entry is accessed using a different value of the intermediate portion of a target reference; means for performing an access check using the obtained first extreme portion of the target reference and a first value stored in the accessed entry; and means for using a second value stored in the accessed entry as a host reference if the access check is successful.
15. A look-up table data structure for translating a target reference, having an intermediate portion that separates first and second extreme portions to a host reference comprising a plurality of entries, wherein each entry is accessed using a different value of the intermediate portion of a target reference and comprises a first extreme portion of the target reference as an access check and a host reference as a return value for the access.
16. A method of translating a target reference to a host reference comprising: performing a look-up operation in which any one of a sub-set of the possible target references return a respective different host reference; and performing a simulation to map the target reference to a host reference if the look-up fails.
17. A method as claimed in claim 16, wherein the sub-set is of fixed size m.
18. A method as claimed in claim 16 or 17, wherein a target reference refers to a target memory space having an ordered sequence of n regular sections each of which has an ordered sequence of m regular sub-sections that is repeated in each section and the sub-set has m entries, one and only one for each subsection.
19. A method as claimed in claim 16, 17 or 18, wherein the look-up operation using a look-up table or collection of look-up tables as defined in claim 15.
20. A method as claimed in claim 16, 17, 18 or 19, wherein the look-up operation uses a different look-up table for each one of a plurality of processes.
21. A method as claimed in claim 20, wherein each process has independently controllable permissions.
22. A method as claimed in claim 19, 20 or 21 wherein a read lookup table is used for a read instruction, write lookup table is used for a write instruction and an execute lookup table is used for an execute instruction.
23. A look-up table data structure for translating a target reference for a target memory space that has n sections each of which has m sub-sections, the look-up table comprising m entries, one and only one for each sub-section, wherein a jth entry is associated with a jth sub-section of a section identified in the entry and the jth entry comprises a section identifier and a return value.
24. A method of controlling the translation of a target reference to a host reference when simulating the operation of a target computer system at a host computer system comprising: dividing a target memory space into n regular sections; dividing each section into m regular sub-sections; creating a look-up table that has m entries, one and only one for each subsection, wherein a /th entry is associated with a /th sub-section of a section identified in the entry and the/th entry comprises a section identifier and a return value.
25. A computer program comprising program instructions for causing a computer to perform the method of any one of claims 1 to 14, 16 to 23 or 24.
26. An tangible computer readable medium embodying the computer program as claimed in claim 25.
PCT/GB2007/004045 2006-11-01 2007-10-23 Translating a simulation-target memory access to a simulation-host memory access WO2008053160A1 (en)

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