WO2004008490A2 - A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics - Google Patents

A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics Download PDF

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Publication number
WO2004008490A2
WO2004008490A2 PCT/US2003/021566 US0321566W WO2004008490A2 WO 2004008490 A2 WO2004008490 A2 WO 2004008490A2 US 0321566 W US0321566 W US 0321566W WO 2004008490 A2 WO2004008490 A2 WO 2004008490A2
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Prior art keywords
thε
signal
circuit
data
values
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PCT/US2003/021566
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French (fr)
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WO2004008490A3 (en
Inventor
Jared L. Zerbe
Vladimir M. Stojanovic
Fred F. Chen
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Rambus Inc.
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Priority claimed from US10/195,129 external-priority patent/US7292629B2/en
Priority claimed from US10/195,130 external-priority patent/US7362800B1/en
Priority claimed from US10/195,140 external-priority patent/US8861667B1/en
Application filed by Rambus Inc. filed Critical Rambus Inc.
Priority to AU2003251839A priority Critical patent/AU2003251839A1/en
Publication of WO2004008490A2 publication Critical patent/WO2004008490A2/en
Publication of WO2004008490A3 publication Critical patent/WO2004008490A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

Definitions

  • the pr ⁇ s ⁇ nt invention relates generally to high spe ⁇ d signaling within and b ⁇ tween int ⁇ grated circuit devices, and more particularly to reducing latent signal distortions in high spe ⁇ d signaling systems.
  • Equalizing driver circuits are often used in high spe ⁇ d signaling syst ⁇ ms to mitigat ⁇ th ⁇ ⁇ ff ⁇ cts of int ⁇ r-symbol int ⁇ rf ⁇ r ⁇ nc ⁇ and crosstalk.
  • signaling system 100 of Figur ⁇ 1 for example, data values queu ⁇ d in buff ⁇ r 104 ar ⁇ output to signal path 102 by output driv ⁇ r 101 simultaneously with transmission of an equalizing signal by equalizing driver 109.
  • the equalizing driv ⁇ r 109 includ ⁇ s a shift r ⁇ gist ⁇ r 113 and a bank of output driv ⁇ rs 111 to g ⁇ n ⁇ rate an equalizing signal based on the two most rec ⁇ ntly transmitt ⁇ d data valu ⁇ s and the data value to be transmitted after the present, ref ⁇ r ⁇ nce value.
  • the ⁇ qualizing driv ⁇ r 109 constitutes a thre ⁇ -tap (i. ⁇ ., thr ⁇ data sourc ⁇ ) equalizer for reducing inter- symbol interference that results from disp ⁇ rsion of signals transmitt ⁇ d n ⁇ ar in tim ⁇ to the r ⁇ f ⁇ r ⁇ nc ⁇ valu ⁇ (i. ⁇ ., disp ⁇ rsion-typ ⁇ ISI).
  • Whil ⁇ the ⁇ qualizing driv ⁇ r 109 is ⁇ ff ⁇ ctiv ⁇ for r ⁇ ducing relatively low-latency distortions such as dispersion-typ ⁇ 1ST, oth ⁇ r typ ⁇ s of syst ⁇ matic distortions, such as signal r ⁇ fl ⁇ ctions (also r ⁇ f ⁇ rr ⁇ d to as r ⁇ fl ⁇ ction-typ ⁇ ISI), tend to have a much higher latency (i. ⁇ ., occur much later in time r ⁇ lative to transmission of the ref ⁇ r ⁇ nc ⁇ value) and therefore would require a substantially larger number of taps and a correspondingly larg ⁇ r shift r ⁇ gist ⁇ r to count ⁇ ract.
  • relatively low-latency distortions such as dispersion-typ ⁇ 1ST
  • oth ⁇ r typ ⁇ s of syst ⁇ matic distortions such as signal r ⁇ fl ⁇ ctions (also r ⁇ f ⁇ rr ⁇ d to as r ⁇ fl ⁇ ction-typ ⁇ ISI
  • a first refl ⁇ ction, A T occurs wh ⁇ n a ref ⁇ r ⁇ nce signal encounters an imp ⁇ danc ⁇ discontinuity at a transmit-sid ⁇ interfac ⁇ 105 between a transmit-side portion (102A) and a backplan ⁇ portion (102B) of the signal path 102 (e.g., a connector interfac ⁇ to a backplan ⁇ ).
  • th ⁇ reflection will arrive at the input of a rec ⁇ iv ⁇ r 103 with a lat ⁇ ncy (i.e., d ⁇ lay r ⁇ lativ ⁇ to arrival of th ⁇ unr ⁇ fl ⁇ cted ref ⁇ r ⁇ nc ⁇ signal) ⁇ qual to approximately twic ⁇ th ⁇ r ⁇ fl ⁇ ction flight tim ⁇ b ⁇ tw ⁇ n th ⁇ transmit-sid ⁇ int ⁇ rfac ⁇ 105 and th ⁇ transmit circuit output.
  • a lat ⁇ ncy i.e., d ⁇ lay r ⁇ lativ ⁇ to arrival of th ⁇ unr ⁇ fl ⁇ cted ref ⁇ r ⁇ nc ⁇ signal
  • Figure 2 is a wav ⁇ form diagram of reflections A , A R , B, C T , C R and D illustrating their r ⁇ sp ⁇ ctiv ⁇ latencies r ⁇ lative to reference signal arrival time, T (A2 TR corresponds to additional reflections produced by the int ⁇ rface 105). Because such reflections may occur at latenci ⁇ s on th ⁇ order of tens or ev ⁇ n hundreds of signal transmission intervals, the shift regist ⁇ r 113 would n ⁇ d to b ⁇ substantially deeper in order to store the tap values need ⁇ d to mitigat ⁇ th ⁇ resulting distortions.
  • the precise tim ⁇ at which r ⁇ fl ⁇ ctions arriv ⁇ at the receiv ⁇ r 103 ar ⁇ d ⁇ p ⁇ nd ⁇ nt upon syst ⁇ m configuration meaning that a gen ⁇ rally applicable equalizer, whether implem ⁇ nt ⁇ d on th ⁇ transmit or receiv ⁇ sid ⁇ of the signaling syst ⁇ m 100, would need a relatively large number of equalizing taps to be able to compensat ⁇ for a r ⁇ fl ⁇ ction occurring at any tim ⁇ b ⁇ tw ⁇ en the signal transmit time and a worst case lat ⁇ ncy.
  • each additional equalizing tap increases the parasitic capacitance of the transmit or receive circuit, degrading the fr ⁇ qu ⁇ ncy r ⁇ spons ⁇ of th ⁇ circuit and pot ⁇ ntially increasing th ⁇ imp ⁇ dance discontinuity (and therefore the magnitude of reflected signal) at the circuit input/output.
  • Th ⁇ present invention is illustrated by way of ⁇ xampl ⁇ , and not by way of limitation, in th ⁇ figures of the accompanying drawings and in which like r ⁇ f ⁇ r ⁇ nc ⁇ num ⁇ rals r ⁇ f ⁇ r to similar elem ⁇ nts and in which:
  • Figure 1 illustrates a prior-art signaling system
  • Figure 2 is a waveform diagram of refl ⁇ ct ⁇ d signals produced by the prior-art signaling system of Figure 1 ;
  • Figure 3 illustrat ⁇ s a signaling syst ⁇ m according an ⁇ mbodim ⁇ nt of th ⁇ invention
  • Figure 4 illustrates an ex ⁇ mplary relationship b ⁇ tw ⁇ n clock and data signals in th ⁇ signaling syst ⁇ m of Figure 3
  • Figure 5 illustrates the manner in which pre- ⁇ mphasis and s ⁇ l ⁇ ctabl ⁇ - tap equalization are employed to reduce low- and high-latency distortions in th ⁇ signaling syst ⁇ m of Figure 3;
  • Figure 6 illustrates a transmit device having circuitry for s ⁇ l ⁇ cting betwe ⁇ n t ⁇ mporal ⁇ qualization and cross-talk cancellation data sources;
  • Figure 7 illustrates transmit and receive devices configured to perform near-end cross-talk cancellation;
  • Figure 8 illustrates a transceiver device that includes both an ⁇ qualizing transmitt ⁇ r and an equalizing receiv ⁇ r
  • Figure 9 illustrates an equalizing transceiv ⁇ r according to an ⁇ mbodim ⁇ nt in which both transmitt ⁇ d and receiv ⁇ d data valu ⁇ s are stor ⁇ d and s ⁇ l ⁇ ctiv ⁇ ly us ⁇ d to source ⁇ qualiz ⁇ r taps;
  • Figure 10 illustrates an ⁇ x ⁇ mplary buff ⁇ r that may b ⁇ us ⁇ d within the receiv ⁇ r of Figure 3;
  • Figure 11 is a flow diagram of an ⁇ xemplary method of s ⁇ l ⁇ cting a data valu ⁇ having desired symbol latency from the buffer of Figure 10;
  • Figure 12 illustrates an ex ⁇ mplary ⁇ mbodim ⁇ nt of a tap s ⁇ l ⁇ ct circuit
  • Figure 13 illustrates an ex ⁇ mplary embodiment of the select logic of Figure 12
  • Figure 14 illustrates a gen ⁇ raliz ⁇ d sel ⁇ ct circuit that may b ⁇ us ⁇ d to s ⁇ l ⁇ ct Q tap values from the buffer circuit of Figure 12;
  • Figure 15 illustrat ⁇ s an ⁇ mbodim ⁇ nt of a switch ⁇ l ⁇ m ⁇ nt that may b ⁇ us ⁇ d within th ⁇ switch matrix of Figure 14;
  • Figure 16 illustrat ⁇ s an embodiment of an equalizing receiv ⁇ r;
  • Figure 17 illustrat ⁇ s th ⁇ rec ⁇ iv ⁇ circuit of Figure 16 in greater detail
  • Figure 18 illustrates an exemplary timing relationship between clock, data and equalization signals in the equalizing receiver of Figure 16;
  • Figure 19 illustrates a current-sinking output driv ⁇ r that may be used within the equalizing receiv ⁇ r of Figure 16;
  • Figure 20 illustrates an embodim ⁇ nt of a push-pull typ ⁇ of sub-driver circuit that may be us ⁇ d within an ⁇ qualizing output driv ⁇ r;
  • Figure 21 illustrates another ⁇ mbodim ⁇ nt of a sub-driv ⁇ r circuit that may b ⁇ us ⁇ d within an equalizing output driver
  • Figure 22 illustrates an Var ⁇ type of equalizing circuit that may be us ⁇ d in ⁇ mbodim ⁇ nts of th ⁇ inv ⁇ ntion;
  • Figure 23 illustrates an embodiment of a lev ⁇ l shifting circuit that may be used within the equalizing circuit of Figure 22;
  • Figure 24 illustrates another type of equalizing circuit that may be used in embodiments of the invention;
  • Figure 25 illustrates an embodiment of a level shifting circuit that us ⁇ d within th ⁇ ⁇ qualizing circuit of Figure 24;
  • Figure 26 illustrates an equalizing receiver according to an embodiment of the invention;
  • Figure 27 illustrates a shift regist ⁇ r and tap selector that may be us ⁇ d within th ⁇ ⁇ qualizing r ⁇ c ⁇ iv ⁇ r of Figure 26;
  • Figure 28 illustrates an equalizing receiver for receiving a double data rate, multilev ⁇ l input signal according to an embodiment of the invention
  • Figure 29 illustrates an exemplary encoding of bits according to the level of a sampled, multilevel input signal
  • Figure 30 illustrat ⁇ s an ex ⁇ mplary timing relationship b ⁇ tw ⁇ en clock, data and equalization signals in an equalizing receiv ⁇ r;
  • Figure 31 illustrates an ⁇ mbodim ⁇ nt of an ⁇ qualizing receiver that generat ⁇ s r ⁇ c ⁇ iv ⁇ and ⁇ qualization clock signals having th ⁇ phas ⁇ relationship shown in Figure 30;
  • Figure 32 illustrat ⁇ s the use of embedded scoping to gen ⁇ rate a trace of a data signal ov ⁇ r a singl ⁇ symbol time;
  • Figure 33 illustrates an embodiment of a signaling system that employs ⁇ mb ⁇ dded scoping to determine equalizer tap selections, tap weights and tap polarities;
  • Figure 34 illustrates an exemplary trace record for a pulse waveform captured by an emb ⁇ dded scope within the signaling system of Figure 33;
  • Figure 35 illustrates a method of setting equalization coefficients in a signaling system according to the invention.
  • Figure 36 illustrat ⁇ s a signaling system that employs path length symmetry to reduce the total number of equalization taps ne ⁇ ded to compensate for reflection-type ISI.
  • circuit el ⁇ m ⁇ nts or circuit blocks may be shown as multi-conductor or single conductor signal lines.
  • Each of the multi-conductor signal lines may alternatively be singl ⁇ signal conductor lines, and each of the single conductor signal lines may alt ⁇ rnativ ⁇ ly b ⁇ multi-conductor signal lines.
  • a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic stat ⁇ or discharged to a low logic state) to indicate a particular condition.
  • a signal is said to b ⁇ "d ⁇ ass ⁇ rt ⁇ d” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating stat ⁇ that may occur wh ⁇ n th ⁇ signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition).
  • a signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled betw ⁇ n th ⁇ signal driving and signal receiving circuits.
  • a signal line is said to be “activated” wh ⁇ n a signal is asserted on the signal line, and “deactivated” when the signal is deasserted.
  • th ⁇ prefix symbol "/" attached to signal names indicat ⁇ s that th ⁇ signal is an active low signal (i.e., the asserted state is a logic low state).
  • a line over a signal name (e.g., ' ⁇ signal name > ') is also used to indicate an active low signal. Active low signals may be changed to active high signals and vice-versa as is gen ⁇ rally known in the art.
  • equalizing refers to counteracting, canceling or otherwise reducing signal distortion.
  • equalizing refers to counteracting, canceling or otherwise reducing signal distortion.
  • hi one embodim ⁇ nt, low-latency distortions e.g., disp ⁇ rsion-type
  • ISI, cross-talk, etc. are reduced by a transmit-side ⁇ qualization circuit, and high-latency distortions (e.g., signal reflections) ar ⁇ reduced by a rec ⁇ iv ⁇ -sid ⁇ equalization circuit; the lat ⁇ ncy of r ⁇ c ⁇ iv ⁇ -sid ⁇ equalization taps being offset relative to the reception time of a ref ⁇ r ⁇ nc ⁇ signal by th ⁇ numb ⁇ r of transmit- side equalization taps.
  • a s ⁇ lect circuit is provided to selectively route a relativ ⁇ ly small subs ⁇ t of th ⁇ stored data values to equalizing taps within the equalizing rec ⁇ iver. By this arrangem ⁇ nt, reflected signals arriving at various, latent times may be counteracted by routing of selected stored data valu ⁇ s to the rec ⁇ ive-side equalization taps.
  • the parasitic capacitance of the equalizing rec ⁇ iver is small relativ ⁇ to th ⁇ parasitic capacitance that would result from providing a dedicated tap for each stor ⁇ d data valu ⁇ .
  • Signaling System with Selectable-Tap Equalizer Figure 3 illustrates a signaling system 117 according to an ⁇ mbodim ⁇ nt of the invention.
  • the system 117 includes an equalizing transmitter 115 and equalizing receiver 116 coupled to one another via a high-spe ⁇ d signal path 122, and a controller 141 coupl ⁇ d to th ⁇ transmitt ⁇ r 115 and the receiv ⁇ r 116 via relatively low-speed signal paths 142A and 142B, respectively.
  • the signal path 122 is formed by component signal paths 122 A, 122B and 122C ( ⁇ .g., transmission lin ⁇ s that introduce respective, nonzero propagation delays and exhibit resp ⁇ ctiv ⁇ impedance characteristics), each disposed on respective circuit boards that are coupled to one another via circuit board interfac ⁇ s 125 and 127 ( ⁇ .g., connectors).
  • signal path 122B is form ⁇ d on a backplan ⁇ and signal paths
  • 122A and 122C ar ⁇ form ⁇ d on respective daughterboards (e.g., line cards) that are removably coupled to the backplane via connectors 125 and 127.
  • the transmitt ⁇ r 115 and r ⁇ c ⁇ iv ⁇ r 116 ar ⁇ impl ⁇ mented in r ⁇ sp ⁇ ctiv ⁇ int ⁇ grat ⁇ d circuit (IC) devices that are mounted on the daughterboards.
  • the controller which may be a g ⁇ neral or special purpos ⁇ processor, state machin ⁇ or other logic circuit, is impl ⁇ m ⁇ nt ⁇ d within a third int ⁇ grated circuit device mounted to a yet another circuit board.
  • signal paths 142 A and 142B ar ⁇ us ⁇ d to convey configuration information from the controller 141 to the transmitter 115 and rec ⁇ iv ⁇ r 116, r ⁇ sp ⁇ ctiv ⁇ ly, and may b ⁇ dispos ⁇ d on the sam ⁇ circuit board (or circuit boards) as signal path 122 or impl ⁇ mented by an Cod ⁇ structure such as a cable.
  • the controller may Var ⁇ ly b ⁇ coupl ⁇ d to th ⁇ transmitter 115 and rec ⁇ iv ⁇ r 116 by a shared signal path such as a multi-drop bus. Th ⁇ op ⁇ ration of th ⁇ controller 141 is discussed in greater detail below.
  • th ⁇ IC d ⁇ vices containing the transmitter 115, rec ⁇ iv ⁇ r 116 and controller 141 may be mounted to a common structure with the signaling paths 122, 142A and 142B coupled directly to the IC devices (e.g., all thre ⁇ ICs mount ⁇ d to a circuit board and coupled to one another via circuit board traces, or all thre ⁇ ICs packaged within a single multi-chip module with signal paths 122 and 142 formed b ⁇ tw ⁇ n the ICs by bond wires or oth ⁇ r conducting structures).
  • IC devices e.g., all thre ⁇ ICs mount ⁇ d to a circuit board and coupled to one another via circuit board traces, or all thre ⁇ ICs packaged within a single multi-chip module with signal paths 122 and 142 formed b ⁇ tw ⁇ n the ICs by bond wires or oth ⁇ r conducting structures.
  • the transmitter 115, r ⁇ c ⁇ iv ⁇ r 116 and controller 141, or any subset thereof, may be included within the same IC devic ⁇ ( ⁇ .g., syst ⁇ m on chip) and th ⁇ signaling paths 122 and/or 142 implemented by a metal layer or other conducting structure within th ⁇ IC d ⁇ vice.
  • IC devic ⁇ ⁇ .g., syst ⁇ m on chip
  • th ⁇ signaling paths 122 and/or 142 implemented by a metal layer or other conducting structure within th ⁇ IC d ⁇ vice.
  • the transmitter 115 transmits data on the signaling path 122 during succ ⁇ ssiv ⁇ tim ⁇ intervals, ref ⁇ rr ⁇ d to herein as symbol times.
  • ⁇ ach symbol time, Ts corresponds to a half cycle of a transmit clock signal, TCLK, such that two data values (e.g., valu ⁇ s A and B) are transmitted on signaling path 122 per transmit clock cycle.
  • Th ⁇ transmitt ⁇ d data signal arriv ⁇ s at th ⁇ input of receiver 116 after propagation time, Tp, and is sampled by the rec ⁇ iver 116 in r ⁇ spons ⁇ to ⁇ dges of a receive clock signal, RCLK.
  • th ⁇ receive clock signal has a quadrature phase relation to data valid windows (i.e., data eyes) in the incoming data signal such that each sample is captured at the midpoint of a data ey ⁇ .
  • data valid windows i.e., data eyes
  • th ⁇ sampling instant may b ⁇ skewed relative to data eye midpoints as necessary to satisfy signal setup and hold time requirements in the receiver 116.
  • more or f ⁇ wer symbols may be transmitted per cycle of the transmit clock signal.
  • the ⁇ qualizing transmitt ⁇ r 115 includ ⁇ s a transmit shift regist ⁇ r 124, output driv ⁇ r 121 and transmit ⁇ qualizer 129; the transmit equalizer 129 itself including a shift register 120 and a bank of output drivers 131.
  • the data value at th ⁇ h ⁇ ad of the transmit shift regist ⁇ r 124 referred to herein as the primary data value, is driv ⁇ n onto the signal path 122 by the output driv ⁇ r 121, and the equalizer 129 simultaneously drives an equalizing signal onto the signal path 122.
  • This type of ⁇ qualization is referred to herein as transmit preemphasis.
  • the signal driven onto th ⁇ signal path 122 by th ⁇ output driver 121 (referred to herein as the primary signal) is a multi-lev ⁇ l signal having on ⁇ of four possibl ⁇ stat ⁇ s ( ⁇ .g., d ⁇ fin ⁇ d by four distinct signal ranges) and therefore constitutes a symbol repr ⁇ s ⁇ ntativ ⁇ of two binary bits of information.
  • th ⁇ primary signal may hav ⁇ more or f ⁇ w ⁇ r possibl ⁇ states and therefore represent more or few ⁇ r than two binary bits.
  • th ⁇ primary signal may b ⁇ singl ⁇ - ⁇ nd ⁇ d or diff ⁇ r ⁇ ntial (an additional signal line is provid ⁇ d to carry th ⁇ compl ⁇ m ⁇ nt signal in th ⁇ differential case), and may be a voltage or current mode signal.
  • Each of the output driv ⁇ rs 131 within th ⁇ equalizing circuit 129 form either a pre-tap driver or post-tap driver according to whether the source data value has already been transmitted (post-tap data) or is yet to be transmitted
  • th ⁇ equalizer includes N post-tap drivers sourced by data valu ⁇ s within th ⁇ shift r ⁇ gist ⁇ r 120 and one pre-tap driver sourced by a data valu ⁇ within th ⁇ transmit shift register 124.
  • the resultant equalizing signal driven onto the data path 122 will have a signal level according to data values having symbol latencies of -1, 1,
  • the rec ⁇ iv ⁇ r 116 includes a sampling circuit 123, buffer 132, tap sel ⁇ ct circuit 128 and tap select logic 139. Data signals are sampled by the sampling circuit 123, then stored in the buffer 134 for eventual use by application logic (not shown). Because the buffered data is stored for at least a predetermined time, and represents historical data up to a pred ⁇ termin ⁇ d numb ⁇ r of symbol latencies, the buffered data forms an ideal source of post-tap data values.
  • buff ring of r ⁇ c ⁇ iv ⁇ d data in r ⁇ c ⁇ iv ⁇ r 116 incurs no additional storage overh ⁇ ad b ⁇ caus ⁇ th ⁇ r ⁇ c ⁇ iv ⁇ d data values ar ⁇ buffered in any event to facilitate transfer to receiv ⁇ -sid ⁇ application logic.
  • th ⁇ tap s ⁇ lect circuit 128 enabl ⁇ s a subs ⁇ t of data valu ⁇ s within th ⁇ buff ⁇ r ⁇ d data to b ⁇ s ⁇ lected to source equaliz ⁇ r taps in a r ⁇ c ⁇ iv ⁇ -side equalizer circuit.
  • a relativ ⁇ ly small numb ⁇ r of data valu ⁇ s may b ⁇ selected to form receiv ⁇ -side equalization taps having lat ⁇ ncies that match th ⁇ latencies of the distortions.
  • high latency distortions may be reduced by rec ⁇ iv ⁇ -side equalization without dramatically increasing the parasitic capacitance of the receiver (i.e., as would result from a large number of receiv ⁇ -sid ⁇ ⁇ qualization taps).
  • the tap s ⁇ l ⁇ ct logic is a configuration circuit that outputs a tap s ⁇ l ⁇ ct signal 134 according to a configuration value.
  • the configuration value may be automatically generated by system 117 (e.g., at system startup) or may be empirically d ⁇ t ⁇ rmin ⁇ d and stored within the configuration circuit or els ⁇ wh ⁇ r ⁇ within syst ⁇ m 117.
  • the receiv ⁇ r 116 includes an output driv ⁇ r 140 (illustrated in dashed outline in Figure 3 to indicate its optional nature) to drive an equalizing signal onto the signal path 122 (and therefore to the input of the sampling circuit 123) coincidentally with the symbol time of an incoming signal.
  • the sampling circuit 123 includes a preamplifier having an equalizing subcircuit.
  • an ⁇ qualizing subcircuit is coupl ⁇ d to the sampling circuit itself.
  • the distribution of low- and high-latency equalization functions b ⁇ tw ⁇ n th ⁇ ⁇ qualizing transmitt ⁇ r 115 and equalizing rec ⁇ iv ⁇ r 116 is achi ⁇ v ⁇ d through us ⁇ of a d ⁇ ad rang ⁇ within the receive-side buffer 132. That is, the range of stored data values that may be selected to source receiv ⁇ -sid ⁇ equalization taps (i. ⁇ ., R) is offs ⁇ t from the sampling instant by a number of symbol times, M.
  • M is equal to N
  • the rec ⁇ iv ⁇ r 116 is said to have a dead range of four symbol times.
  • buffer 132 is formed by a shift register having a dead range component 133 and a sel ⁇ ctabl ⁇ -rang ⁇ component 135, the tap selector 128 being coupl ⁇ d to th ⁇ s ⁇ l ⁇ ctable-range component 135 to s ⁇ l ⁇ ct th ⁇ subset of tap data sources therefrom.
  • th ⁇ d ⁇ ad rang ⁇ component of the buff ⁇ r 132 may include few ⁇ r than M storag ⁇ ⁇ l ⁇ m ⁇ nts or even zero storage el ⁇ m ⁇ nts, d ⁇ p ⁇ nding on th ⁇ tim ⁇ required to r ⁇ c ⁇ iv ⁇ data and transf ⁇ r data into th ⁇ buff ⁇ r 132.
  • th ⁇ tap selector 128 may be coupled to one or more storag ⁇ ⁇ l ⁇ ments within the dead range component 133 to enabl ⁇ th ⁇ siz ⁇ of the dead range to be programmed according to the configuration of the transmit circuit 115.
  • th ⁇ buff ⁇ r 132 may include one or more parallel r ⁇ gist ⁇ rs in addition to (or instead of) the shift register formed by components 133 and 135.
  • Figure 5 illustrates the manner in which pre- ⁇ mphasis at the transmitter 115 and selectable-tap equalization within the receiver 116 are employed to reduce low- and high-latency distortions in the signaling syst ⁇ m of Figur ⁇ 3.
  • the primary signal is transmitted during a transmit interval 149 (i.e., a symbol time) that starts at time T, and the corresponding primary value is used to generate a transmit-side equalization signal (i.e., pre ⁇ mphasis signal) ov ⁇ r a window of N symbol tim ⁇ s following th ⁇ transmit int ⁇ rval 149.
  • a transmit-side equalization signal i.e., pre ⁇ mphasis signal
  • Th ⁇ transmit-side equalization signal is used to reduce low-latency distortions that may result from any number of sources including, without limitation, dispersion-typ ⁇ ISI, inductive and capacitive coupling (which may be compensated, for exampl ⁇ , by sourcing a pr ⁇ - ⁇ mphasis output driv ⁇ r within bank 131 with a valu ⁇ being transmitted on a neighboring signal path), and low-latency refl ⁇ ctions ( ⁇ .g., r ⁇ fl ⁇ ctions that do not trav ⁇ l significantly further than the unrefl ⁇ cted primary signal and therefore arrive at the rec ⁇ iver shortly aft ⁇ r th ⁇ primary signal).
  • sources including, without limitation, dispersion-typ ⁇ ISI, inductive and capacitive coupling (which may be compensated, for exampl ⁇ , by sourcing a pr ⁇ - ⁇ mphasis output driv ⁇ r within bank 131 with a valu ⁇ being transmitted on a neighboring signal path), and low-latency refl ⁇
  • the primary signal is sampled by the rec ⁇ iver 116 during a reception interval (i.e., data valid window) that corresponds to the transmit interval 149, the reception interval being shifted relative to the transmit int ⁇ rval according to th ⁇ signal flight time betw ⁇ n the transmitter 115 and rec ⁇ iv ⁇ r 116.
  • Th ⁇ s ⁇ l ⁇ ctable-tap equaliz ⁇ r within th ⁇ rec ⁇ iv ⁇ r 116 has a dead range of M symbol tim ⁇ s and a selectable range of R symbol times.
  • th ⁇ sampled primary value (i.e., the primary received during the reception interval) is s ⁇ l ⁇ ctabl ⁇ to sourc ⁇ an equalizer tap within the rec ⁇ iver 116 when the symbol latency of the sampled primary value is great ⁇ r than M symbol tim ⁇ s and l ⁇ ss or ⁇ qual to R symbol tim ⁇ s.
  • previously r ⁇ c ⁇ ived values having symbol latencies ranging from M+l to R may be selected by the tap sel ⁇ ctor 128 of Figur ⁇ 3 and us ⁇ d to reduce high-latency distortions.
  • Intervals 150 l3 150 , and 150 within interval 153 illustrate equalization windows achi ⁇ v ⁇ d by tap s ⁇ l ⁇ ctions within th ⁇ tap selector 128.
  • interval 150 ⁇ corresponds to one or more tap selections used to ⁇ qualize a distortion occurring shortly aft ⁇ r th ⁇ dead rang ⁇
  • interval 150 corresponds to one or more tap s ⁇ lections used to reduce a distortion caused by a signal transmission dozens or even hundreds of symbol times prior to the current reception interval.
  • the polarity of signal contributions which form the transmit preemphasis signal may b ⁇ fix ⁇ d or programmable and may be established (or controlled) within the data shift regist ⁇ rs (i. ⁇ ., 124 and 120) or by the output drivers thems ⁇ lv ⁇ s ( ⁇ .g., output driv ⁇ rs within bank 131).
  • the polarity of signal contributions which form th ⁇ receiv ⁇ r equalization signal may be fixed or programmable and may be establish ⁇ d (or controlled) within a data storage circuit (i.e., buff ⁇ r 132) or within a r ⁇ c ⁇ iv ⁇ r ⁇ qualization circuit.
  • the controller 141 is used to configure one or more of the values of N, M and R (i.e., the number of transmit-side post-tap ⁇ qualiz ⁇ rs, th ⁇ r ⁇ c ⁇ iv ⁇ -side d ⁇ ad rang ⁇ and th ⁇ r ⁇ c ⁇ ive-sid ⁇ s ⁇ l ⁇ ctabl ⁇ rang ⁇ ) according to syst ⁇ m n ⁇ ds.
  • the controller includes a nonvolatile memory to store ⁇ mpirically or analytically determined values of N, M and R.
  • th ⁇ signaling syst ⁇ m 117 may include a separate storage (e.g., flash memory, or other non- volatile media) to store values of N, M and R (or values that may be used to d ⁇ t ⁇ rmin ⁇ N, M and R), the controller 141 being coupled to access such separat ⁇ storage via signal path 142 or another path.
  • the controller 141 communicates the post-tap equalizer count, N, to the transmitter 115 and the dead range and selectable range valu ⁇ s, M and R, to th ⁇ receiver 116.
  • th ⁇ values of N, M and R may be det ⁇ rmin ⁇ d at production tim ⁇ (e.g., through system testing) or design time, and pre-programm ⁇ d into configuration circuitry within th ⁇ transmitt ⁇ r 115 and/or r ⁇ c ⁇ iv ⁇ r 116, or fix ⁇ d by design of the transmitter 115 and/or receiv ⁇ r 116.
  • th ⁇ controller 141 and signal path 142 may b ⁇ omitt ⁇ d altog ⁇ th ⁇ r.
  • embodiments of the invention may additionally include circuitry to automatically det ⁇ rmin ⁇ distortion lat ⁇ nci ⁇ s and to s ⁇ lect correspondingly latent data tap sources from the buffer 132, thus providing a system-ind ⁇ pendent solution for r ⁇ ducing systematic distortion ev ⁇ nts of virtually any lat ⁇ ncy.
  • the controller 141 may be used to coordinate operation of the transmitter 115 and rec ⁇ iv ⁇ r 116 during such automatic distortion latency det ⁇ rmination, and also to d ⁇ termine appropriat ⁇ s ⁇ ttings of N, M and
  • the transmit-side equalizer 129 may be us ⁇ d to reduce signal distortion resulting from inductive and capacitiv ⁇ coupling of signals transmitt ⁇ d on n ⁇ ighboring signal paths; a type of equalization referred to as far-end cross-talk cancellation.
  • the output driver bank 131 includes additional output driv ⁇ rs to g ⁇ n ⁇ rat ⁇ ⁇ qualization signals bas ⁇ d on valu ⁇ s b ⁇ ing transmitt ⁇ d on signal paths that ar ⁇ adjacent or otherwise proximal to the signal path 122.
  • an equalizing signal having a polarity opposite that of an interfering neighboring signal is transmitted on the signal path 122, ther ⁇ by reducing the signal interf ⁇ r ⁇ nc ⁇ .
  • Th ⁇ numb ⁇ r of ⁇ qualizer taps ne ⁇ d ⁇ d for cross-talk cancellation within a given signaling system is dep ⁇ nd ⁇ nt on th ⁇ physical layout of signal paths relative to one another.
  • ⁇ xampl ⁇ in a syst ⁇ m in which signal paths 122 ar ⁇ arranged relativ ⁇ to on ⁇ anoth ⁇ r such that cross-talk int ⁇ rf ⁇ r ⁇ nc ⁇ is negligible (e.g., paths 122 are spaced apart, arranged in an orthogonal disposition (e.g., twisted pair), etc.), no equaliz ⁇ r taps may b ⁇ n ⁇ d ⁇ d for cross-talk cancellation.
  • on ⁇ or more equaliz ⁇ r taps may b ⁇ n ⁇ d ⁇ d for ⁇ ach adjacent pair of signal paths.
  • ⁇ qualiz ⁇ r taps are sel ⁇ ctively coupled to either pre-tap, post- tap or cross-talk cancellation data sources (i.e., primary value being transmitt ⁇ d on n ⁇ ighboring path).
  • ⁇ qualiz ⁇ r taps may be selectively configured, according to syst ⁇ m requirements, to provide eith ⁇ r t ⁇ mporal ⁇ qualization (i. ⁇ ., pr ⁇ -tap and/or post-tap ⁇ qualization) or cross-talk canc ⁇ llation.
  • Figure 6 illustrat ⁇ s a transmit d ⁇ vice 154 having circuitry for sel ⁇ cting b ⁇ tw ⁇ n temporal equalization and cross-talk cancellation data sources.
  • the transmit device 154 includes transmitters 152 t and 152 , each for transmitting data signals on a respectiv ⁇ signal path 122i and 122 2 .
  • R ⁇ sp ⁇ ctiv ⁇ sources of transmit data values (TX DATA1 and TX DATA2) are provided from other logic (not shown) within transmit d ⁇ vic ⁇ 154.
  • additional transmitters may b ⁇ provid ⁇ d in accordance with the number of signal paths 122 and/or th ⁇ number of sources of transmit data values.
  • Each of the transmitters 152 includes a transmit shift register (124 ls 124 2 ), output driver (121 1 , 121 2 ), post-tap data shift regist ⁇ r (120 1 ⁇ 120 2 ) and output driver bank (131 l5 131 2 ) that operate gen ⁇ rally as d ⁇ scribed in reference to Figure 3.
  • Each transmitt ⁇ r 152 additionally includes a tap data source selector (153 l5 153 2 ) having one or more multipl ⁇ x ⁇ rs for selectively coupling eith ⁇ r a local data value (e.g., a pre-tap or post-tap data value from corresponding transmit shift regist ⁇ r 124 or post-tap data shift register 120) or a remote data value (e.g., a primary value suppli ⁇ d from th ⁇ head of a transmit shift regist ⁇ r 124 of another transmitter, or a post-tap data value supplied from the post-tap data shift regist ⁇ r of anoth ⁇ r transmitter) to be the equalization tap data source.
  • a local data value e.g., a pre-tap or post-tap data value from corresponding transmit shift regist ⁇ r 124 or post-tap data shift register 120
  • a remote data value e.g., a primary value suppli ⁇ d from th ⁇ head of a transmit shift regist ⁇ r 124 of another transmitter,
  • multiplexer A within tap data source sel ⁇ ctor 153 ⁇ has a first input coupled to a storage el ⁇ ment within post-tap data shift register 120 ⁇ and a s ⁇ cond input coupl ⁇ d to th ⁇ output of transmit shift register 124 2 , and selects, according to a select signal SEL , ⁇ ith ⁇ r a post-tap data valu ⁇ within shift regist ⁇ r 120 l5 or th ⁇ r ⁇ mot ⁇ primary valu ⁇ output by shift register
  • Multipl ⁇ x ⁇ r J within tap data source sel ⁇ ctor 153i has a first input coupled to a storage element within the transmit shift regist ⁇ r 124 1 and a second input coupled to th ⁇ output of th ⁇ transmit shift r ⁇ gist ⁇ r 124 2 , and s ⁇ lects, according to a select signal SELu, either a pre-tap data value within the transmit shift regist ⁇ r 124 ls or th ⁇ r ⁇ mot ⁇ primary valu ⁇ to b ⁇ th ⁇ data tap source for an output driver within output driver bank 131 ⁇ .
  • additional multiplex ⁇ rs may b ⁇ provid ⁇ d within th ⁇ tap data source selectors 153 to select betwe ⁇ n local data valu ⁇ s (pre- or post-tap) and remote post-tap data values.
  • select signal SEL IK - Tap data source selector 153 2 similarly includes on ⁇ or more multiplexers to select between pre-tap, post-tap and or cross-talk cancellation data sources for output driver bank 131 2 .
  • output drivers within banks 131 may alternatively be used to generate temporal ⁇ qualization signals or cross-talk cancellation signals according to system ne ⁇ ds.
  • multiplexer A of data source sel ⁇ ctor 153 ⁇ may include one or more inputs to receive pre-tap data values from register 124j, one or more inputs to receive post-tap data values from post-tap register 120 ! , and/or one or more inputs to r ⁇ c ⁇ ive cross-talk canc ⁇ llation data valu ⁇ s (i. ⁇ ., r ⁇ mot ⁇ primary, pr ⁇ -tap and or post-tap valu ⁇ s from any numb ⁇ r of oth ⁇ r transmitt ⁇ rs 152).
  • ⁇ ach output driv ⁇ r within an output driv ⁇ r bank 131 may b ⁇ sourc ⁇ d by a multipl ⁇ x ⁇ r that s ⁇ l ⁇ cts b ⁇ tw ⁇ n any numb ⁇ r of pr ⁇ -tap, post-tap and/or cross-talk cancellation data sources. Also, not all output drivers within output driver banks 131 ne ⁇ d b ⁇ f ⁇ d by multipl ⁇ x ⁇ rs, but rather may be coupled to dedicated tap data sources.
  • the select signals, SEL ⁇ (including signals SEL !A ,
  • SEL U , SEL ⁇ K , ⁇ tc.) and SEL 2 ar ⁇ g ⁇ n ⁇ rat ⁇ d by a configuration circuit (not shown) within transmit device 151 or els ⁇ wher ⁇ in a signaling syst ⁇ m that includes transmit device 151.
  • the configuration circuit may be pre- programm ⁇ d or may be programm ⁇ d at system start-up, for example, by a controller similar to controller 141 of Figure 3.
  • selectiv ⁇ -tap transmit-sid ⁇ pr ⁇ mphasis may b ⁇ us ⁇ d to cancel or reduce interference between signals transmitted in the same direction on neighboring or oth ⁇ rwis ⁇ proximal signal lin ⁇ s (i. ⁇ ., far- ⁇ nd cross-talk).
  • S ⁇ l ⁇ ctiv ⁇ -tap r ⁇ c ⁇ ive-side ⁇ qualization may similarly be used to reduce interference betw ⁇ n outgoing and incoming transmissions on proximal signal lin ⁇ s; int ⁇ rf ⁇ r ⁇ nc ⁇ r ⁇ f ⁇ rr ⁇ d to h ⁇ rein as near- ⁇ nd cross-talk.
  • the transmit device 118 includes an output driver 121, transmit shift register 124, post-tap data shift regist ⁇ r 120, and output driver bank 131, all of which operate gen ⁇ rally as described above in ref ⁇ r ⁇ nc ⁇ to transmit device 115 of Figure 3 to ⁇ nabl ⁇ g ⁇ n ⁇ ration of an ⁇ qualiz ⁇ d transmit signal (TX OUT) on signal path 122 ⁇ .
  • the transmit device 118 may additionally include sel ⁇ ct circuitry as described in ref ⁇ r ⁇ nc ⁇ to Figur ⁇ 6 to enable sel ⁇ ction of various equalization data sources.
  • Th ⁇ receiv ⁇ d ⁇ vic ⁇ 119 includes a sampling circuit 123, buffer 132, tap sel ⁇ ct circuit 137, tap select logic 139 and equalization circuit (e.g., included within the sampling circuit 123 or implement ⁇ d as an output driv ⁇ r 140) to r ⁇ c ⁇ iv ⁇ an incoming signal (RX IN) on signal path 122 2 .
  • RX IN incoming signal
  • TX OUT transmit signal
  • pre-tap, primary and post-tap data values used to gen ⁇ rat ⁇ th ⁇ TX OUT signal i.e., from transmit shift register 124 and post-tap data shift regist ⁇ r 120
  • th ⁇ tap s ⁇ l ⁇ ct logic 139 may s ⁇ lect, as tap values for the r ⁇ c ⁇ iv ⁇ r ⁇ qualization circuit, any combination of the r ⁇ ceiv ⁇ d data valu ⁇ s stor ⁇ d within buff ⁇ r 132, and th ⁇ pr ⁇ - tap, post-tap and primary data valu ⁇ s us ⁇ d to g ⁇ nerate th ⁇ TX OUT signal.
  • tap sel ⁇ ct logic 139 outputs a control signal to th ⁇ tap s ⁇ l ⁇ ctor 137 to control tap data source selection according system configuration information.
  • the pre-tap, post-tap and/or primary data values may b ⁇ s ⁇ l ⁇ ct ⁇ d with the polarity necessary to achiev ⁇ a subtractiv ⁇ effect on th ⁇ corresponding cross-talk interf ⁇ r ⁇ nc ⁇ (the appropriate polarity being establish ⁇ d or controlled within the buffer 132 or receiver equalizing circuit), thereby enabling reduction of near- ⁇ nd cross-talk int ⁇ rference.
  • the tap select circuit 137 is shown in Figure 7, any numb ⁇ r of tap select circuits may be used.
  • FIG. 8 illustrates a transceiver device 151 that may be coupled to either or both sides of signaling path 122, and that includ ⁇ s both an ⁇ qualizing transmitt ⁇ r 115 and an ⁇ qualizing receiv ⁇ r 116 according to embodiments described herein (transmitters and r ⁇ ceiv ⁇ rs according to th ⁇ cross-talk canceling embodim ⁇ nts d ⁇ scribed in reference to
  • Th ⁇ transc ⁇ iv ⁇ r d ⁇ vic ⁇ 151 additionally includ ⁇ s an application logic circuit 154 to provide transmit data to the ⁇ qualizing transmitter 115 and to rec ⁇ iv ⁇ sampl ⁇ d data from the equalizing rec ⁇ iv ⁇ r 116.
  • Th ⁇ application logic circuit 154 also outputs an ⁇ nabl ⁇ signal
  • the transceiv ⁇ r 155 includes a transmit shift regist ⁇ r 124, output driv ⁇ r 121, post-tap data shift r ⁇ gist ⁇ r 120 and output driv ⁇ r bank 131 (which may include output drivers sourced by pre- tap data valu ⁇ s, cross-talk cancellation values, or by tap data source sel ⁇ ctors as d ⁇ scrib ⁇ d in reference to. Figure 6), all of which operat ⁇ g ⁇ nerally as described in reference to Figure 3 to output, during a giv ⁇ n transmit interval, a primary signal and corresponding equalization signal onto signal path 122.
  • the transceiv ⁇ r also includes a sampling circuit 123, buffer circuit 132, tap selector 156 and tap select logic 157.
  • the sampling circuit 123 samples data signals transmitted on signal path 122 (i.e., by a remote transmitter or transceiver) and stores the corresponding data values in buffer circuit 132.
  • the tap selector 156 is coupled to the buffer circuit 132 as well as the transmit shift regist ⁇ r (including th ⁇ h ⁇ ad of th ⁇ transmit shift register which contains the primary data value) and the post-tap data shift regist ⁇ r 120, and th ⁇ refore enables any combination of received data values (i. ⁇ ., from buff ⁇ r 132) and pre-tap, primary and/or post-tap transmit data values to be. selected as source data taps within an equalizing circuit (i.e., output driver 140 or an equalizing circuit within the sampling circuit 123).
  • the tap sel ⁇ ct logic 157 outputs a control signal to the tap s ⁇ lector according syst ⁇ m configuration information
  • the tap s ⁇ l ⁇ ct logic 157 and tap s ⁇ lector 156 operate to sel ⁇ ct tap valu ⁇ s from the transmit shift register 124, data tap shift regist ⁇ r 120, and/or buff ⁇ r circuit 132 in any combination. Th ⁇ selected tap values are then used to source equaliz ⁇ r taps within an equalizing output driver 140 or an equalizing circuit within sampling circuit 123.
  • the transceiver embodim ⁇ nts d ⁇ scrib ⁇ d in reference to Figures 8 and 9 include an enabl ⁇ lin ⁇ to alternat ⁇ ly enable transmission or reception of signals
  • the enable line may be omitted and transmission and reception of signals may occur simultaneously (i. ⁇ ., simultan ⁇ ous bi-dir ⁇ ctional signaling).
  • multilevel signaling may be used to enable an outgoing signal to b ⁇ transmitt ⁇ d simultaneously (in ⁇ ff ⁇ ct, superimposed on) an incoming signal.
  • th ⁇ receive circuit may subtract the locally transmitted signal from an incoming signal to recover only the desired portion (i.e., r ⁇ mot ⁇ ly transmitted portion) of the incoming signal.
  • the locally transmitt ⁇ d signal may produce dispersion- and reflection-type ISI that may b ⁇ compensated by an equalizing rec ⁇ iv ⁇ r having, as an ⁇ xample, the configuration of Figure 9, but omitting the enabl ⁇ line.
  • th ⁇ transmit shift register 124 and post- tap data register 120 may be sel ⁇ ct ⁇ d by tap s ⁇ lect circuit 156 to source tap data values for equalization of low- and/or high-lat ⁇ ncy distortions resulting from th ⁇ local signal transmission (i. ⁇ ., by output driver 121).
  • the post-tap data register may need to be extended (i.e., have an increased number of entri ⁇ s) to ⁇ nable reduction of high-latency distortions resulting from the local signal transmission.
  • the rec ⁇ iv ⁇ circuit tap s ⁇ l ⁇ ctions, controlled by tap s ⁇ lect logic 157, may b ⁇ determin ⁇ d ⁇ mpirically or during run-tim ⁇ , for ⁇ xampl ⁇ , by using th ⁇ m ⁇ thods and circuits described below for determining equalization tap latencies, weights and polarities.
  • Figure 10 illustrat ⁇ s an ⁇ x ⁇ mplary buffer 159 that may be used within the receiver 116 of Figure 3 and that includes both a serial shift register 161 as w ⁇ ll as a numb ⁇ r (K) of parall ⁇ l-load r ⁇ gist ⁇ rs 165rl65 ⁇ .
  • a serial shift register 161 as w ⁇ ll as a numb ⁇ r (K) of parall ⁇ l-load r ⁇ gist ⁇ rs 165rl65 ⁇ .
  • a newly sampl ⁇ d data value 160 is loaded from sampling circuit 123 into the shift register 161.
  • the shift register is formed by N storage elements (depicted as flip-flops 163]-163H, though latches or other types of storage el ⁇ m ⁇ nts may b ⁇ us ⁇ d) coupl ⁇ d in daisy chain fashion such that, as th ⁇ n ⁇ wly sampl ⁇ d value 160 is loaded into the first storag ⁇ ⁇ l ⁇ ment 163 ! in the shift register 161, the contents of each storage element 163 except the last (163N) is shifted to th ⁇ n ⁇ xt storag ⁇ elem ⁇ nt in th ⁇ chain in response to a receive clock signal (RCLK).
  • N storage elements depicted as flip-flops 163]-163H, though latches or other types of storage el ⁇ m ⁇ nts may b ⁇ us ⁇ d
  • the symbol latency of the input value 160 is i-1
  • the symbol latencies of the outputs of the remaining storage elem ⁇ nts 163 in the shift regist ⁇ r 161 are, from left to right, i+1, i+2, ..., and i+(N-l), r ⁇ sp ⁇ ctiv ⁇ ly.
  • a shift counter 169 (which may be included within or separat ⁇ from buffer circuit 159) maintains a count of the number of data values shifted into the shift register 161, incrementing the shift count in response to each transition of RCLK.
  • the shift counter 169 asserts a load signal 164 (LD) upon reaching a count that corresponds to a full shift regist ⁇ r, then rolls the shift count back to a starting valu ⁇ .
  • the load signal 164 is routed to strobe inputs of storag ⁇ el ⁇ m ⁇ nts within th ⁇ parallel-load registers 165, enabling parall ⁇ l load register 165 ! to be loaded with the contents of the shift register, and enabling each of the parallel-load regist ⁇ rs 165 2 -165 to b ⁇ load ⁇ d with the content of a preceding one of the parallel load regist ⁇ rs (i.e.,
  • the symbol latency of a data value stored within any of th ⁇ parall ⁇ l-load r ⁇ gist ⁇ rs 165 is d ⁇ p ⁇ nd ⁇ nt on how many data valu ⁇ s hav ⁇ been shifted into the shift register since the last assertion of the load signal 164; a measure indicated by the shift count.
  • the shift count is 1, indicating that the load signal 164 was asserted at the immediately preceding edge of RCLK
  • the content of storage el ⁇ m ⁇ nt 167i of parall ⁇ l- load register 165i has a symbol latency of i+1 (i. ⁇ ., on ⁇ symbol tim ⁇ old ⁇ r than th ⁇ content of storage ⁇ lement 163 ⁇ of the shift regist ⁇ r).
  • Wh ⁇ n the next valu ⁇ is shifted into th ⁇ s ⁇ rial shift register 161, th ⁇ contents of the parallel r ⁇ gist ⁇ rs 165 remain unchanged, meaning that th ⁇ latency of each data value stored in th ⁇ parall ⁇ l registers 165 is increased by a symbol time.
  • the content latency (i.e., lat ⁇ ncy of a stor ⁇ d valu ⁇ ) of a given storag ⁇ ⁇ l ⁇ m ⁇ nt within on ⁇ of parall ⁇ l regist ⁇ rs 165 is d ⁇ pendent upon the value of the shift count. Ref ⁇ rring to parall ⁇ l load r ⁇ gist ⁇ r 165 l5 for example, the content latency of storag ⁇ ⁇ l ⁇ ment 167 !
  • the content lat ⁇ ncy of storag ⁇ ⁇ l ⁇ ment 167 2 is i+SC+1, and so forth to storage el ⁇ m ⁇ nt 167 N , which has a content latency of i+(N-l)+SC.
  • the content latencies of storage el ⁇ m ⁇ nts within the parallel-load registers 165 2 -165 ⁇ are similarly dependent upon the shift clock value, SC, but are increased by N for each parall ⁇ l load away from register 165 ⁇ .
  • the content latency of th ⁇ leftmost storage el ⁇ m ⁇ nt within r ⁇ gist ⁇ r 165 2 is i+N+SC
  • the content latency of the leftmost storage el ⁇ m ⁇ nt within register 165 ⁇ is i+(K-l)N + SC.
  • the content latencies of the storage el ⁇ m ⁇ nts within registers 165 -165 ⁇ are incrementally relat ⁇ d to th ⁇ content latency of th ⁇ corresponding leftmost storag ⁇ ⁇ l ⁇ m ⁇ nt in th ⁇ sam ⁇ manner that the content latencies of storage el ⁇ ments 167 2 -167 N relate to the content latency of storage el ⁇ m ⁇ nt 167].
  • the desired data value is located at a shift- count-depend ⁇ nt bit position within one of the parallel-load regist ⁇ rs 165.
  • N the desired data valu ⁇ is locat ⁇ d within register 165] at bit position X-SC, as indicated at 181.
  • the symbol latency of storage el ⁇ ment 167 N is increased, and the storage el ⁇ m ⁇ nt one position to the left of storage element 167 N (i. ⁇ ., 167N- I ) now contains th ⁇ data valu ⁇ having the desired symbol latency and is therefore selected to supply the data value to an equalizer tap.
  • th ⁇ n X is compared with 2N+SC at 183. If X is less than 2N+SC, then parallel-load regist ⁇ r 165 2 contains the desired tap value at bit position X-N-SC as indicated at 185. The decision flow continues in this manner to 187 at which point X is compared with (K-1)N+SC. If X is l ⁇ ss than (K-1)N+SC, th ⁇ n parall ⁇ l-load r ⁇ gist ⁇ r 165 . ! contains the desired tap value at position X-(K-1)N - SC as indicated at 189.
  • Figure 12 illustrates an exemplary embodim ⁇ nt of a tap select circuit for sel ⁇ cting a tap valu ⁇ (DATA, + ⁇ ) from a buff ⁇ r circuit 210 that includes an eight-bit serial shift regist ⁇ r 161 and two ⁇ ight bit parall ⁇ l-load registers 165 ls
  • the data value in th ⁇ first (leftmost) storage el ⁇ m ⁇ nt within the shift register 161 has a symbol latency of one and that the dead range is four symbol times (i.e., the leftmost four storage el ⁇ m ⁇ nts within th ⁇ shift register 161 are not used to source tap values to the equalizer).
  • the data values stored in parallel-load register 165 ! will have symbol latencies ranging from 2-9 symbol tim ⁇ s, and th ⁇ data valu ⁇ s stor ⁇ d in parall ⁇ l-load r ⁇ gist ⁇ r 165 2 will hav ⁇ symbol lat ⁇ ncies ranging from 10-17 symbol times.
  • refactions (or other distortions) appearing at the receiver input betw ⁇ en 5 and 17 symbol times after the corresponding primary signal may be reduced by sel ⁇ cting data values having corresponding symbol latencies from the buffer circuit 210 to drive the rec ⁇ iv ⁇ -sid ⁇ ⁇ qualiz ⁇ r taps (i.e., to be tap data values).
  • Multiplexers 205, 207j and 207 2 are responsiv ⁇ to low order bits of a latency value 200 (X[4:0]) to select tap positions within the shift register 161, parallel-load regist ⁇ r 165 l5 and parallel-load r ⁇ gist ⁇ r 165 2 .
  • Th ⁇ lat ⁇ ncy valu ⁇ 200 is additionally suppli ⁇ d to a s ⁇ lect logic circuit 201 which generates a register select signal, SEL[1:0], to sel ⁇ ct one of th ⁇ thr ⁇ r ⁇ gist ⁇ rs 161, 165 ⁇ and 165 2 within th ⁇ buff ⁇ r circuit 210 to source the tap data value, DATAj+ ⁇ .
  • Th ⁇ least significant two bits of the latency value 200 are input to multiplex ⁇ r 205 to s ⁇ lect on ⁇ of th ⁇ four s ⁇ l ⁇ ctabl ⁇ data values within the serial shift regist ⁇ r 161.
  • Th ⁇ l ⁇ ast three significant bits of the latency value 200 are input to a subtract circuit 203 which subtracts the shift count 202 from the thre ⁇ -bit lat ⁇ ncy valu ⁇ to produce a tap select value for the parallel-load regist ⁇ rs 165 1? 165 .
  • th ⁇ s ⁇ lect value 200 corresponds to a desired symbol latency as shown in Table 1 below, and the shift count 202 is encoded in a three-bit value, SC[2:0], as shown in Table 2 below.
  • SC[2:0] 000
  • th ⁇ l ⁇ ftmost bit positions within r ⁇ gist ⁇ rs 165 hav ⁇ symbol lat ⁇ nci ⁇ s 9 and 17 wh ⁇ n th ⁇ shift count is eight.
  • Figure 13 illustrates an exemplary embodim ⁇ nt of th ⁇ s ⁇ l ⁇ ct logic 201 of Figur ⁇ 12.
  • the select logic 201 includes a comparator circuit 215 to compare the latency select value 200 with N (th ⁇ siz ⁇ , in bits, of each of registers within buffer circuit 210), a summing circuit 217 to sum the shift count 202 with N (ther ⁇ by gen ⁇ rating SC+N), and a comparator circuit 219 to compare the latency select value 202 with the output of the summing circuit 217.
  • the summing circuit and comparators may have numerous implementations depending on the size of N and the number of bits used to form the latency select value 200 and shift count 202.
  • the sum of the shift count and N may be formed simply by including an additional bit in parallel with the thre ⁇ shift count bits, the additional bit forming the most significant bit of the resulting sum (i.e., sum[3]) while SC[2:0] form the less significant thre ⁇ bits of th ⁇ sum (i. ⁇ ., sum[2:0]).
  • the comparator 215 may be impl ⁇ m ⁇ nt ⁇ d by a NOR gat ⁇ having inputs coupl ⁇ d to X[4] and X[3].
  • th ⁇ X ⁇ N output will be high only if both X[4] and X[3] are low.
  • Numerous other logic circuits may be used to implement the sel ⁇ ct logic circuit 201 of Figure 12 in Var ⁇ ⁇ mbodiments. More generally, specific numbers of bits and registers have be ⁇ n described for purpose of example only. Alternativ ⁇ embodiments may included ⁇ diff ⁇ r ⁇ nt numbers of regist ⁇ rs having various siz ⁇ s, and latency select values and shift count values having different sizes.
  • any circuit for sel ⁇ cting a data value based on a latency sel ⁇ ct value may alternatively be used without departing from the spirit and scope of the pres ⁇ nt inv ⁇ ntion.
  • Figure 14 illustrat ⁇ s a g ⁇ n ⁇ raliz ⁇ d sel ⁇ ct circuit 230 that may b ⁇ us ⁇ d to select Q tap values from the buff ⁇ r circuit 210 of Figur ⁇ 12.
  • Th ⁇ s ⁇ l ⁇ ct circuit 230 includes a switch matrix 231 and tap select logic 235.
  • each of the possibl ⁇ tap data sources within the buffer circuit 210 (i.e., the rightmost four bits within shift register 161 and all the bits within the parallel-load registers 165) are coupled to respective column lines 234 of the switch matrix 231, and each of the Q tap outputs are coupled to resp ⁇ ctiv ⁇ row lin ⁇ s 236 of th ⁇ switch matrix 231.
  • a switch clement 233 is provid ⁇ d at ⁇ ach row-column int ⁇ rs ⁇ ction to enable the tap data source for the column to be selectively coupled to the tap output for the row.
  • each enable signal includes Q component signals coupled respectively to the Q switch elements within a corresponding column.
  • the column 1 data value i.e., th ⁇ data value stored in shift regist ⁇ r position 4
  • sel ⁇ ct signal E 1 [Q:1] 100..00.
  • E j [i] l for each column data value, j, to be coupled to a tap output, i.
  • the Q tap outputs may b ⁇ s ⁇ l ⁇ ct ⁇ d from among th ⁇ complete range of data values stored within buffer circuit 210.
  • the sel ⁇ ct logic includes combinatorial logic that operates as d ⁇ scribed in ref ⁇ rence to Figure 10 to gen ⁇ rat ⁇ ⁇ ach ⁇ nabl ⁇ signal.
  • a stat ⁇ machine or other processing logic may be used to generate the enable signals in accordance with the latency selection values and shift count.
  • FIG. 15 illustrat ⁇ s an ⁇ mbodim ⁇ nt of a switch element 233 that may be used within th ⁇ switch matrix 231 of Figur ⁇ 14.
  • Th ⁇ switch ⁇ l ⁇ ment includes a transistor 235 having source and drain terminals coupled betwe ⁇ n th ⁇ i th row lin ⁇ 236; (TAP;) and th ⁇ j th column line 235 j (DATAj) of the switch matrix, and a gate t ⁇ rminal coupl ⁇ d to r ⁇ c ⁇ iv ⁇ the i th component signal of enabl ⁇ signal j (i. ⁇ ., E j [i]).
  • transistor 235 is switched on to couple the s ⁇ lected data source to the tap output.
  • Other types of switching el ⁇ ments may b ⁇ us ⁇ d in alt ⁇ rnati ve ⁇ mbodim ⁇ nts .
  • th ⁇ tap values selected by the tap sel ⁇ ct logic 139 and s ⁇ l ⁇ ct circuit 128 may be used in a number of different equalizing circuits to counteract distortion ev ⁇ nts.
  • an equalizing output driver 140 is coupled in parallel with the sampling circuit 123 to drive an equalizing signal back onto the signal path 122 during each symbol reception interval (i.e., symbol time during which a valid symbol is pres ⁇ nt at the input of the receiver).
  • symbol reception interval i.e., symbol time during which a valid symbol is pres ⁇ nt at the input of the receiver.
  • Figure 17 illustrat ⁇ s th ⁇ r ⁇ c ⁇ iv ⁇ circuit of Figure 16 in greater detail.
  • the sampling circuit 123 may include any number of preamplifiers 240 ! -240 N coupled in series with a sampler 241.
  • the sampler 241 may be any type of circuit for det ⁇ cting th ⁇ level of an input signal, including but not limited to a latching circuit that latches the signal level in response to a rising or falling clock edg ⁇ , or an integrating circuit that integrat ⁇ s the input signal over a finite period of time (e.g., a symbol time or portion of a symbol time).
  • Th ⁇ ⁇ qualizing output driv ⁇ r 140 may b ⁇ coupled to the signal path 122 (i.e., the input of the first pr ⁇ amplifi ⁇ r 240 ⁇ ) or, alternatively, to the output of any of the preamplifi ⁇ rs 240. Also, as discussed below, the output driv ⁇ r 140 may be coupl ⁇ d to the sampler 241 to affect the sampling operation. In one embodim ⁇ nt, th ⁇ ⁇ qualizing output driv ⁇ r 140 of Figures 15 and
  • EQCLK equalizer clock signal
  • the equaliz ⁇ r clock signal may b ⁇ furth ⁇ r offs ⁇ t from th ⁇ r ⁇ c ⁇ iv ⁇ clock signal as shown by arrow 245 to account for the time required for the ⁇ qualization data (i. ⁇ ., selected tap values) to propagat ⁇ through the equalizing output driver 140 or other equalizing circuit.
  • Figure 19 illustrates a current-sinking output driver 250 that may be us ⁇ d to impl ⁇ m ⁇ nt th ⁇ equalizing output driver 140 of Figure 16.
  • the output driver includes a plurality of sub-driver circuits 251 ⁇ 251 ⁇ each sub-driver circuit 251 including a current source 257, clocking transistor 255 and data tap transistor 253 coupled in seri ⁇ s between an output node 254 and a ref ⁇ r ⁇ nc ⁇ voltage (ground in this exampl ⁇ ).
  • Control terminals (e.g., gate terminals) of the data tap transistors 253 of the sub-driver circuits 251 ar ⁇ coupl ⁇ d to r ⁇ c ⁇ ive resp ⁇ ctive data tap values (designat ⁇ d EQD ⁇ -EQDN in Figure 19) from a sel ⁇ ct circuit, control terminals of the current sources 257 are coupled to resp ⁇ ctiv ⁇ tap w ⁇ ight valu ⁇ s, EQW P EQW N , and control terminals of the clocking transistors are coupled in common to r ⁇ c ⁇ ive th ⁇ ⁇ qualiz ⁇ r clock signal, EQCLK.
  • th ⁇ tap w ⁇ ights provid ⁇ d to th ⁇ output driv ⁇ r 250 or oth ⁇ r ⁇ qualizing circuits described herein may be pr ⁇ d ⁇ t ⁇ rmin ⁇ d valu ⁇ s, or may be determin ⁇ d dynamically according to th ⁇ l ⁇ v ⁇ l of the distortions to be reduced. Because the sub-driver circuits 251 are coupled in parallel to the output node, the overall equalization signal gen ⁇ rat ⁇ d by output driver 250 during a given symbol time is the sum of contributions from the individual sub-driver circuits 251.
  • output driver 250 outputs an equalization signal only when the equalizer clock signal is high (i.e., ev ⁇ n phas ⁇ s of EQCLK).
  • An additional instance of output driver 250 may be provided to output an equalization signal when a complem ⁇ nt ⁇ qualiz ⁇ r clock signal (i.e., /EQLCK) is high.
  • Figure 20 illustrat ⁇ s an embodiment of a push-pull type of sub-driver circuit 260 that may be used within an ⁇ qualizing output driver inst ⁇ ad of th ⁇ pull-down sub-driv ⁇ r circuits 251 described in ref ⁇ r ⁇ nc ⁇ to Figure 19.
  • current is eith ⁇ r sourc ⁇ d or sunk via the driver output according to the state of the tap data value, EQDi.
  • Th ⁇ sub- driv ⁇ r circuit 260 includes switching transistors 263 and 265, and AND gate 261.
  • a first input of the AND gate 261 is coupled to receiv ⁇ the tap data value, EQDj, and a s ⁇ cond input of th ⁇ AND gat ⁇ 261 is coupl ⁇ d to a clock line to receiv ⁇ th ⁇ ⁇ qualiz ⁇ r clock signal, EQCLK.
  • Th ⁇ output of th ⁇ AND gat ⁇ 261 is coupled to the gate terminals of transistors 263 and 265 such that, during each high phase of the equalizer clock signal, th ⁇ tap data valu ⁇ is pass ⁇ d to th ⁇ gat ⁇ t ⁇ rminals of transistors 263 and 265 to ⁇ stablish th ⁇ output stat ⁇ of th ⁇ sub-driv ⁇ r circuit 260.
  • ⁇ v ⁇ ry other half cycle of the equalizer clock signal constitutes an output enable interval for the sub-driver circuit 260. If the tap data value, EQDj, is high during a given output enable interval, transistor 265 is switched on, causing th ⁇ sub-driv ⁇ r circuit 260 to sink current via the output nod ⁇ (OUTj). Conversely, if the tap data value is low during the output enable interval, transistor 263 is switched on to source current via the output nod ⁇ .
  • a pull-down biasing circuit ( ⁇ .g., current source) may be coupled between the pull-down data tap transistor 265 and ground, and a pull-up biasing circuit may be coupled betw ⁇ n the pull-up data tap transistor 263 and the supply reference voltage (e.g., V DD ) to enable weighted control of the current sourcing and sinking strength of the push-pull sub-driv ⁇ r circuit 260.
  • V DD supply reference voltage
  • an additional instance of the sub-driver circuit 260 may be provided with a complement equalizer clock signal (/EQCLK) and complem ⁇ nt tap data valu ⁇ (/EQDj) being input to AND gate 261 to ⁇ nable the sub-driver circuit 260 to output an equalizing signal during the alternat ⁇ half cycle of the equalizer clock signal.
  • Figure 21 illustrates another embodim ⁇ nt of a sub-driver circuit 275 that may be used within an equalizing output driver.
  • the sub-driver circuit 275 includes a differential transistor pair 277 having control terminals coupled to outputs of AND gates 261 ⁇ and 261 2 , respectively.
  • a tap data value (EQDi) and an equaliz ⁇ r clock signal (EQCLK) are input to AND gate 261 ⁇
  • a complem ⁇ nt of th ⁇ tap data valu ⁇ (/EQDj) and th ⁇ equalizer clock signal are input to AND gate 261 2 -
  • the tap data value and complement tap data value are applied to respective inputs of the differential pair 277 during ev ⁇ ry other half cycle of the equalizer clock signal.
  • Output nodes of the differential pair 277 are pulled up through resp ⁇ ctiv ⁇ r ⁇ sistiv ⁇ loads 283 (R), and source terminals of the differential pair are coupled to ground via a current source 281.
  • the resistiv ⁇ loads 283 may b ⁇ , for example, termination el ⁇ ments coupled to th ⁇ signal path (not shown) rather than resistive ⁇ l ⁇ ments included within the sub-driver circuit 275. Accordingly, the sub-driver circuit 275 is enabled, during ev ⁇ ry other half cycle of the equalizer clock signal, to output a differential ⁇ qualizing signal on output nod ⁇ s OUT,- and /OUT; in accordance with the complem ⁇ ntary tap data valu ⁇ s, EQDj and /EQDi.
  • a counterpart instance of sub-driver circuit 275 may be provided to generat ⁇ a diff ⁇ rential equalizing signal during the alternate half clock cycle of the equaliz ⁇ r clock signal.
  • the current source 281 is controlled by the tap weight value, EQW,-, in the manner described in reference to Figure 19, though different weighting schemes may be used in alternative embodim ⁇ nts (e.g., using weight-bias ⁇ d pull-up ⁇ l ⁇ m ⁇ nts in place of resistive el ⁇ m ⁇ nts 283).
  • Figure 22 illustrates an Var ⁇ typ ⁇ of ⁇ qualizing circuit 290 that may b ⁇ us ⁇ d in ⁇ mbodim ⁇ nts of th ⁇ inv ⁇ ntion.
  • ⁇ qualization is p ⁇ rform ⁇ d in conjunction with preamphfication of th ⁇ incoming signal, and therefore affects the level of preamphfication applied to th ⁇ incoming signal. That is, th ⁇ ⁇ qualizing circuit
  • Equalizing circuit 290 includes a differential amplifier 294 formed by differential transistor pair 291, biasing current source 292 and resistive loads
  • output lines P O U T and /P OUT are coupled to input terminals of a differential amplifier within a sampling circuit so that amplifier 294 eff ⁇ ctively forms a first stage in a two-stage amplifier (i.e., amplifier 294 is a preamplifier).
  • Equalizing circuit 290 additionally includes a level shifting circuit 296 coupled to the differ ⁇ ntial amplifier 294 to provide preamplifi ⁇ r equalization.
  • the lev ⁇ l shifting circuit 296 includes a pair of sub-circuits 298 1 and 298 2 ⁇ ach coupled betw ⁇ en a respective one of the diff ⁇ rential amplifier outputs
  • 298 includes a respective plurality of data tap transistors (295 ! -295N and 297 ! -
  • each of the data tap transistors 295 is sized (e.g., by width-length ratio) to achieve a respective tap weight EQ N -EQWi.
  • each data tap value may be coupled to the control terminal of a sel ⁇ ct ⁇ d on ⁇ of th ⁇ data tap transistors 295 according to the desir ⁇ d tap w ⁇ ight.
  • Th ⁇ transistors 297 are similarly weighted and therefore allow coupling of the complem ⁇ nt data tap valu ⁇ s according to desired tap weights.
  • the weights of the individual data tap transistors 295 (and 297) may b ⁇ incr ⁇ m ⁇ ntally r ⁇ lat ⁇ d (i.e., EQW !
  • the clocking transistor 299 is switched on during every other half cycle of th ⁇ equalizer clock signal to enable the operation of the subcircuits 298.
  • the subcircuits 298 operate to increas ⁇ or d ⁇ crease the difference between the pr ⁇ amplifi ⁇ d output signals (or ⁇ v ⁇ n change the polarity of th ⁇ diff ⁇ rence) by drawing more current from one of the preamplifier output lines (P OUT or /P OUT ) than the other in accordance with the sel ⁇ ct ⁇ d data tap valu ⁇ s.
  • the subcircuits 298 act to differentially shift the level of the preamplified output signal generated by differential amplifier 294.
  • An additional instance of the equalizing circuit 290 may be provided to enable preamplifier equalization during th ⁇ alternate half cycl ⁇ of th ⁇ ⁇ qualiz ⁇ r clock signal.
  • Figure 23 illustrates an alternative lev ⁇ l shifting circuit 305 that may be substituted for circuit 296 of Figure 22.
  • circuit 305 differential pairs of data tap transistors 307 307 N are coupled to output lines POUT and /POUT in the same manner as in circuit 296, but instead of sizing the data tap transistors to achieve tap weighting, tap weighted current sources 311 ! -3 H N are coupled in series with the diff ⁇ r ntial pairs of data tap transistors 307 ! -307 N , respectively.
  • current source 31 ⁇ is controlled by (i.e., draws a bias current according to) weight value EQWi and is coupl ⁇ d via clocking transistors 309 ! to data tap transistors 307].
  • weight values EQW J -EQWN may be configured (e.g., via run-time calibration or production time programming) as necessary to establish a desir ⁇ d equalizing signal contribution from each differ ⁇ ntial pair of data tap valu ⁇ s 307.
  • An additional instance of th ⁇ equalizing circuit 290 may be provided to enable preamplifier equalization during the alternate half cycl ⁇ of th ⁇ ⁇ qualiz ⁇ r clock signal (i.e., by driving clocking transistors 309 with complement equalizing clock, /EQCLK).
  • Figure 24 illustrates anoth ⁇ r typ ⁇ of ⁇ qualizing circuit 320 that may be used in embodiments of the inv ⁇ ntion.
  • a l ⁇ vel shifting circuit 330 is coupled to low impedance inputs of a differ ⁇ ntial sampling circuit 328, and is us ⁇ d to affect the lev ⁇ l of th ⁇ input signal b ⁇ for ⁇ the sampled signal is captured.
  • the sampling circuit includes differential transistor pair 329 to precharg ⁇ input nodes S ⁇ N and /S ⁇ N according to th ⁇ state of a differential input (e.g., the output of a preamplifier 294 of Figure 22, or a differential data signal), during a first half cycle of the receive clock (which enabl ⁇ s clocking transistor 331).
  • a differential input e.g., the output of a preamplifier 294 of Figure 22, or a differential data signal
  • transistors 321 and 325 ar ⁇ switched on by the low-going rec ⁇ iv ⁇ clock signal, thereby enabling a cross-coupled latch formed by transistors 322, 323, 325 and 326 to latch the state of the precharg ⁇ d signal l ⁇ v ⁇ ls on nod ⁇ s S ⁇ N and /S ⁇ N -
  • the l ⁇ v ⁇ l shifting circuit 330 is similar to th ⁇ circuit 296 of Figur ⁇ 22 ⁇ xc ⁇ pt that clocking transistor 341 is ⁇ nabl ⁇ d by th ⁇ receive clock signal
  • RCLK equalizer clock signal
  • the equalizer clock signal being used to switch on switching transistors 335 ! -335 N and 339 1 -339 N during every other half cycle.
  • Data tap transistors 333 ! -333 N which are controlled by respective tap data values EQD ⁇ EQD N , are coupled in s ⁇ ries with the switching transistors 335]-335 N , resp ⁇ ctiv ⁇ ly.
  • data tap transistors 337 ! -337 N ar ⁇ coupl ⁇ d in s ⁇ ries with switching transistors 339 ! -339 N and are controlled by respective complem ⁇ nt tap data valu ⁇ s /EQD !
  • th ⁇ data tap transistors 333, 337 and switching transistors 335, 339 are sized to provide different current draws according to pred ⁇ t ⁇ rmin ⁇ d weights, EQW1-EQWN, thereby permitting different data taps to make different level-shifting contributions, hi one embodim ⁇ nt, for ⁇ xampl ⁇ , the switching transistors 335 and 339 are binary weighted such that, when switched on, the current draw through transistor pair 333 N /335 is 2 N-1 times the current through transistor pair 333 1 /335 1 (and the current draw through transistor pair 337 N /339 N is 2 _1 times the current through transistor pair 337 ⁇ 339 ! .
  • Other weighting schemes may also be used including, without limitation, thermom ⁇ t ⁇ r coding of high-gain transistor pairs, linear weighting schemes, or any combination of exponential (e.g., binary), linear and fhermomet ⁇ r coded weightings.
  • the ⁇ qualiz ⁇ r clock is phas ⁇ advanced relative to the receive clock signal such that transistors 337 and 339 are switched on in advance of clocking transistor 341.
  • transistors 333 and 337 ar ⁇ poised to shift the lev ⁇ l of th ⁇ sampling circuit input nodes, S I N and
  • sampling circuit input nodes S I N and /S ⁇ N are diff ⁇ rentially discharged according to the tap data values EQD ⁇ -EQD N , /EQD ! -/EQDN and the resp ⁇ ctive weights of transistors 333 and 337.
  • Cons ⁇ qu ⁇ ntly, th ⁇ signal l ⁇ v ⁇ ls at th ⁇ input nod ⁇ s, SIN and /S I N, of sampling circuit 328 ar ⁇ differentially shifted by the lev ⁇ l shifting circuit 330 to reduce static offsets in the incoming data signal (applied to control terminals of differential pair 329) caused by reflections or other distortions.
  • Figure 25 illustrates an Var ⁇ lev ⁇ l shifting circuit 342 that may b ⁇ substitut ⁇ d for circuit 330 of Figur ⁇ 24.
  • the level shifting circuit 342 includes data tap transistors 333, 33 and equaliz ⁇ r-clock- ⁇ nabl ⁇ d switching transistors 335, 339 coupl ⁇ d as described in reference to Figure 24. However, rather than being coupl ⁇ d to a clocking transistor 335, th ⁇ source terminals of transistors 335 I -335 N are coupled to ground via capacitive ⁇ lements 334r 334 N , respectively, and the source terminals of transistors 339 !
  • the data tap transistors 333, 337 and switching transistors 335, 339 have uniform sizes (i. ⁇ ., uniform weighting), and the capacitive elements 334, 338 have weighted capacitive values to permit a broad range of capacitances to be coupled to th ⁇ input nod ⁇ s of sampling circuit 328.
  • the capacitive el ⁇ ments 334 are implem ⁇ nt ⁇ d by source-to-drain coupled transistors and are binary w ⁇ ight ⁇ d
  • capacitive elem ⁇ nt 335 has twice the capacitance of capacitive el ⁇ m ⁇ nt 335 ⁇ , and capacitive elem ⁇ nt 335 N has 2 N"1 tim ⁇ s th ⁇ capacitance of capacitive ⁇ l ⁇ ment 335i.
  • Other weighting relationships e.g., thermom ⁇ t ⁇ r coding, linear, uniform, etc.
  • the data tap transistors 333, 337 and/or switching transistors 335, 339 may be weighted in Var ⁇ ⁇ mbodiments instead of
  • an incoming data signal may include two symbols per receiv ⁇ clock cycl ⁇ (sometimes referred to as a "double data rat ⁇ " signal), and ⁇ ach symbol may hav ⁇ more than two possibl ⁇ stat ⁇ s (i. ⁇ ., may have a signal lev ⁇ l falling within mor ⁇ than two distinct ranges of signals).
  • the receiv ⁇ clock frequency may be so high that by the time a sampled data value is loaded into th ⁇ buff ⁇ r circuit 132, the data value already has a latency of several symbol times. All thes ⁇ factors present challeng ⁇ s to th ⁇ buff ⁇ ring and s ⁇ l ⁇ ction of tap valu ⁇ s d ⁇ scrib ⁇ d in reference to Figure 3.
  • Figure 26 illustrat ⁇ s an equalizing rec ⁇ iver 350 according to an .embodiment of the inv ⁇ ntion.
  • Th ⁇ r ⁇ c ⁇ iv ⁇ r 350 includes a double data rate sampling circuit 351, shift regist ⁇ r 353, s ⁇ l ⁇ ct circuit 355 and equalizing output driv ⁇ r 357.
  • Th ⁇ sampling circuit 351 includes a pair of sub-circuits 36l! and 361 2 to sample the incoming data signal in response to rising edges in the receiv ⁇ clock (RCLK) and complement receive clock (/RCLK), resp ⁇ ctively. Falling clock edges may alternatively be us ⁇ d to tim ⁇ th ⁇ sampling instant.
  • sampling circuit 351 outputs ⁇ v ⁇ n phas ⁇ data (EVEN IN) and odd phas ⁇ data (ODD IN) to the shift r ⁇ gist ⁇ r 353 via signal lin ⁇ s 362i and
  • th ⁇ d ⁇ ad rang ⁇ is assum ⁇ d to b ⁇ fiv ⁇ symbol lat ⁇ nci ⁇ s (oth ⁇ r d ⁇ ad rang ⁇ s may be used) such that data values D ⁇ +5 -
  • the sel ⁇ ct circuit 355 includes N tap selectors, 365 ! -365 N , that sel ⁇ ct from among th ⁇ plurality of data valu ⁇ s stored within the shift regist ⁇ r 353 and output a s ⁇ l ⁇ cted tap data value to a respective one of N output sub-drivers 369 ! -369 N within the equalizing output driv ⁇ r 357.
  • Each of th ⁇ output sub-driv ⁇ rs 369 in turn, driv ⁇ s a component ⁇ qualizing signal onto th ⁇ signal path 122.
  • th ⁇ ⁇ qualizing output driv ⁇ r 357 may b ⁇ replaced by an equalizing circuit that operates within a preamplifi ⁇ r circuit (not shown in Figur ⁇ 26) or sampling circuit 351 as described above in ref ⁇ rence to Figures 17-20.
  • Figure 27 illustrates the shift register 353 and one of the tap selectors 365 of Figure 26 according to more specific embodiments.
  • Th ⁇ shift r ⁇ gist ⁇ r includes a pair of shift sub-circuits 383] and 383 2 to store ev ⁇ n phas ⁇ data and odd phase data, respectively.
  • ⁇ ach of the shift sub- circuits 383 includes a numb ⁇ r of storag ⁇ ⁇ l ⁇ m ⁇ nts 381 (e.g., latches) coupled in a daisy chain configuration (i.e., output to input) to enabl ⁇ an input data valu ⁇ to b ⁇ shift ⁇ d progressively from a first (i.e., leftmost) storage el ⁇ m ⁇ nt 381 in th ⁇ chain to a last (rightmost) storage ⁇ l ⁇ ment 381 in the chain.
  • a numb ⁇ r of storag ⁇ ⁇ l ⁇ m ⁇ nts 381 e.g., latches
  • a daisy chain configuration i.e., output to input
  • Each of the shift sub-circuits 383 is responsive to the rec ⁇ iv ⁇ clock and compl ⁇ m ⁇ nt r ⁇ c ⁇ iv ⁇ clock signals such that the contents of each shift sub-circuit 383 is shifted during each half clock cycle of the receiv ⁇ clock signal.
  • each even phase data value stored in shift sub-circuit 383 ⁇ is designated by a prime (i.e., ') in Figur ⁇ 27 to indicate that the data value was load ⁇ d synchronously with th ⁇ loading of a newly received odd phase data value into shift sub-circuit 383 2 .
  • a prime i.e., '
  • two instances of each odd phas ⁇ data valu ⁇ ar ⁇ stored in the shift sub-circuit 383 2 with the second instance of the odd phase data value being designat ⁇ d by a prim ⁇ to indicate that the data valu ⁇ was load ⁇ d synchronously with th ⁇ loading of a newly received even phase data value into shift sub-circuit 383 ! .
  • the shift sub-circuits 383 collectively contain a sequence of data values, A', B, C, D, E' F, G', H, that may be us ⁇ d to generate odd phase equalizing signals (i.e., driving an equalizing signal onto th ⁇ signal path or aff ⁇ cting signal levels within a preamplifier or sampling circuit during odd phase symbol reception), and a sequ ⁇ nc ⁇ of data valu ⁇ s, B', C, D', E, F', G, H', I, that may be us ⁇ d to g ⁇ n ⁇ rat ⁇ ⁇ v ⁇ n phas ⁇ ⁇ qualizing signals.
  • th ⁇ outputs of each of the storage elements 381 within shift sub- circuit 383 ! are coupled to respective inputs of an even tap data select circuit 387 ! within the tap selector 365, and the outputs of each of the storage el ⁇ m ⁇ nts 381 within th ⁇ shift sub-circuit 383 2 are coupled to respective inputs of an odd tap data s ⁇ lect circuit 387 2 within the tap selector 365.
  • the even and odd tap data sel ⁇ ct circuits 387 are responsive to a select signal, S[2:0], to output sel ⁇ ct ⁇ d tap data values from the even and odd phases sequences of data values, resp ⁇ ctively.
  • Th ⁇ s ⁇ lect signal may be generated, for example, by tap the select logic 139 described in ref ⁇ r ⁇ nc ⁇ to Figur ⁇ 3.
  • the output of the ev ⁇ n tap data s ⁇ l ⁇ ct circuit is clocked into a flip-flop
  • flip-flop 387 2 is clocked into a flip-flop 391 2 (or other storage elem ⁇ nt) so that, at any giv ⁇ n tim ⁇ , the output of flip-flop 391 2 is delayed by two symbol times relativ ⁇ to th ⁇ most lat ⁇ nt data valu ⁇ suppli ⁇ d to th ⁇ odd tap data select circuit
  • the flip-flops 391 eff ⁇ ctiv ⁇ ly increas ⁇ the latency of selected even and odd data tap values by two symbol times.
  • S ⁇ l ⁇ ct circuits 393i and 393 2 ar ⁇ provided to ext ⁇ nd th ⁇ ov ⁇ rall lat ⁇ ncy rang ⁇ of th ⁇ even and odd data tap sel ⁇ ctions within tap s ⁇ lector 365 by allowing s ⁇ lection of tap data directly from the ev ⁇ n and odd data inputs to the shift regist ⁇ r 353 (i. ⁇ ., EVEN IN and ODD IN) or from the outputs of flip-flops 391.
  • Sel ⁇ ct bit S[3] is provided ( ⁇ .g., by the tap select logic 139 of Figure 3) to select between the fast path data (i.e., connections 384 ! and 384 2 to the inputs of the sub shift circuits 383) and the selected data values stored in flip-flops 391.
  • Flip-flops 395 ⁇ and 395 2 (or other storage elem ⁇ nts) ar ⁇ provid ⁇ d to synchroniz ⁇ th ⁇ outputs of multiplexers 393 ⁇ and 393 2 with the receiv ⁇ clock and complement receive clock, resp ⁇ ctiv ⁇ ly.
  • ⁇ ven and odd data tap values, ETD and OTD, each having a range of latencies according to the depth of the shift sub-circuits 383 and the number of fast path taps (of which signal lines 384 ! and 384 are ⁇ xamples) are output to the equalizing circuit (not shown in Figure 27) to enabl ⁇ even and odd phase equalization of an incoming signal.
  • Figur ⁇ 28 illustrates an equalizing receiver 405 for receiving a double data rate, multilevel input signal according to an embodiment of the invention.
  • the receiver 405 includes a sampling circuit 407, shift register 411, select circuit 421 and ⁇ qualizing output driv ⁇ r 427.
  • Th ⁇ sampling circuit includes ev ⁇ n and odd phas ⁇ sampling sub-circuits 409i and 409 2 to capture even and odd phase samples of the incoming multilevel data signal and to generate a multi-bit output indicative of the sampled signal lev ⁇ l.
  • the incoming data signal has one of four possible signal lev ⁇ ls, ⁇ ach l ⁇ vel being defined by a distinct range of voltages.
  • each sample is resolved (i.e., by sampling sub-circuits 409) to a thermom ⁇ ter code in which bits A, B, and C hav ⁇ valu ⁇ s according to which of four voltage ranges the sampled signal level falls within.
  • bits A,B and C are set according to the following relationships betw ⁇ en the sampled signal, Vs, and high, middle and low threshold voltage l ⁇ v ⁇ ls:
  • schem ⁇ s may be us ⁇ d in alternative embodiments.
  • more or fewer threshold l ⁇ vels (and th ⁇ r ⁇ fore signal ranges) may be used, and current levels may be used to indicate signal lev ⁇ l instead of voltage levels.
  • each of th ⁇ bits is input to a respective one of shift registers 413 A -413 C and used to source a tap value for s ⁇ lection by a respective set of select circuits 422 A ⁇ 422Q (each sel ⁇ ct circuit including N tap s ⁇ l ⁇ ct s ⁇ l ⁇ ctors 423 ! -423N).
  • Each of th ⁇ shift r ⁇ gist ⁇ rs 413 and select circuits 422 operates generally as described in reference to Figures 21 and 22 to g ⁇ n ⁇ rate a set of selected tap values, 424 A -424 C - Corresponding tap values from within each set 424 are provided to a respective one of output sub-drivers 429 ! -429N within ⁇ qualizing output driv ⁇ r 427, wh ⁇ re th ⁇ y ar ⁇ used to gen ⁇ rat ⁇ a multi-level equalization signal.
  • the tap valu ⁇ s output by tap s ⁇ lector 423 1 within each of the select circuits 422 are input to output sub-driver 429 j of the ⁇ qualizing output driv ⁇ r 427.
  • the equalization signal gen ⁇ rat ⁇ d by a r ⁇ ceive-sid ⁇ equalizing output driver to b ⁇ driv ⁇ n onto th ⁇ signal path in phas ⁇ alignment with data eyes in the incoming data signal.
  • rec ⁇ iv ⁇ clock (or compl ⁇ m ⁇ nt r ⁇ c ⁇ iv ⁇ clock) may b ⁇ us ⁇ d to clock th ⁇ ⁇ qualizing output driv ⁇ r (or preamp or sampling circuit equalizer)
  • propagation delay through the equalizing driver tends to become significant in high frequ ⁇ ncy systems, producing undesired timing offset betw ⁇ n th ⁇ incoming data signal and th ⁇ ⁇ qualization signal, hi on ⁇ ⁇ mbodim ⁇ nt
  • clock data recovery circuitry within an equalizing receiver is used to gen ⁇ rat ⁇ an ⁇ qualization clock signal (EQCLK) that is phas ⁇ advanced relative to the receive clock signal according to the propagation delay (i.e., clock-to-Q) of an equalizing output driver.
  • EQCLK ⁇ qualization clock signal
  • the equalizing output driver outputs an equalization signal having the desired phase relation with the incoming data signal.
  • a d ⁇ sired phase relationship b ⁇ tw ⁇ n th ⁇ incoming data signal (RX DATA) and ⁇ qualization signal (EQ DATA) is achieved.
  • the equalization data tap is assumed to have a symbol latency of five symbol times, such that an equalization signal bas ⁇ d on received symbol A is transmitted by the equalizing output driver during the reception interval for symbol F.
  • the receiver 450 includes a sampling circuit 451, shift register 453, clock-data-recov ⁇ ry (CDR) circuit 457, application logic 455, tap data sel ⁇ ctor 461, signal generator 462, equalizer clock gen ⁇ rator 459, and ⁇ qualization data source sel ⁇ ctor 463.
  • An incoming data signal (DATA) on signal path 122 is sampled by the sampling circuit 451 in response to a rec ⁇ ive clock signal (RCLK). The samples are output to the shift register 453 where they are stored for parallel output to the application logic 455 and the CDR circuit 457.
  • DATA incoming data signal
  • RCLK rec ⁇ ive clock signal
  • th ⁇ receive clock signal includes multiple component clock signals including a data clock signal and its complem ⁇ nt for capturing even and odd phase data samples, and an ⁇ dge clock signal and complem ⁇ nt edg ⁇ clock signal for capturing ⁇ dg ⁇ samples (i.e., transitions of the data signal between successive data eyes).
  • the data and edg ⁇ sampl ⁇ s are shifted into the shift regist ⁇ r 453 and then supplied as parallel words (i. ⁇ ., a data word and an ⁇ dg ⁇ word) to a phas ⁇ control circuit 467 within the CDR circuit 457.
  • the phas ⁇ control circuit 467 compares adjacent data sampl ⁇ s (i.e., successiv ⁇ ly receiv ⁇ d data samples) within the data word to determine when data signal transitions hav ⁇ taken place, then compares an interv ⁇ ning ⁇ dg ⁇ sampl ⁇ with the preceding data sample (or succ ⁇ ding data sampl ⁇ ) to det ⁇ rmin ⁇ wh ⁇ th ⁇ r th ⁇ ⁇ dg ⁇ sample matches th ⁇ preceding data sample or succeeding data sample. If the ⁇ dge sampl ⁇ matches the data sample that prec ⁇ d ⁇ d th ⁇ data signal transition, then the edge clock is de ⁇ m ⁇ d to be early relativ ⁇ to th ⁇ data signal transition.
  • the edge clock is deem ⁇ d to be lat ⁇ relativ ⁇ to th ⁇ data signal transition.
  • th ⁇ phas ⁇ control circuit 467 asserts an up signal (UP) or down signal (DN). If there is no early/lat ⁇ majority, neither the up signal nor the down signal is assert ⁇ d.
  • the mix logic circuit 471 receiv ⁇ s a set of phase vectors 472 (i.e., clock signals) from a reference loop circuit 470.
  • the phase vectors have incrementally offset phase angles within a cycle of a reference clock signal (REF CLK).
  • th ⁇ r ⁇ ference loop outputs a s ⁇ t of ⁇ ight phas ⁇ v ⁇ ctors that ar ⁇ offs ⁇ t from one another by 45 degrees (i.e., choosing an arbitrary one of the phase vectors to have a z ⁇ ro d ⁇ gre ⁇ angl ⁇ , the remaining s ⁇ v ⁇ n phase vectors have phase angles of 45, 90, 135, 180, 225, 270 and 315 degre ⁇ s).
  • the mix logic 471 maintains a phase count value which includes a v ⁇ ctor s ⁇ l ⁇ ct component to sel ⁇ ct a phas ⁇ -adjacent pair of the phase vectors (i.e., phase vectors that bound a phase angle equal to 360°/N, where N is the total number of phase vectors), and an interpolation component (TNT) which is output to a mixer circuit 473 along with the s ⁇ l ⁇ ct ⁇ d pair of phas ⁇ vectors (VI, V2).
  • the mix ⁇ r circuit mixes the selected pair of phase vectors according to the interpolation component of the phase count to gen ⁇ rat ⁇ complementary edg ⁇ clock signals and complem ⁇ ntary data clock signals that collectively constitute the receiv ⁇ clock signal.
  • Th ⁇ mix logic 471 increments and decrements the phase count value in response to assertion of the up and down signals, resp ⁇ ctiv ⁇ ly, th ⁇ reby shifting the interpolation of the sel ⁇ cted pair of phase vectors (or, if a phase vector boundary is crossed, sel ⁇ cting a n ⁇ w pair of phas ⁇ vectors) to increm ⁇ ntally retard or advance the phase of the rec ⁇ iv ⁇ clock signal.
  • the mix logic 471 increments the phase count, thereby incrementing th ⁇ interpolation component of the count and causing the mixer to incrementally increas ⁇ th ⁇ phase offs ⁇ t (retard the phas ⁇ ) of th ⁇ receive clock signal.
  • the phas ⁇ control signal output begins to dither between assertion of the up signal and the down signal, indicating that edg ⁇ clock components of the rec ⁇ iv ⁇ clock signal hav ⁇ b ⁇ come phase aligned with the edges in the incoming data signal.
  • the equaliz ⁇ r clock g ⁇ n ⁇ rator 459 receives the phase vectors 472 from the reference loop 470 and includes mix logic 481 and an equalizer clock mixer 483 that operate in the same manner as the mix logic 471 and receive clock mixer 473 within the CDR circuit 457. That is, the mix logic 481 maintains a phas ⁇ count valu ⁇ that is incrementally adjusted up or down in response to the up and down signals from the phase control circuit 467.
  • the mix logic selects a phase-adjac ⁇ nt pair of phase vectors 472 based on a vector select component of the phas ⁇ count, and outputs th ⁇ s ⁇ l ⁇ ct ⁇ d vectors (VI, V2) and interpolation component of the phas ⁇ count (INT) to the equalizer clock mixer 483.
  • the equaliz ⁇ r clock mix ⁇ r 483 mix ⁇ s th ⁇ s ⁇ l ⁇ ct ⁇ d v ⁇ ctors in accordance with the interpolation component of the phase count to generate the equalizer clock signal, EQCLK.
  • the equalizer clock signal which may include complem ⁇ ntary component clock signals, is output to the equalizing output driver 465 (or oth ⁇ r typ ⁇ of ⁇ qualization circuit as described above) to time the output of equalizing signals onto signal path 122.
  • the equalizer data source s ⁇ l ⁇ ctor 463 is r ⁇ sponsiv ⁇ to th ⁇ calibration signal 474 to s ⁇ lect either the tap selector 461 (which operates as described above to sel ⁇ ct data tap valu ⁇ s from the shift register 453 and/or one or mor ⁇ parall ⁇ l r ⁇ gist ⁇ rs) or the signal generator 462 that outputs clock pattern 10101010 (e.g., a bi-stable storage elem ⁇ nt that toggles betwe ⁇ n stat ⁇ s in response to each EQCLK transition).
  • the equalization data source s ⁇ lector 463 selects the tap selector 461 to supply select ⁇ d data valu ⁇ s to th ⁇ equalizing output driver 465.
  • the rec ⁇ iv ⁇ r 450 enters a calibration mode in which the signal generator 462 is sel ⁇ cted to supply the clock pattern to the equalizing output driver 465. Also, in calibration mod ⁇ , th ⁇ high stat ⁇ of the calibration signal 474 disables AND gates 468i and 468 2 from passing the up and down signals to the mix logic 471. Thus, the phase count within the CDR circuit remains unchanged in calibration mode, whil ⁇ up and down signals g ⁇ nerated by th ⁇ phase control circuit 467 are used to increment and decrement the phase count value within the mix logic 481.
  • phase control circuit 467 will assert an up or down- signal (as the case may b ⁇ ) to adjust the phase of the receive clock signal relative to the incoming data stream.
  • the receive clock phase is eff ⁇ ctively locked, however (i.e., by operation of the AND gates 468), only the phase count within the equalization clock generator will be adjusted.
  • the normal-mode CDR operation is ⁇ ff ⁇ ctively carried out in rev ⁇ rs ⁇ whil ⁇ th ⁇ receiver 450 is in calibration mode.
  • the phase of the equalizer clock signal is shifted to align transitions in the incoming data signal (i.e., the clock pattern output by th ⁇ ⁇ qualizing output driv ⁇ r) with th ⁇ r ⁇ c ⁇ ive clock signal.
  • the equalizer clock signal is advanced relative to an edge clock component of the receive clock signal by a time substantially equal to the clock-to-Q delay of th ⁇ ⁇ qualizing output driv ⁇ r 465.
  • th ⁇ overall effect of the calibration mode operation is to advance the phase of the equalization clock according to the clock-to-Q tim ⁇ of th ⁇ ⁇ qualizing output driv ⁇ r as shown in Figur ⁇ 30.
  • th ⁇ ⁇ qualizing output driver 465 drives an equalizing signal onto the signal path 122 in phase alignment with the incoming data signal.
  • the calibration signal 474 is assert ⁇ d for a time interval previously determined to be sufficient to achieve phase alignment between transitions in the transmitted clock pattern and the edg ⁇ clock compon ⁇ nt of th ⁇ r ⁇ c ⁇ iv ⁇ clock signal.
  • the up and down signals generated by the phase control circuit may b ⁇ monitored in the calibration mod ⁇ to d ⁇ termine wh ⁇ n th ⁇ up and down signals b ⁇ gin to alt rnat ⁇ , thereby indicating that the desired phase alignment has b ⁇ n obtain ⁇ d.
  • th ⁇ calibration signal is deasserted to enabl ⁇ normal op ⁇ ration of the receive circuit.
  • the CDR circuit returns to adjusting the phas ⁇ count within mix logic 471 in response to the up and down signals from the phase control circuit 467. Because the mix logic 481 within the equalizer clock gen ⁇ rator 459 continues to respond to the same up and down signals, the phase offset betwe ⁇ n th ⁇ ⁇ qualiz ⁇ r clock signal and th ⁇ r ⁇ c ⁇ iv ⁇ clock signal (i.e., th ⁇ phas ⁇ offs ⁇ t ⁇ stablish ⁇ d in th ⁇ calibration mod ⁇ ) is maintain ⁇ d as the phases of the two clocks are adjust ⁇ d.
  • th ⁇ equalizer. clock signal and receive clock signal retain the phase offset established in calibration mode, but otherwise track on ⁇ anoth ⁇ r.
  • signal patterns oth ⁇ r than th ⁇ clock pattern 1010101 may be gen ⁇ rat ⁇ d by the signal generator 462 and used to achieve the desired phase relationship between the equalizer clock signal and th ⁇ receiv ⁇ clock signal.
  • the signal gen ⁇ rator may be implemented by a pseudo random bit s ⁇ quence (PRBS) gen ⁇ rator that g ⁇ nerates a pseudo random bit sequence.
  • PRBS pseudo random bit s ⁇ quence
  • any signal generator random or otherwise, that generates a sequ ⁇ nce of values having a sufficient transition density (i.e., transitions per unit time) to enable phase locking in the equalizing receiver 450 (i.e., phase locking betw ⁇ n transitions in th ⁇ waveform output by output driver 465 and the receive clock signal) may be used to implem ⁇ nt signal g ⁇ n ⁇ rator 462.
  • tap sel ⁇ ction logic may b ⁇ implemented in a number of different ways.
  • the tap s ⁇ lect logic 139 includes a configuration circuit that may be programmed with configuration information that specifies the tap data sources to be selected by sel ⁇ ct circuit 128.
  • Th ⁇ configuration circuit may include a nonvolatile memory, fusible circuit, ⁇ tc. that is programmed at production time according to the symbol latency, amplitude and polarity of empirically observed (or analytically det ⁇ rmined) distortions.
  • the configuration circuit may include memory (volatile or nonvolatile) which is initialized with predetermined configuration information during system startup.
  • a signaling system includes circuitry to automatically det ⁇ rmin ⁇ th ⁇ symbol latency, amplitude and polarity of distortions on the signaling path between a transmitter and receiver, and to program a configuration circuit within the tap sel ⁇ ct logic with configuration information that indicates the tap data sources to be sel ⁇ ct ⁇ d by a s ⁇ lect circuit and the tap w ⁇ ights and polarities to be appli ⁇ d by an ⁇ qualization circuit.
  • a technique called ⁇ mb ⁇ dd ⁇ d scoping is used to det ⁇ rmin ⁇ the symbol latency, amplitude and polarity of signal path distortions.
  • the symbol latency of a given distortion, onc ⁇ known is used to select one or more tap data values having corresponding symbol latencies, and the distortion amplitud ⁇ and polarity ar ⁇ used to det ⁇ rmin ⁇ th ⁇ weight and polarity to be applied to the selected tap data valu ⁇ in gen ⁇ rating an ⁇ qualization response.
  • the symbol latency of a given distortion may be used to det ⁇ rmine whether to counteract the distortion through transmitter pre ⁇ mphasis or r ⁇ c ⁇ iv ⁇ r ⁇ qualization (or both), and the overall range of symbol latencies for det ⁇ ct ⁇ d distortions may b ⁇ used to d ⁇ termine an appropriate dead range for the signaling system.
  • Embedded scoping involves iterativ ⁇ ly receiving a sequence of symbols in a rec ⁇ iver and comparing th ⁇ r ⁇ c ⁇ ived symbol sequence with a local generation of the sequ ⁇ nce to confirm error-fr ⁇ r ⁇ c ⁇ ption.
  • a thr ⁇ shold voltag ⁇ used to distinguish between symbol values in the incoming signal is offset from a calibrated level by a progressively larg ⁇ r amount until a symbol in th ⁇ s ⁇ qu ⁇ nc ⁇ no longer matches the expected value.
  • Th ⁇ threshold voltage offset at which the failure occurs is ref ⁇ rr ⁇ d to h ⁇ rein as a pass/fail offs ⁇ t and represents a measure of the signal level at the sampling instant at which the failure occurred.
  • Furth ⁇ r by sweeping the rec ⁇ iv ⁇ clock signal through an incr ⁇ m ⁇ ntal s ⁇ qu ⁇ nce of phase offsets, and det ⁇ rmining th ⁇ pass/fail offset at each phase offset, a complete trace of the incoming signal may b ⁇ generat ⁇ d.
  • th ⁇ granularity and start stop points of th ⁇ phas ⁇ offs ⁇ ts and/or threshold voltage steps may be controlled (e.g., by configuring a programmable circuit or register) to enable the waveform trace to b ⁇ constrained to sel ⁇ cted points of interest in the incoming signal (e.g., +N° from an int ⁇ nd ⁇ d sampling instant, N r ⁇ pr ⁇ s ⁇ nting a sw ⁇ p angl ⁇ ).
  • Figure 32 illustrates th ⁇ us ⁇ of ⁇ mbedded scoping to generate a time- based trace 490 of an incoming data signal 486.
  • the range of threshold voltage offsets over which the incoming signal 486 is sampled is indicated by V T
  • the range of phase offsets at which th ⁇ signal is sampl ⁇ d is indicated by D .
  • Each sample point within the swe ⁇ p is indicated by a respective dot within a grid of sample points 480. Note that the sweep may be obtained by stepping the voltage threshold through the rang ⁇ of V ⁇ values for each valu ⁇ of
  • V ⁇ (CAL) V ⁇ (CAL)
  • V ⁇ (CAL) the average of the V T offsets between the pass and fail samples, and recorded as a measure of the incoming signal. That is, the pass/fail offset may be us ⁇ d to ⁇ stablish a data point within the trace 490 as shown. Aft ⁇ r sw ⁇ ping through all th ⁇ sampl ⁇ points within the grid 480 (which swe ⁇ p may be repeated numerous times to obtain an average and to discard statistical outliers), a measure of the incoming signal is obtained as illustrated graphically by the trace 490. Embedded scoping has a number of benefits over traditional signal measurem ⁇ nt techniques.
  • the technique is non-invasive (i.e., no probe contact)
  • the el ⁇ ctrical characteristics of the system under test are unaltered, thereby yi ⁇ lding potentially more accurate results.
  • the trace is gen ⁇ rat ⁇ d from th ⁇ p ⁇ rsp ⁇ ctiv ⁇ of th ⁇ receive circuit itself, meaning that any non-ideal characteristics of the rec ⁇ iv ⁇ circuit are accounted for in th ⁇ resulting signal trace information.
  • embedded scoping may be used to p ⁇ rform numerous run-time analyses, including det ⁇ rmining th ⁇ lat ⁇ ncy and amplitude of refactions and oth ⁇ r distortions within th ⁇ signaling syst ⁇ m.
  • FIG 33 illustrates a signaling system 500 according to an embodim ⁇ nt of the invention.
  • the signaling system 500 includes a receive devic ⁇ 501 and transmit d ⁇ vice 509 that employ embedd ⁇ d scoping to determine equaliz ⁇ r tap s ⁇ lections, tap weights and tap polarities.
  • Th ⁇ transmit device 501 includes a pattern generator 503, data selector 505, equalizing transmitter 507 and application logic 502.
  • the application logic 502 performs the core function of th ⁇ transmitting d ⁇ vice ( ⁇ .g., signal processing, instruction processing, routing control, or any other function) and provides transmit data (TX DATA) to a first input of the data selector 505.
  • TX DATA transmit data
  • the application logic 502 outputs a logic low scope signal 506 (SCOPE) to the data sel ⁇ ctor 505 to s ⁇ lect the transmit data to be passed to the equalizing transmitter 507 for transmission to the rec ⁇ iv ⁇ device 509 via signal path 122
  • SCOPE logic low scope signal 506
  • th ⁇ application logic 502 drives the scope signal 506 high to enable a scoping mode of op ⁇ ration within th ⁇ transmit circuit 501.
  • the data sel ⁇ ctor 505 selects a rep ⁇ ating singl ⁇ -symbol pulse sequence (e.g., a test signal such as: 00100...00100...00100...) generated by the pattern generator 503 to be transmitted to th ⁇ r ⁇ c ⁇ iv ⁇ device 509.
  • the receive device 509 includes an equalizing receiv ⁇ r 510 to rec ⁇ iv ⁇ th ⁇ incoming data signal, a pattern register 511 to store a local version of th ⁇ singl ⁇ -symbol pulse sequence, a multiplex ⁇ r 512 to ⁇ nabl ⁇ th ⁇ pattern register 511 to be switched betw ⁇ n load and barr ⁇ l-shifting mod ⁇ s, a XOR gate 513 to compare the rec ⁇ iv ⁇ d data s ⁇ quence with th ⁇ locally g ⁇ n ⁇ rat ⁇ d s ⁇ qu ⁇ nc ⁇ , and application logic 515 (or other logic) to gen ⁇ rat ⁇ a clock adjust signal (CLK ADJ) and threshold voltage adjust signal (THRESH ADJ) to swe ⁇ p th ⁇ receive clock and threshold voltage us ⁇ d within the equalizing receiver through their scoping ranges.
  • the application logic 515 additionally builds a trace record (i. ⁇ ., data indicative of the incoming data sequ ⁇ nc ⁇ ) based on the output of XOR
  • the multiplexer 512 When the receive device 509 is in a scoping mode of operation, the multiplexer 512 is initially set to load the pattern register 511 with the output of the equalizing receiver 510. After a desired sequ ⁇ nce of data (e.g., the singl ⁇ -symbol puls ⁇ sequence) is shifted into the pattern register 511, the multiplexer 512 is set to enable the barrel-shifting mode of the pattern regist ⁇ r
  • the data sequ ⁇ nc ⁇ loaded into th ⁇ pattern r ⁇ gist ⁇ r 511 is r ⁇ p ⁇ atedly output, bit by bit, to a first input of the XOR gate 513.
  • the data sequ ⁇ nc ⁇ r ⁇ c ⁇ iv ⁇ d by the equalizing receiver is input to a second input of the XOR gate 513 so that the received data sequ ⁇ nc ⁇ is compared, bit by bit, with th ⁇ data sequence stored within the pattern regist ⁇ r 511.
  • th ⁇ pattern regist ⁇ r contents are repeatedly compared with a newly received version of the same data sequence (i.e., putatively th ⁇ sam ⁇ data s ⁇ qu ⁇ nc ⁇ ). Any reception error will result in a mismatch betw ⁇ n th ⁇ receiv ⁇ d value and the corresponding value within th ⁇ pattern register and therefore, when compared by XOR gate 513, will result in an error signal being output from the XOR gat ⁇ 513 to the application logic 515.
  • the application logic 515 may then record the adjusted threshold voltage and clock phase offset at which the error occurred to a signal l ⁇ v ⁇ l for a timing offs ⁇ t within a wav ⁇ form trac ⁇ .
  • Figure 34 illustrates an ex ⁇ mplary waveform trace 527 of a pulse data sequence captured by an emb ⁇ dd ⁇ d scope within the signaling system of Figure 33.
  • a primary pulse 529 arrives at the receiver at symbol time, T 0 ;
  • a negative refl ⁇ ction 531 of th ⁇ primary puls ⁇ app ⁇ ars at symbol tim ⁇ T 5 and a positive refl ⁇ ction 533 appears at symbol time T 12 .
  • the application logic 515 of r ⁇ c ⁇ iv ⁇ r 509 may store configuration information in a s ⁇ l ⁇ ct logic circuit within the equalizing receiver 510 (or elsewh ⁇ r ⁇ within th ⁇ receive device 509) to enable sel ⁇ ction of stored data values having symbol latencies of five and twelve symbol times as tap data sourc ⁇ s for an equalizing circuit.
  • the application logic 515 may directly output select signals to sel ⁇ ct th ⁇ d ⁇ sired stored data values as tap data sources.
  • the application logic 515 may also generate tap weights and tap polarity values in accordance with the amplitude and polarity of the distortions 531 and 533, and store or output the weights and polarity values as necessary to apply the appropriate tap weights and polarities within th ⁇ ⁇ qualizing rec ⁇ iv ⁇ r 510.
  • Figure 35 illustrates a method of setting equalization coefficients in a signaling system according to the invention, hi the embodiment shown, transmit-side equalization coefficients are s ⁇ t first (541), th ⁇ n r ⁇ c ⁇ ive-side ⁇ qualization coefficients are set (551).
  • the transmit-side coefficients are set by transmitting a test signal at 543 (e.g., a pulse signal, st ⁇ p, ⁇ tc), then gen ⁇ rating a waveform trac ⁇ (545) using th ⁇ ⁇ mb ⁇ dded scoping techniques described above.
  • the transmit-side equalization coefficients including tap data sources, tap w ⁇ ights and tap polariti ⁇ s, are then set at 547 to produce a rec ⁇ iv ⁇ d waveform trace that most closely corresponds to the ideal waveform ( ⁇ .g., puls ⁇ , st ⁇ p, etc.) output by the transmitter.
  • the transmit-side equalization coefficients may be d ⁇ t ⁇ rmin ⁇ d analytically (i. ⁇ ., by computing th ⁇ coefficients based on th ⁇ wav ⁇ form trac ⁇ generated at 545) or iteratively, by rep ⁇ ating op ⁇ rations 543 and 545 for diff ⁇ rent combinations of coefficient settings until a coeffici ⁇ nt setting that provides a desired waveform is det ⁇ rmin ⁇ d.
  • the receive-sid ⁇ coefficients are set by transmitting the test signal at 553 (i.e., a pulse, step or other signal transmitted with equalization according to the coefficients set at 547), then generating a waveform trace of the received waveform (555) using the embedded scoping techniques described above.
  • the rec ⁇ iv ⁇ -side ⁇ qualization coefficients including tap data sources, tap weights and tap polarities, are th ⁇ n s ⁇ t at 557 to produce a received waveform that most closely corresponds to the ideal waveform (i.e., waveform having reduc ⁇ d high-lat ⁇ ncy distortion).
  • Th ⁇ rec ⁇ iv ⁇ -sid ⁇ ⁇ qualization coefficients may be det ⁇ rmin ⁇ d analytically as described in reference to Figures 31-33, or iterativ ⁇ ly, by repeating operations 553 and 555 for different combinations of coefficient settings until a coefficient setting that provides a desired waveform is det ⁇ rmin ⁇ d.
  • selection of tap data sources within the transmitter may include outputting test signals on neighboring signal paths simultan ⁇ ously with th ⁇ t ⁇ st signal transmission at 543 to allow determination of which transmit-side equalizer taps, if any, should be sourced by cross-talk cancellation data values (i.e., data values being transmitted on neighboring signal paths) and the corresponding tap weights.
  • the tap select logic 139 and select circuit 128 enable equalization ov ⁇ r a r ⁇ lativ ⁇ ly wid ⁇ rang ⁇ of symbol lat ⁇ ncies using a small numb ⁇ r of ⁇ qualiz ⁇ r taps.
  • the total number of equalizer taps is further reduced through symmetry in the electrical distances betwe ⁇ n signal path discontinuities.
  • Figur ⁇ 36 illustrat ⁇ s a signaling system that employs path length symmetry to reduce the total number of equalization taps need ⁇ d to comp ⁇ nsat ⁇ for refl ⁇ ction-typ ⁇ ISI.
  • Th ⁇ syst ⁇ m includes a pair of circuit boards 571 and 573 (e.g., line cards, port cards, memory modules, etc.) having integrated circuit (IC) devices 575 and 577 mounted resp ⁇ ctively thereon.
  • IC device 575 includes a transmit circuit coupled to a connector interface 581 (e.g., a connector or a terminal to be received by a connector) via signal path s ⁇ gm ⁇ nt 582
  • IC device 577 includes a receive circuit coupled to a connector interface 585 via signal path segment 586.
  • the connector interfaces 581 and 585 are coupl ⁇ d to on ⁇ anoth ⁇ r through signal path segment 592 (e.g., backplan ⁇ trace, cable, etc.) to form an overall signal path between the transmit circuit and receiv ⁇ circuit.
  • the connector interfaces 581 and 585 tend to have at least slightly different impedances than the impedance of path segments 582, 586 and 592, refl ⁇ ctions ar ⁇ produced at comiector interfaces as shown by refl ⁇ ction flight paths A T , A R , C T and C R . Mor ⁇ sp ⁇ cifically, the reflection flight path indicated by A results from the primary signal reflecting off connector interface 581, and the reflection reflecting off the output node of the transmit circuit within IC 575.
  • the reflection flight time over path A T exc ⁇ ds th ⁇ unr ⁇ fl ⁇ ct ⁇ d primary signal flight time by twice the signal propagation time between the connector int ⁇ rfac ⁇ 581 and the transmit circuit output node; i.e., the signal propagation time on path segment 582.
  • the reflection flight time over path AR reflection off rec ⁇ iver input, then off connector int ⁇ rfac ⁇ 585) ⁇ xceeds the unrefl ⁇ ct ⁇ d primary signal flight tim ⁇ by twice the signal propagation time between the connector interface 585 and the receive circuit input; the signal propagation time on path segment 586.
  • path s ⁇ gm ⁇ nts 582 and 586 ar ⁇ designed or calibrated to have equal electrical lengths (i.e., equal signal propagation delays)
  • reflections A T and A R will arrive at the input of the receive circuit of IC device 577 at substantially the same time. Consequently, a single equalization tap having a symbol latency that corresponds to the latent arrival of the coincident A T /A R reflections may be used to cancel or at least reduce both reflections.
  • refl ⁇ ction flight paths C T and CR ar ⁇ mad ⁇ equal by equalizing the electrical lengths of path segments 582 and 586, a single ⁇ qualization tap that corresponds to the latent arrival of coincident CT/C R reflections may be used to cancel or at least reduce both reflections.
  • path segm ⁇ nts 582 and 586 to hav ⁇ equal electrical lengths (which path segm ⁇ nts may optionally include an on-chip path segment betwe ⁇ n th ⁇ transmit circuit output and an IC device 575 output node and/or an on-chip path segm ⁇ nt b ⁇ tw ⁇ n th ⁇ receiv ⁇ circuit input and an IC device 577 input node), one equalization tap within eith ⁇ r the transmit circuit or rec ⁇ iv ⁇ circuit may b ⁇ us ⁇ d to cancel or reduce a distortion that would otherwis ⁇ require two or more taps.
  • path segments 582 and 586 may optionally include an on-chip path segment betwe ⁇ n th ⁇ transmit circuit output and an IC device 575 output node and/or an on-chip path segm ⁇ nt b ⁇ tw ⁇ n th ⁇ receiv ⁇ circuit input and an IC device 577 input node
  • one equalization tap within eith ⁇ r the transmit circuit or rec ⁇ iv ⁇ circuit
  • 586 are made equal (or substantially equal — as achi ⁇ vabl ⁇ through practicable manufacturing techniques) by design which may include, but is not limited to:
  • path s ⁇ gments 582 and 586 1) making the physical lengths of path s ⁇ gments 582 and 586 substantially equal, wheth ⁇ r implemented by printed traces, cables or other types of conductors; 2) including inductive or capacitive structures (e.g., vias, f ⁇ rrite materials, narrowed or widened trace regions, or any other impedance-altering structures) statically coupled in seri ⁇ s or parall ⁇ l with path s ⁇ gm ⁇ nts 582 and/or 586 to ⁇ qualize otherwis ⁇ different electrical lengths of the path segm ⁇ nts; and/or 3) including inductive and/or capacitive structures that may be run-time coupled (e.g., through pass gates or other electrically or magnetically controllable structures) in series or parallel with path s ⁇ gm ⁇ nts 582 and/or 586 to ⁇ qualiz ⁇ otherwise different electrical lengths of the path segm ⁇ nts.
  • inductive or capacitive structures e.g.
  • any technique for adjusting the electrical lengths of path segments 582 and 586 to achieve coincident arrival of two or more signal refl ⁇ ctions at th ⁇ input of an ⁇ qualizing receiv ⁇ r may b ⁇ us ⁇ d without d ⁇ parting from th ⁇ spirit and scope of the present invention.
  • impedance-altering structures may be selectively coupled to path segm ⁇ nts 582 and/or 586 through operation of a configuration circuit (e.g., volatile or non-volatile storage, or fusible or otherwis ⁇ one-time programmable circuit).
  • a configuration circuit e.g., volatile or non-volatile storage, or fusible or otherwis ⁇ one-time programmable circuit.
  • a configuration value that corresponds to the d ⁇ sired electrical length of a path segment may be programmed into the configuration circuit and used to control pass gates or other switching elements for switchably coupling the impedance-altering structures to the path segm ⁇ nt.
  • Th ⁇ d ⁇ sir ⁇ d setting of the configuration value may be determined, for exampl ⁇ , by using th ⁇ ⁇ mb ⁇ dd ⁇ d scoping technique described above in ref ⁇ renc ⁇ to Figures 27-29 to determine relative arrival times of signal refl ⁇ ctions and therefor ⁇ propagation tim ⁇ diff ⁇ rences betw ⁇ n signal r ⁇ fl ⁇ ctions.

Abstract

A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics is provided. The selectable-tap equalizer includes a buffer, a select circuit and an equalizing circuit. The auto-configured equalizer includes a scoping circuit, buffer circuit, select circuit and equalizing circuit. The receiving circuit includes a sampling circuit, output driver and clock signal generator. The system includes a transmit circuit, a receive circuit, and a signal path coupled between the transmit circuit and the receive circuit. The signal path includes a first signal path segment coupled between the transmit circuit and a first interface, and a second signal path segment coupled between the receive circuit and a second interface, the second signal path having an electrical length that is substantially equal to an electrical length of the first signal path segment.

Description

A SELECTABLE-TAP EQUALIZER, AUTO-CONFIGURED EQUALIZER,
RECEIVING CIRCUIT HAVING AN EQUALIZER CALIBRATION
FUNCTION, AND SYSTEM HAVING GROUPED REFLECTION
CHARACTERISTICS
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to U.S. Patent Application Nos. 10/195,129, 10/195,130, 10/195,140, and 10/195,128, filed on July 12, 2002, which applications are hereby incorporated by referencε in their entirety.
FIELD OF THE INVENTION
The prεsεnt invention relates generally to high speεd signaling within and bεtween intεgrated circuit devices, and more particularly to reducing latent signal distortions in high speεd signaling systems.
BACKGROUND
Equalizing driver circuits are often used in high speεd signaling systεms to mitigatε thε εffεcts of intεr-symbol intεrfεrεncε and crosstalk. Referring to signaling system 100 of Figurε 1, for example, data values queuεd in buffεr 104 arε output to signal path 102 by output drivεr 101 simultaneously with transmission of an equalizing signal by equalizing driver 109. In the example shown, the equalizing drivεr 109 includεs a shift rεgistεr 113 and a bank of output drivεrs 111 to gεnεrate an equalizing signal based on the two most recεntly transmittεd data valuεs and the data value to be transmitted after the present, refεrεnce value. Thus, the εqualizing drivεr 109 constitutes a threε-tap (i.ε., thrεε data sourcε) equalizer for reducing inter- symbol interference that results from dispεrsion of signals transmittεd nεar in timε to the rεfεrεncε valuε (i.ε., dispεrsion-typε ISI). Whilε the εqualizing drivεr 109 is εffεctivε for rεducing relatively low-latency distortions such as dispersion-typε 1ST, othεr typεs of systεmatic distortions, such as signal rεflεctions (also rεfεrrεd to as rεflεction-typε ISI), tend to have a much higher latency (i.ε., occur much later in time rεlative to transmission of the refεrεncε value) and therefore would require a substantially larger number of taps and a correspondingly largεr shift rεgistεr to countεract. For example, in the systεm of Figure 1, a first reflεction, AT, occurs whεn a refεrεnce signal encounters an impεdancε discontinuity at a transmit-sidε interfacε 105 between a transmit-side portion (102A) and a backplanε portion (102B) of the signal path 102 (e.g., a connector interfacε to a backplanε). Because the reflεction bounces between the interface 105 and the output of the transmit circuit, thε reflection will arrive at the input of a recεivεr 103 with a latεncy (i.e., dεlay rεlativε to arrival of thε unrεflεcted refεrεncε signal) εqual to approximately twicε thε rεflεction flight timε bεtwεεn thε transmit-sidε intεrfacε 105 and thε transmit circuit output. Impεdancε discontinuities at the input to recεivεr 103 and at a rεcεivε-sidε intεrfacε 107 betweεn a receive-side portion (102C) and thε backplanε portion (102B) of thε signal path 102 similarly producε rεflεctions, A , CT, CR and D that arrivε at thε rεcεivεr 103 at rεspεctive, latent timεs according to thε additional distance travelεd by thε rεflεctions. Figure 2 is a wavεform diagram of reflections A , AR, B, CT, CR and D illustrating their rεspεctivε latencies rεlative to reference signal arrival time, T (A2TR corresponds to additional reflections produced by the intεrface 105). Because such reflections may occur at latenciεs on thε order of tens or evεn hundreds of signal transmission intervals, the shift registεr 113 would nεεd to bε substantially deeper in order to store the tap values needεd to mitigatε thε resulting distortions. Moreover, the precise timε at which rεflεctions arrivε at the receivεr 103 arε dεpεndεnt upon systεm configuration, meaning that a genεrally applicable equalizer, whether implemεntεd on thε transmit or receivε sidε of the signaling systεm 100, would need a relatively large number of equalizing taps to be able to compensatε for a rεflεction occurring at any timε bεtwεen the signal transmit time and a worst case latεncy. Unfortunately, each additional equalizing tap increases the parasitic capacitance of the transmit or receive circuit, degrading the frεquεncy rεsponsε of thε circuit and potεntially increasing thε impεdance discontinuity (and therefore the magnitude of reflected signal) at the circuit input/output.
BRIEF DESCRIPTION OF THE DRAWINGS Thε present invention is illustrated by way of εxamplε, and not by way of limitation, in thε figures of the accompanying drawings and in which like rεfεrεncε numεrals rεfεr to similar elemεnts and in which: Figure 1 illustrates a prior-art signaling system; Figure 2 is a waveform diagram of reflεctεd signals produced by the prior-art signaling system of Figure 1 ;
Figure 3 illustratεs a signaling systεm according an εmbodimεnt of thε invention;
Figure 4 illustrates an exεmplary relationship bεtwεεn clock and data signals in thε signaling systεm of Figure 3; Figure 5 illustrates the manner in which pre-εmphasis and sεlεctablε- tap equalization are employed to reduce low- and high-latency distortions in thε signaling systεm of Figure 3;
Figure 6 illustrates a transmit device having circuitry for sεlεcting betweεn tεmporal εqualization and cross-talk cancellation data sources; Figure 7 illustrates transmit and receive devices configured to perform near-end cross-talk cancellation;
Figure 8 illustrates a transceiver device that includes both an εqualizing transmittεr and an equalizing receivεr; Figure 9 illustrates an equalizing transceivεr according to an εmbodimεnt in which both transmittεd and receivεd data valuεs are storεd and sεlεctivεly usεd to source εqualizεr taps;
Figure 10 illustrates an εxεmplary buffεr that may bε usεd within the receivεr of Figure 3;
Figure 11 is a flow diagram of an εxemplary method of sεlεcting a data valuε having desired symbol latency from the buffer of Figure 10;
Figure 12 illustrates an exεmplary εmbodimεnt of a tap sεlεct circuit;
Figure 13 illustrates an exεmplary embodiment of the select logic of Figure 12;
Figure 14 illustrates a genεralizεd selεct circuit that may bε usεd to sεlεct Q tap values from the buffer circuit of Figure 12;
Figure 15 illustratεs an εmbodimεnt of a switch εlεmεnt that may bε usεd within thε switch matrix of Figure 14; Figure 16 illustratεs an embodiment of an equalizing receivεr;
Figure 17 illustratεs thε recεivε circuit of Figure 16 in greater detail;
Figure 18 illustrates an exemplary timing relationship between clock, data and equalization signals in the equalizing receiver of Figure 16;
Figure 19 illustrates a current-sinking output drivεr that may be used within the equalizing receivεr of Figure 16;
Figure 20 illustrates an embodimεnt of a push-pull typε of sub-driver circuit that may be usεd within an εqualizing output drivεr;
Figure 21 illustrates another εmbodimεnt of a sub-drivεr circuit that may bε usεd within an equalizing output driver; Figure 22 illustrates an alternativε type of equalizing circuit that may be usεd in εmbodimεnts of thε invεntion;
Figure 23 illustrates an embodiment of a levεl shifting circuit that may be used within the equalizing circuit of Figure 22; Figure 24 illustrates another type of equalizing circuit that may be used in embodiments of the invention;
Figure 25 illustrates an embodiment of a level shifting circuit that usεd within thε εqualizing circuit of Figure 24; Figure 26 illustrates an equalizing receiver according to an embodiment of the invention;
Figure 27 illustrates a shift registεr and tap selector that may be usεd within thε εqualizing rεcεivεr of Figure 26;
Figure 28 illustrates an equalizing receiver for receiving a double data rate, multilevεl input signal according to an embodiment of the invention;
Figure 29 illustrates an exemplary encoding of bits according to the level of a sampled, multilevel input signal;
Figure 30 illustratεs an exεmplary timing relationship bεtwεen clock, data and equalization signals in an equalizing receivεr; Figure 31 illustrates an εmbodimεnt of an εqualizing receiver that generatεs rεcεivε and εqualization clock signals having thε phasε relationship shown in Figure 30;
Figure 32 illustratεs the use of embedded scoping to genεrate a trace of a data signal ovεr a singlε symbol time; Figure 33 illustrates an embodiment of a signaling system that employs εmbεdded scoping to determine equalizer tap selections, tap weights and tap polarities;
Figure 34 illustrates an exemplary trace record for a pulse waveform captured by an embεdded scope within the signaling system of Figure 33; Figure 35 illustrates a method of setting equalization coefficients in a signaling system according to the invention; and
Figure 36 illustratεs a signaling system that employs path length symmetry to reduce the total number of equalization taps neεded to compensate for reflection-type ISI. DETAILED DESCRIPTION
In the following dεscription, specific nomenclature is set forth to provide a thorough understanding of thε present invention. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the present invention, hi some instances, the interconnection between circuit elεmεnts or circuit blocks may be shown as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be singlε signal conductor lines, and each of the single conductor signal lines may altεrnativεly bε multi-conductor signal lines. A signal is said to be "asserted" when the signal is driven to a low or high logic state (or charged to a high logic statε or discharged to a low logic state) to indicate a particular condition. Conversεly, a signal is said to bε "dεassεrtεd" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating statε that may occur whεn thε signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled betwεεn thε signal driving and signal receiving circuits. A signal line is said to be "activated" whεn a signal is asserted on the signal line, and "deactivated" when the signal is deasserted. Additionally, thε prefix symbol "/" attached to signal names indicatεs that thε signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ' < signal name > ') is also used to indicate an active low signal. Active low signals may be changed to active high signals and vice-versa as is genεrally known in the art.
Signaling systems and circuits for equalizing low- and high-latεncy signal distortions arε disclosed herεin in various embodiments (herein, equalizing refers to counteracting, canceling or otherwise reducing signal distortion). hi one embodimεnt, low-latency distortions (e.g., dispεrsion-type
ISI, cross-talk, etc.) are reduced by a transmit-side εqualization circuit, and high-latency distortions (e.g., signal reflections) arε reduced by a recεivε-sidε equalization circuit; the latεncy of rεcεivε-sidε equalization taps being offset relative to the reception time of a refεrεncε signal by thε numbεr of transmit- side equalization taps.
Because data values recεivεd within an εqualizing receivεr arε stored for parallel transfer to application logic, stored data is available to supply receivε-sidε equalizer taps; no additional shift register or other storage circuit is necessary to store equalizεr data. In onε εmbodimεnt, a sεlect circuit is provided to selectively route a relativεly small subsεt of thε stored data values to equalizing taps within the equalizing recεiver. By this arrangemεnt, reflected signals arriving at various, latent times may be counteracted by routing of selected stored data valuεs to the recεive-side equalization taps. Bεcausε thε number of equalizing taps within the equalizing rεcεivεr is small relative to the range of time for which distortion evεnts are mitigated, the parasitic capacitance of the equalizing recεiver is small relativε to thε parasitic capacitance that would result from providing a dedicated tap for each storεd data valuε.
Signaling System with Selectable-Tap Equalizer Figure 3 illustrates a signaling system 117 according to an εmbodimεnt of the invention. The system 117 includes an equalizing transmitter 115 and equalizing receiver 116 coupled to one another via a high-speεd signal path 122, and a controller 141 couplεd to thε transmittεr 115 and the receivεr 116 via relatively low-speed signal paths 142A and 142B, respectively. In one embodiment, the signal path 122 is formed by component signal paths 122 A, 122B and 122C (ε.g., transmission linεs that introduce respective, nonzero propagation delays and exhibit respεctivε impedance characteristics), each disposed on respective circuit boards that are coupled to one another via circuit board interfacεs 125 and 127 (ε.g., connectors). In a specific implemεntation, signal path 122B is formεd on a backplanε and signal paths
122A and 122C arε formεd on respective daughterboards (e.g., line cards) that are removably coupled to the backplane via connectors 125 and 127. The transmittεr 115 and rεcεivεr 116 arε implεmented in rεspεctivε intεgratεd circuit (IC) devices that are mounted on the daughterboards. The controller, which may be a gεneral or special purposε processor, state machinε or other logic circuit, is implεmεntεd within a third intεgrated circuit device mounted to a yet another circuit board. In thε εmbodimεnt of Figurε 3, signal paths 142 A and 142B arε usεd to convey configuration information from the controller 141 to the transmitter 115 and recεivεr 116, rεspεctivεly, and may bε disposεd on the samε circuit board (or circuit boards) as signal path 122 or implεmented by an alternativε structure such as a cable. The controller may alternativεly bε couplεd to thε transmitter 115 and recεivεr 116 by a shared signal path such as a multi-drop bus. Thε opεration of thε controller 141 is discussed in greater detail below. In alternative embodimεnts, thε IC dεvices containing the transmitter 115, recεivεr 116 and controller 141 may be mounted to a common structure with the signaling paths 122, 142A and 142B coupled directly to the IC devices (e.g., all threε ICs mountεd to a circuit board and coupled to one another via circuit board traces, or all threε ICs packaged within a single multi-chip module with signal paths 122 and 142 formed bεtwεεn the ICs by bond wires or othεr conducting structures). Also, the transmitter 115, rεcεivεr 116 and controller 141, or any subset thereof, may be included within the same IC devicε (ε.g., systεm on chip) and thε signaling paths 122 and/or 142 implemented by a metal layer or other conducting structure within thε IC dεvice.
The transmitter 115 transmits data on the signaling path 122 during succεssivε timε intervals, refεrrεd to herein as symbol times. In one embodimεnt, illustratεd by thε timing diagram of Figurε 4, εach symbol time, Ts, corresponds to a half cycle of a transmit clock signal, TCLK, such that two data values (e.g., valuεs A and B) are transmitted on signaling path 122 per transmit clock cycle. Thε transmittεd data signal arrivεs at thε input of receiver 116 after propagation time, Tp, and is sampled by the recεiver 116 in rεsponsε to εdges of a receive clock signal, RCLK. Still referring to Figure 4, thε receive clock signal has a quadrature phase relation to data valid windows (i.e., data eyes) in the incoming data signal such that each sample is captured at the midpoint of a data eyε. In altεrnative embodimεnts, thε sampling instant may bε skewed relative to data eye midpoints as necessary to satisfy signal setup and hold time requirements in the receiver 116. Also, more or fεwer symbols may be transmitted per cycle of the transmit clock signal.
The εqualizing transmittεr 115 includεs a transmit shift registεr 124, output drivεr 121 and transmit εqualizer 129; the transmit equalizer 129 itself including a shift register 120 and a bank of output drivers 131. At the start of each symbol time, the data value at thε hεad of the transmit shift registεr 124, referred to herein as the primary data value, is drivεn onto the signal path 122 by the output drivεr 121, and the equalizer 129 simultaneously drives an equalizing signal onto the signal path 122. This type of εqualization is referred to herein as transmit preemphasis. In one embodimεnt, the signal driven onto thε signal path 122 by thε output driver 121 (referred to herein as the primary signal) is a multi-levεl signal having onε of four possiblε statεs (ε.g., dεfinεd by four distinct signal ranges) and therefore constitutes a symbol reprεsεntativε of two binary bits of information. In alternativε εmbodimεnts, thε primary signal may havε more or fεwεr possiblε states and therefore represent more or fewεr than two binary bits. Also, thε primary signal may bε singlε-εndεd or diffεrεntial (an additional signal line is providεd to carry thε complεmεnt signal in thε differential case), and may be a voltage or current mode signal. Each of the output drivεrs 131 within thε equalizing circuit 129 form either a pre-tap driver or post-tap driver according to whether the source data value has already been transmitted (post-tap data) or is yet to be transmitted
(pre-tap data). In the spεcifϊc embodiment of Figure 3, thε equalizer includes N post-tap drivers sourced by data valuεs within thε shift rεgistεr 120 and one pre-tap driver sourced by a data valuε within thε transmit shift register 124.
Accordingly, the resultant equalizing signal driven onto the data path 122 will have a signal level according to data values having symbol latencies of -1, 1,
2, ..., N, where the symbol latεncy of a givεn data valuε rεfεrs to thε number of symbol times by which transmission of the data value prεcεdes the transmission of the primary value. Different numbεrs of post-tap and prε-tap drivεrs may be provided in alternative embodiments, thereby allowing for equalization basεd on values having different symbol latencies.
Still referring to Figure 3, the recεivεr 116 includes a sampling circuit 123, buffer 132, tap selεct circuit 128 and tap select logic 139. Data signals are sampled by the sampling circuit 123, then stored in the buffer 134 for eventual use by application logic (not shown). Because the buffered data is stored for at least a predetermined time, and represents historical data up to a predεterminεd numbεr of symbol latencies, the buffered data forms an ideal source of post-tap data values. That is, in contrast to transmit-side buffering of post-tap data values (which requirεs dedicated storage such as shift registεr 120), buff ring of rεcεivεd data in rεcεivεr 116 incurs no additional storage overhεad bεcausε thε rεcεivεd data values arε buffered in any event to facilitate transfer to receivε-sidε application logic. Additionally, thε tap sεlect circuit 128 enablεs a subsεt of data valuεs within thε buffεrεd data to bε sεlected to source equalizεr taps in a rεcεivε-side equalizer circuit. Because the subsεt of data values may be selεctεd according to the precise symbol latencies of reflections and other high-latency distortions, a relativεly small numbεr of data valuεs may bε selected to form receivε-side equalization taps having latεncies that match thε latencies of the distortions. By this arrangement, high latency distortions may be reduced by recεivε-side equalization without dramatically increasing the parasitic capacitance of the receiver (i.e., as would result from a large number of receivε-sidε εqualization taps).
In onε εmbodimεnt, the tap sεlεct logic is a configuration circuit that outputs a tap sεlεct signal 134 according to a configuration value. As discussed below, the configuration value may be automatically generated by system 117 (e.g., at system startup) or may be empirically dεtεrminεd and stored within the configuration circuit or elsεwhεrε within systεm 117.
Still referring to Figurε 3, numεrous alternative types of equalization circuits may be used within the recεivεr 116. For εxample, in one embodiment, the receivεr 116 includes an output drivεr 140 (illustrated in dashed outline in Figure 3 to indicate its optional nature) to drive an equalizing signal onto the signal path 122 (and therefore to the input of the sampling circuit 123) coincidentally with the symbol time of an incoming signal. In another embodiment, the sampling circuit 123 includes a preamplifier having an equalizing subcircuit. In yet another embodimεnt, an εqualizing subcircuit is couplεd to the sampling circuit itself. Each of thεse embodiments is described in further detail below.
Still referring to Figure 3, the distribution of low- and high-latency equalization functions bεtwεεn thε εqualizing transmittεr 115 and equalizing recεivεr 116 is achiεvεd through usε of a dεad rangε within the receive-side buffer 132. That is, the range of stored data values that may be selected to source receivε-sidε equalization taps (i.ε., R) is offsεt from the sampling instant by a number of symbol times, M. In one embodiment, M is equal to N, the number of post-tap drivers, such that transmit preεmphasis is used to reduce distortions resulting from symbol transmissions up to N symbol timεs prior to transmission of thε primary signal, and receive-side equalization is usεd to rεducε distortions resulting from symbol transmissions more than N symbol timεs prior to transmission of thε primary signal. For εxamplε, if thεrε are four post-tap drivεrs in thε transmittεr 116 (i.e., M=N=4 ), then thε lowεst latεncy value within the range, R, of stored data values is M+l=5 symbol times, and the recεivεr 116 is said to have a dead range of four symbol times. In the embodimεnt of Figurε 3, buffer 132 is formed by a shift register having a dead range component 133 and a selεctablε-rangε component 135, the tap selector 128 being couplεd to thε sεlεctable-range component 135 to sεlεct thε subset of tap data sources therefrom. In altεrnative embodimεnts, thε dεad rangε component of the buffεr 132 may include fewεr than M storagε εlεmεnts or even zero storage elεmεnts, dεpεnding on thε timε required to rεcεivε data and transfεr data into thε buffεr 132. Also, thε tap selector 128 may be coupled to one or more storagε εlεments within the dead range component 133 to enablε thε sizε of the dead range to be programmed according to the configuration of the transmit circuit 115. Finally, as discussed bεlow, thε buffεr 132 may include one or more parallel rεgistεrs in addition to (or instead of) the shift register formed by components 133 and 135.
Figure 5 illustrates the manner in which pre-εmphasis at the transmitter 115 and selectable-tap equalization within the receiver 116 are employed to reduce low- and high-latency distortions in the signaling systεm of Figurε 3. Wavεform 148 dεpicts thε state of the signal path 122 during and after non- equalized transmission of a primary signal to illustrate the low- and high- latency distortions that may result. The primary signal is transmitted during a transmit interval 149 (i.e., a symbol time) that starts at time T, and the corresponding primary value is used to generate a transmit-side equalization signal (i.e., preεmphasis signal) ovεr a window of N symbol timεs following thε transmit intεrval 149. Thε transmit-side equalization signal is used to reduce low-latency distortions that may result from any number of sources including, without limitation, dispersion-typε ISI, inductive and capacitive coupling (which may be compensated, for examplε, by sourcing a prε- εmphasis output drivεr within bank 131 with a valuε being transmitted on a neighboring signal path), and low-latency reflεctions (ε.g., rεflεctions that do not travεl significantly further than the unreflεcted primary signal and therefore arrive at the recεiver shortly aftεr thε primary signal). The primary signal is sampled by the recεiver 116 during a reception interval (i.e., data valid window) that corresponds to the transmit interval 149, the reception interval being shifted relative to the transmit intεrval according to thε signal flight time betwεεn the transmitter 115 and recεivεr 116. Thε sεlεctable-tap equalizεr within thε recεivεr 116 has a dead range of M symbol timεs and a selectable range of R symbol times. Accordingly, thε sampled primary value (i.e., the primary received during the reception interval) is sεlεctablε to sourcε an equalizer tap within the recεiver 116 when the symbol latency of the sampled primary value is greatεr than M symbol timεs and lεss or εqual to R symbol timεs. Thus, during given reception interval, previously rεcεived values having symbol latencies ranging from M+l to R may be selected by the tap selεctor 128 of Figurε 3 and usεd to reduce high-latency distortions. Intervals 150l3 150 , and 150 within interval 153 illustrate equalization windows achiεvεd by tap sεlεctions within thε tap selector 128. For example, interval 150ι corresponds to one or more tap selections used to εqualize a distortion occurring shortly aftεr thε dead rangε, while interval 150 corresponds to one or more tap sεlections used to reduce a distortion caused by a signal transmission dozens or even hundreds of symbol times prior to the current reception interval. In the transmit circuit 115 of Figurε 3 and other equalizing transmitters disclosed herein, the polarity of signal contributions which form the transmit preemphasis signal (including any cross-talk cancellation component thereof) may bε fixεd or programmable and may be established (or controlled) within the data shift registεrs (i.ε., 124 and 120) or by the output drivers themsεlvεs (ε.g., output drivεrs within bank 131).
Similarly, in the receive circuit 116 of Figure 3 and other equalizing recεivεrs disclosed herein, the polarity of signal contributions which form thε receivεr equalization signal (including any cross-talk cancellation component thereof) may be fixed or programmable and may be establishεd (or controlled) within a data storage circuit (i.e., buffεr 132) or within a rεcεivεr εqualization circuit.
The ability to control tap data latenciεs with thε tap select logic 139 and tap selector 128 of Figure 3 enablεs thε εqualization windows 150 to be shifted within thε sεlεctablε range, R, as necessary to reduce high-latency distortions, thereby permitting generalized application of system 117 in environments having a variety of diffεrεnt distortion characteristics, hi the signaling system 117 of Figure 3, the controller 141 is used to configure one or more of the values of N, M and R (i.e., the number of transmit-side post-tap εqualizεrs, thε rεcεivε-side dεad rangε and thε rεcεive-sidε sεlεctablε rangε) according to systεm nεεds. hi onε embodiment, the controller includes a nonvolatile memory to store εmpirically or analytically determined values of N, M and R. Alternativεly, thε signaling systεm 117 may include a separate storage (e.g., flash memory, or other non- volatile media) to store values of N, M and R (or values that may be used to dεtεrminε N, M and R), the controller 141 being coupled to access such separatε storage via signal path 142 or another path. In either case, when the signaling system 117 is initially powered on, the controller 141 communicates the post-tap equalizer count, N, to the transmitter 115 and the dead range and selectable range valuεs, M and R, to thε receiver 116. Alternativεly, thε values of N, M and R may be detεrminεd at production timε (e.g., through system testing) or design time, and pre-programmεd into configuration circuitry within thε transmittεr 115 and/or rεcεivεr 116, or fixεd by design of the transmitter 115 and/or receivεr 116. hi such embodiments, thε controller 141 and signal path 142 may bε omittεd altogεthεr. As discussed below, embodiments of the invention may additionally include circuitry to automatically detεrminε distortion latεnciεs and to sεlect correspondingly latent data tap sources from the buffer 132, thus providing a system-indεpendent solution for rεducing systematic distortion evεnts of virtually any latεncy. The controller 141 may be used to coordinate operation of the transmitter 115 and recεivεr 116 during such automatic distortion latency detεrmination, and also to dεtermine appropriatε sεttings of N, M and
R basεd on such distortion latεnciεs.
Far-End and Near-End Cross-Talk Cancellation
As discussed above in refεr nce to Figure 3, the transmit-side equalizer 129 may be usεd to reduce signal distortion resulting from inductive and capacitivε coupling of signals transmittεd on nεighboring signal paths; a type of equalization referred to as far-end cross-talk cancellation. In one embodiment, the output driver bank 131 includes additional output drivεrs to gεnεratε εqualization signals basεd on valuεs bεing transmittεd on signal paths that arε adjacent or otherwise proximal to the signal path 122. By appropriate polarity control (performεd, for εxamplε, within the output drivers or data shift register), an equalizing signal having a polarity opposite that of an interfering neighboring signal is transmitted on the signal path 122, therεby reducing the signal interfεrεncε.
Thε numbεr of εqualizer taps neεdεd for cross-talk cancellation within a given signaling system is depεndεnt on thε physical layout of signal paths relative to one another. For εxamplε, in a systεm in which signal paths 122 arε arranged relativε to onε anothεr such that cross-talk intεrfεrεncε is negligible (e.g., paths 122 are spaced apart, arranged in an orthogonal disposition (e.g., twisted pair), etc.), no equalizεr taps may bε nεεdεd for cross-talk cancellation. By contrast, in a system in which signal paths form parallel adjacent paths (e.g., parallel traces on a printed circuit board or parallεl conductors within a multi-conductor cablε), onε or more equalizεr taps may bε nεεdεd for εach adjacent pair of signal paths. In one εmbodimεnt of thε invεntion, εqualizεr taps are selεctively coupled to either pre-tap, post- tap or cross-talk cancellation data sources (i.e., primary value being transmittεd on nεighboring path). By this arrangεmεnt, εqualizεr taps may be selectively configured, according to systεm requirements, to provide eithεr tεmporal εqualization (i.ε., prε-tap and/or post-tap εqualization) or cross-talk cancεllation.
Figure 6 illustratεs a transmit dεvice 154 having circuitry for selεcting bεtwεεn temporal equalization and cross-talk cancellation data sources. The transmit device 154 includes transmitters 152t and 152 , each for transmitting data signals on a respectivε signal path 122i and 1222. Rεspεctivε sources of transmit data values (TX DATA1 and TX DATA2) are provided from other logic (not shown) within transmit dεvicε 154. Although only two transmittεrs 152 arε shown, additional transmitters may bε providεd in accordance with the number of signal paths 122 and/or thε number of sources of transmit data values.
Each of the transmitters 152 includes a transmit shift register (124ls 1242), output driver (1211, 1212), post-tap data shift registεr (1201} 1202) and output driver bank (131l5 1312) that operate genεrally as dεscribed in reference to Figure 3. Each transmittεr 152 additionally includes a tap data source selector (153l5 1532) having one or more multiplεxεrs for selectively coupling eithεr a local data value (e.g., a pre-tap or post-tap data value from corresponding transmit shift registεr 124 or post-tap data shift register 120) or a remote data value (e.g., a primary value suppliεd from thε head of a transmit shift registεr 124 of another transmitter, or a post-tap data value supplied from the post-tap data shift registεr of anothεr transmitter) to be the equalization tap data source. For examplε, multiplexer A within tap data source selεctor 153ι has a first input coupled to a storage elεment within post-tap data shift register 120Ϊ and a sεcond input couplεd to thε output of transmit shift register 1242, and selects, according to a select signal SEL , εithεr a post-tap data valuε within shift registεr 120l5 or thε rεmotε primary valuε output by shift register
1242 to be the tap data source for an output driver within output drivεr bank 131 Multiplεxεr J within tap data source selεctor 153i has a first input coupled to a storage element within the transmit shift registεr 1241 and a second input coupled to thε output of thε transmit shift rεgistεr 1242, and sεlects, according to a select signal SELu, either a pre-tap data value within the transmit shift registεr 124ls or thε rεmotε primary valuε to bε thε data tap source for an output driver within output driver bank 131χ.
To enablε cancellation of crosstalk interfεrence that lasts for more than a single symbol time, additional multiplexεrs may bε providεd within thε tap data source selectors 153 to select betweεn local data valuεs (pre- or post-tap) and remote post-tap data values. For examplε, multiplεxer K within tap data source selεctor 153! has a first input couplεd to receivε a prε-tap data value from transmit shift register 124i and a second input coupled to receive a remote post-tap data value from post-tap register 120 , and selεcts between the two inputs according to select signal SELIK- Tap data source selector 1532 similarly includes onε or more multiplexers to select between pre-tap, post-tap and or cross-talk cancellation data sources for output driver bank 1312. By this arrangemεnt, output drivers within banks 131 may alternatively be used to generate temporal εqualization signals or cross-talk cancellation signals according to system neεds.
Although thε multiplexers within tap data source selεctors 153i and 1532 arε dεpictεd as two-input multiplexers, multiplexers having more than two inputs may alternatively be used. For example, multiplexer A of data source selεctor 153ι may include one or more inputs to receive pre-tap data values from register 124j, one or more inputs to receive post-tap data values from post-tap register 120!, and/or one or more inputs to rεcεive cross-talk cancεllation data valuεs (i.ε., rεmotε primary, prε-tap and or post-tap valuεs from any numbεr of othεr transmittεrs 152). In gεnεral, εach output drivεr within an output drivεr bank 131 may bε sourcεd by a multiplεxεr that sεlεcts bεtwεεn any numbεr of prε-tap, post-tap and/or cross-talk cancellation data sources. Also, not all output drivers within output driver banks 131 neεd bε fεd by multiplεxεrs, but rather may be coupled to dedicated tap data sources.
In onε embodiment, the select signals, SEL\ (including signals SEL!A,
SELU, SELΪK, εtc.) and SEL2, arε gεnεratεd by a configuration circuit (not shown) within transmit device 151 or elsεwherε in a signaling systεm that includes transmit device 151. The configuration circuit may be pre- programmεd or may be programmεd at system start-up, for example, by a controller similar to controller 141 of Figure 3.
As described in refεrencε Figurε 6, selectivε-tap transmit-sidε prεεmphasis may bε usεd to cancel or reduce interference between signals transmitted in the same direction on neighboring or othεrwisε proximal signal linεs (i.ε., far-εnd cross-talk). Sεlεctivε-tap rεcεive-side εqualization may similarly be used to reduce interference betwεεn outgoing and incoming transmissions on proximal signal linεs; intεrfεrεncε rεfεrrεd to hεrein as near- εnd cross-talk. Figurε 7 illustratεs transmit and receive devices (118 and 119, respectively) configured to perform near-εnd cross-talk cancellation. The transmit device 118 includes an output driver 121, transmit shift register 124, post-tap data shift registεr 120, and output driver bank 131, all of which operate genεrally as described above in refεrεncε to transmit device 115 of Figure 3 to εnablε gεnεration of an εqualizεd transmit signal (TX OUT) on signal path 122ι. Though not shown in Figurε 7, the transmit device 118 may additionally include selεct circuitry as described in refεrεncε to Figurε 6 to enable selεction of various equalization data sources. Thε receivε dεvicε 119 includes a sampling circuit 123, buffer 132, tap selεct circuit 137, tap select logic 139 and equalization circuit (e.g., included within the sampling circuit 123 or implementεd as an output drivεr 140) to rεcεivε an incoming signal (RX IN) on signal path 1222. As shown in Figurε 7, thε incoming signal, RX IN, has a smaller amplitude than thε transmit signal, TX OUT, (e.g., due to transmission losses) and therefore is particularly susceptible to nεar-εnd cross-talk intεrference. To counteract cross-talk interfεr nce from the TX OUT transmission, pre-tap, primary and post-tap data values used to genεratε thε TX OUT signal (i.e., from transmit shift register 124 and post-tap data shift registεr 120) arε suppliεd to thε tap sεlεct circuit 137 within thε rεcεivεr 119. By this arrangεmεnt, thε tap sεlεct logic 139 may sεlect, as tap values for the rεcεivεr εqualization circuit, any combination of the rεceivεd data valuεs storεd within buffεr 132, and thε prε- tap, post-tap and primary data valuεs usεd to gεnerate thε TX OUT signal. As discussed above in reference to Figure 3, tap selεct logic 139 outputs a control signal to thε tap sεlεctor 137 to control tap data source selection according system configuration information. Thus, the pre-tap, post-tap and/or primary data values may bε sεlεctεd with the polarity necessary to achievε a subtractivε effect on thε corresponding cross-talk interfεrεncε (the appropriate polarity being establishεd or controlled within the buffer 132 or receiver equalizing circuit), thereby enabling reduction of near-εnd cross-talk intεrference. Although only a single tap select circuit 137 is shown in Figure 7, any numbεr of tap select circuits may be used.
Bi-directional Signaling
Although a unidirectional signaling system is depicted in Figure 3, embodiments of the invention are equally applicable in a bidirectional signaling system. Figure 8, for example, illustrates a transceiver device 151 that may be coupled to either or both sides of signaling path 122, and that includεs both an εqualizing transmittεr 115 and an εqualizing receivεr 116 according to embodiments described herein (transmitters and rεceivεrs according to thε cross-talk canceling embodimεnts dεscribed in reference to
Figures 6 and 7 may also bε usεd). Thε transcεivεr dεvicε 151 additionally includεs an application logic circuit 154 to provide transmit data to the εqualizing transmitter 115 and to recεivε samplεd data from the equalizing recεivεr 116. Thε application logic circuit 154 also outputs an εnablε signal
(ENABLE) to alternately enable the transmittεr 115 to transmit data on thε signal path 122 or thε recεiver 116 receivεs data from thε signal path 122. Figurε 9 illustratεs an equalizing transceivεr 155 according to an embodiment in which both transmitted and received data values are stored and selectively used to source equalizer taps. The transceivεr 155 includes a transmit shift registεr 124, output drivεr 121, post-tap data shift rεgistεr 120 and output drivεr bank 131 (which may include output drivers sourced by pre- tap data valuεs, cross-talk cancellation values, or by tap data source selεctors as dεscribεd in reference to. Figure 6), all of which operatε gεnerally as described in reference to Figure 3 to output, during a givεn transmit interval, a primary signal and corresponding equalization signal onto signal path 122. The transceivεr also includes a sampling circuit 123, buffer circuit 132, tap selector 156 and tap select logic 157. The sampling circuit 123 samples data signals transmitted on signal path 122 (i.e., by a remote transmitter or transceiver) and stores the corresponding data values in buffer circuit 132. The tap selector 156 is coupled to the buffer circuit 132 as well as the transmit shift registεr (including thε hεad of thε transmit shift register which contains the primary data value) and the post-tap data shift registεr 120, and thεrefore enables any combination of received data values (i.ε., from buffεr 132) and pre-tap, primary and/or post-tap transmit data values to be. selected as source data taps within an equalizing circuit (i.e., output driver 140 or an equalizing circuit within the sampling circuit 123). The tap selεct logic 157 outputs a control signal to the tap sεlector according systεm configuration information
(i.e., information indicative of desired symbol latencies) and the historical state of thε εnablε signal (ENABLE). Thus, depending on the dεsired symbol latenciεs of data taps, and the timεs at which thε transcεivεr 155 is transitionεd bεtwεεn sending and receiving data (i.e., turnaround timεs), the tap sεlεct logic 157 and tap sεlector 156 operate to selεct tap valuεs from the transmit shift register 124, data tap shift registεr 120, and/or buffεr circuit 132 in any combination. Thε selected tap values are then used to source equalizεr taps within an equalizing output driver 140 or an equalizing circuit within sampling circuit 123.
Although the transceiver embodimεnts dεscribεd in reference to Figures 8 and 9 include an enablε linε to alternatεly enable transmission or reception of signals, in alternative embodiments, the enable line may be omitted and transmission and reception of signals may occur simultaneously (i.ε., simultanεous bi-dirεctional signaling). In such a system, multilevel signaling may be used to enable an outgoing signal to bε transmittεd simultaneously (in εffεct, superimposed on) an incoming signal. Because the receive circuit has access to the transmitted data values, thε receive circuit may subtract the locally transmitted signal from an incoming signal to recover only the desired portion (i.e., rεmotεly transmitted portion) of the incoming signal. In such a system, the locally transmittεd signal may produce dispersion- and reflection-type ISI that may bε compensated by an equalizing recεivεr having, as an εxample, the configuration of Figure 9, but omitting the enablε line. In such an embodimεnt, thε transmit shift register 124 and post- tap data register 120 may be selεctεd by tap sεlect circuit 156 to source tap data values for equalization of low- and/or high-latεncy distortions resulting from thε local signal transmission (i.ε., by output driver 121). Notε that the post-tap data register may need to be extended (i.e., have an increased number of entriεs) to εnable reduction of high-latency distortions resulting from the local signal transmission. The recεivε circuit tap sεlεctions, controlled by tap sεlect logic 157, may bε determinεd εmpirically or during run-timε, for εxamplε, by using thε mεthods and circuits described below for determining equalization tap latencies, weights and polarities.
Data Tap Selection
Figure 10 illustratεs an εxεmplary buffer 159 that may be used within the receiver 116 of Figure 3 and that includes both a serial shift register 161 as wεll as a numbεr (K) of parallεl-load rεgistεrs 165rl65κ. At each edge of a receive clock signal, RCLK, a newly samplεd data value 160 is loaded from sampling circuit 123 into the shift register 161. The shift register is formed by N storage elements (depicted as flip-flops 163]-163H, though latches or other types of storage elεmεnts may bε usεd) couplεd in daisy chain fashion such that, as thε nεwly samplεd value 160 is loaded into the first storagε εlεment 163! in the shift register 161, the contents of each storage element 163 except the last (163N) is shifted to thε nεxt storagε elemεnt in thε chain in response to a receive clock signal (RCLK). Thus, designating the output of storage element 163ι to have symbol latency i, the symbol latency of the input value 160 is i-1, and the symbol latencies of the outputs of the remaining storage elemεnts 163 in the shift registεr 161 are, from left to right, i+1, i+2, ..., and i+(N-l), rεspεctivεly.
A shift counter 169 (which may be included within or separatε from buffer circuit 159) maintains a count of the number of data values shifted into the shift register 161, incrementing the shift count in response to each transition of RCLK. In one embodiment, the shift counter 169 asserts a load signal 164 (LD) upon reaching a count that corresponds to a full shift registεr, then rolls the shift count back to a starting valuε. The load signal 164 is routed to strobe inputs of storagε elεmεnts within thε parallel-load registers 165, enabling parallεl load register 165! to be loaded with the contents of the shift register, and enabling each of the parallel-load registεrs 1652-165 to bε loadεd with the content of a preceding one of the parallel load registεrs (i.e.,
165 is loaded with the content of .1651, 165 is loaded with 1652, and so forth). By this arrangement, the symbol latency of a data value stored within any of thε parallεl-load rεgistεrs 165 is dεpεndεnt on how many data valuεs havε been shifted into the shift register since the last assertion of the load signal 164; a measure indicated by the shift count. For example, if the shift count is 1, indicating that the load signal 164 was asserted at the immediately preceding edge of RCLK, then the content of storage elεmεnt 167i of parallεl- load register 165i has a symbol latency of i+1 (i.ε., onε symbol timε oldεr than thε content of storage εlement 163ι of the shift registεr). Whεn the next valuε is shifted into thε sεrial shift register 161, thε contents of the parallel rεgistεrs 165 remain unchanged, meaning that thε latency of each data value stored in thε parallεl registers 165 is increased by a symbol time. Thus, the content latency (i.e., latεncy of a storεd valuε) of a given storagε εlεmεnt within onε of parallεl registεrs 165 is dεpendent upon the value of the shift count. Refεrring to parallεl load rεgistεr 165l5 for example, the content latency of storagε εlεment 167! is i+SC (SC bεing the shift count), the content latεncy of storagε εlεment 1672 is i+SC+1, and so forth to storage elεmεnt 167N, which has a content latency of i+(N-l)+SC. The content latencies of storage elεmεnts within the parallel-load registers 1652-165κ are similarly dependent upon the shift clock value, SC, but are increased by N for each parallεl load away from register 165ι. That is, the content latency of thε leftmost storage elεmεnt within rεgistεr 1652 is i+N+SC, and the content latency of the leftmost storage elεmεnt within register 165κ is i+(K-l)N + SC. The content latencies of the storage elεmεnts within registers 165 -165κ are incrementally relatεd to thε content latency of thε corresponding leftmost storagε εlεmεnt in thε samε manner that the content latencies of storage elεments 1672-167N relate to the content latency of storage elεmεnt 167]. Figurε 11 illustrates, in flow diagram form, a mεthod of selecting a data value having symbol latεncy i+X from thε buffεr 159 of Figure 10, i being the content latεncy of storagε εlεmεnt 163!. At 175, X is compared with
N, the number of storage elements within the shift registεr 161 and within εach of thε parallεl-load rεgistεrs 165. If X is lεss than N, then the desired data value is located within the shift registεr which, aftεr bεing initially loaded, always contains data values having symbol latencies ranging from i to i+N-1. Thus, if X is less than N, thεn as shown at 177, thε dεsirεd valuε is in thε shift rεgistεr (REG^SR) at bit position X (BIT=X), where the bit position corresponds to left-to-right numbεred storage elεments.
If X is not less than N, then the desired data value is located at a shift- count-dependεnt bit position within one of the parallel-load registεrs 165. Thus, if X is less than N+SC (179), the desired data valuε is locatεd within register 165] at bit position X-SC, as indicated at 181. To understand this result, consider what happens if a data value having a desirεd symbol latency is initially within the rightmost storage elemεnt, 167N, within parallεl-load register 165!. As a new value is shifted into thε sεrial shift register 161 and the shift count is incremented, the symbol latency of storage elεment 167N is increased, and the storage elεmεnt one position to the left of storage element 167N (i.ε., 167N-I) now contains thε data valuε having the desired symbol latency and is therefore selected to supply the data value to an equalizer tap.
Returning to Figure 11, if X is greatεr than or εqual to N+SC, thεn X is compared with 2N+SC at 183. If X is less than 2N+SC, then parallel-load registεr 1652 contains the desired tap value at bit position X-N-SC as indicated at 185. The decision flow continues in this manner to 187 at which point X is compared with (K-1)N+SC. If X is lεss than (K-1)N+SC, thεn parallεl-load rεgistεr 165 .! contains the desired tap value at position X-(K-1)N - SC as indicated at 189. Otherwise, X is located within the final parallel-load registεr, 165 at position X-KN-SC as indicated at 191. Figure 12 illustrates an exemplary embodimεnt of a tap select circuit for selεcting a tap valuε (DATA,+χ) from a buffεr circuit 210 that includes an eight-bit serial shift registεr 161 and two εight bit parallεl-load registers 165ls
1652. For purposes of illustration, it is assumed that the data value in thε first (leftmost) storage elεmεnt within the shift register 161 has a symbol latency of one and that the dead range is four symbol times (i.e., the leftmost four storage elεmεnts within thε shift register 161 are not used to source tap values to the equalizer). By this arrangement, immediately after a parallεl load operation, the data values stored in parallel-load register 165! will have symbol latencies ranging from 2-9 symbol timεs, and thε data valuεs storεd in parallεl-load rεgistεr 1652 will havε symbol latεncies ranging from 10-17 symbol times. Accordingly, refactions (or other distortions) appearing at the receiver input betwεen 5 and 17 symbol times after the corresponding primary signal may be reduced by selεcting data values having corresponding symbol latencies from the buffer circuit 210 to drive the recεivε-sidε εqualizεr taps (i.e., to be tap data values). Multiplexers 205, 207j and 2072 are responsivε to low order bits of a latency value 200 (X[4:0]) to select tap positions within the shift register 161, parallel-load registεr 165l5 and parallel-load rεgistεr 1652. Thε latεncy valuε 200 is additionally suppliεd to a sεlect logic circuit 201 which generates a register select signal, SEL[1:0], to selεct one of thε thrεε rεgistεrs 161, 165 \ and 1652 within thε buffεr circuit 210 to source the tap data value, DATAj+χ. It should be noted that, because the range of tap valuεs εxtεnds ovεr 13 possiblε symbol timεs (symbol latεncies from 5-17), a smaller, four-bit latency value may altεrnativεly bε usεd to sεlεct a tap valuε. As dεscribed below, howevεr, using a latεncy valuε largε εnough to select any of the bit positions within the buffer circuit 210 enables the size of the dεad rangε to be adjusted (i.ε., programmed) according to application needs. Thε least significant two bits of the latency value 200 (i.e., X[1:0]) are input to multiplexεr 205 to sεlect onε of thε four sεlεctablε data values within the serial shift registεr 161. Thε lεast three significant bits of the latency value 200 (i.e., X[2:0]) are input to a subtract circuit 203 which subtracts the shift count 202 from the threε-bit latεncy valuε to produce a tap select value for the parallel-load registεrs 1651? 165 . In onε εmbodimεnt, for εxamplε, thε sεlect value 200 corresponds to a desired symbol latency as shown in Table 1 below, and the shift count 202 is encoded in a three-bit value, SC[2:0], as shown in Table 2 below. Thus, when the shift count 202 is eight (SC[2:0] = 000), and the selεct valuε is ninε (X[4:0] = 01000), thε output of thε subtract circuit 203 will bε: X[2:0] - SC[2:0] = 0; a valuε that corresponds to the leftmost bit position within each of thε parallεl-load registers 165. This is a desired result as thε lεftmost bit positions within rεgistεrs 165 havε symbol latεnciεs 9 and 17 whεn thε shift count is eight. The multiplexer 209 will genεratε a sεlεct signal 204 (SEL[1:0]) to sεlεct thε data valuε from register 1651 (symbol latency = 9) to source thε tap data valuε (this opεration is discussed below). As a further examplε, whεn thε shift count 202 is one and the sεlect value 200 is nine, the output of the subtract circuit 203 will be: 000-001 = 111 (dεcimal 7); thε rightmost bit position within each of the parallel-load registers 207. Again, this is a desirεd rεsult as the rightmost bit positions with rεgistεrs 165 havε symbol latencies 9 and 17 when the shift count is one.
Figure imgf000028_0001
Table 2
Figure 13 illustrates an exemplary embodimεnt of thε sεlεct logic 201 of Figurε 12. The select logic 201 includes a comparator circuit 215 to compare the latency select value 200 with N (thε sizε, in bits, of each of registers within buffer circuit 210), a summing circuit 217 to sum the shift count 202 with N (therεby genεrating SC+N), and a comparator circuit 219 to compare the latency select value 202 with the output of the summing circuit 217. If the latency select value 200 is less than N, the output of comparator 215 will go high, causing inverter 223 to drive the high order bit of select signal 204 low and OR gate 221 to drive the high order bit of the sεlect signal 204 high. That is, SEL[1:0] = 01 so that multiplεxεr 209 will sεlect the shift register 161 to source the tap data value; the desired result when thε sεlεct value 200 is lεss than N. If thε select value 200 is greater than or equal to N, the output of comparator 215 will go low, thereby driving thε high order bit of selεct signal 204 high, and enabling the output of comparator 219 to control, via OR gatε 221, thε statε of the low order bit of select signal 204. If the latency selεct valuε 200 is less than the output of summing circuit 217 (SC+N), the output of comparator 219 will be low causing select signal SEL[0] to be low, therεby producing SEL[1:0] = 10 and sεlεcting parallel-load register 165j to source the tap data value. If the latency select value 200 is greatεr than or equal to the output of the summing circuit 217, the output of comparator 219 will be high, resulting in a select value of SEL[1:0] = 11, thereby selεcting parallεl-load register 1652 to source the tap data value.
Reflecting on thε structure of Figurε 13, it should bε noted that the summing circuit and comparators may have numerous implementations depending on the size of N and the number of bits used to form the latency select value 200 and shift count 202. For example, where the latency select value 200 and shift count 202 have thε five- and three-bit configurations shown, and N is eight, the sum of the shift count and N (performed by circuit 217 in Figure 13) may be formed simply by including an additional bit in parallel with the threε shift count bits, the additional bit forming the most significant bit of the resulting sum (i.e., sum[3]) while SC[2:0] form the less significant threε bits of thε sum (i.ε., sum[2:0]). As anothεr εxample, the comparator 215 may be implεmεntεd by a NOR gatε having inputs couplεd to X[4] and X[3]. By this arrangement, thε X<N output will be high only if both X[4] and X[3] are low. Numerous other logic circuits may be used to implement the selεct logic circuit 201 of Figure 12 in alternativε εmbodiments. More generally, specific numbers of bits and registers have beεn described for purpose of example only. Alternativε embodiments may includε diffεrεnt numbers of registεrs having various sizεs, and latency select values and shift count values having different sizes. Also, any circuit for selεcting a data value based on a latency selεct value may alternatively be used without departing from the spirit and scope of the presεnt invεntion. Figure 14 illustratεs a gεnεralizεd selεct circuit 230 that may bε usεd to select Q tap values from the buffεr circuit 210 of Figurε 12. Thε sεlεct circuit 230 includes a switch matrix 231 and tap select logic 235. In the embodiment of Figure 14, each of the possiblε tap data sources within the buffer circuit 210 (i.e., the rightmost four bits within shift register 161 and all the bits within the parallel-load registers 165) are coupled to respective column lines 234 of the switch matrix 231, and each of the Q tap outputs are coupled to respεctivε row linεs 236 of thε switch matrix 231. A switch clement 233 is providεd at εach row-column intεrsεction to enable the tap data source for the column to be selectively coupled to the tap output for the row. The tap selεct logic 235 outputs a rεspεctivε onε of εnablε signals Ei-E2o to εach column of switch elements based on latency selection values XΪ-XQ and shift count, SC. h the embodiment of Figure 14, each enable signal includes Q component signals coupled respectively to the Q switch elements within a corresponding column. Thus, if the column 1 data value (i.e., thε data value stored in shift registεr position 4), is selεctεd to bε thε data source for tap Q, then selεct signal E1[Q:1]=100..00. More genεrally, Ej[i]=l for each column data value, j, to be coupled to a tap output, i. By this arrangement, the Q tap outputs may bε sεlεctεd from among thε complete range of data values stored within buffer circuit 210. In one embodiment, the selεct logic includes combinatorial logic that operates as dεscribed in refεrence to Figure 10 to genεratε εach εnablε signal. Altεrnativεly, a statε machine or other processing logic may be used to generate the enable signals in accordance with the latency selection values and shift count. Figurε 15 illustratεs an εmbodimεnt of a switch element 233 that may be used within thε switch matrix 231 of Figurε 14. Thε switch εlεment includes a transistor 235 having source and drain terminals coupled betweεn thε ith row linε 236; (TAP;) and thε jth column line 235j (DATAj) of the switch matrix, and a gate tεrminal couplεd to rεcεivε the ith component signal of enablε signal j (i.ε., Ej[i]). Thus, when the Ej[i] is high, indicating that ith tap output is to be sourced by the data value at the jth position within the range of selectable data values, transistor 235 is switched on to couple the sεlected data source to the tap output. Other types of switching elεments may bε usεd in altεrnati ve εmbodimεnts .
Equalizing Circuits
As discussed above in refεrencε to Figurε 3, thε tap values selected by the tap selεct logic 139 and sεlεct circuit 128 may be used in a number of different equalizing circuits to counteract distortion evεnts. In one equalizing recεivεr εmbodiment, illustrated in Figure 16, an equalizing output driver 140 is coupled in parallel with the sampling circuit 123 to drive an equalizing signal back onto the signal path 122 during each symbol reception interval (i.e., symbol time during which a valid symbol is presεnt at the input of the receiver). By this arrangement, latent distortions arriving at thε rεcεiver during a symbol reception interval may be canceled (or at least reduced) by operation of the εqualizing output drivεr 140.
Figure 17 illustratεs thε rεcεivε circuit of Figure 16 in greater detail. As shown, the sampling circuit 123 may include any number of preamplifiers 240!-240N coupled in series with a sampler 241. The sampler 241 may be any type of circuit for detεcting thε level of an input signal, including but not limited to a latching circuit that latches the signal level in response to a rising or falling clock edgε, or an integrating circuit that integratεs the input signal over a finite period of time (e.g., a symbol time or portion of a symbol time). Thε εqualizing output drivεr 140 may bε coupled to the signal path 122 (i.e., the input of the first prεamplifiεr 240ι) or, alternatively, to the output of any of the preamplifiεrs 240. Also, as discussed below, the output drivεr 140 may be couplεd to the sampler 241 to affect the sampling operation. In one embodimεnt, thε εqualizing output drivεr 140 of Figures 15 and
16 is clocked by an equalizer clock signal, EQCLK, that is offset from the clock signal usεd to timε the sampling instant and therefore to define the symbol reception interval (i.e., receive clock signal, RCLK), as necessary to align edges of the equalizing signal (i.e., state transitions) with edges of the incoming data signal. This timing relationship is illustrated by Figure 18. As shown, the equalizεr clock signal is aligned with edges of the incoming symbol stream so that equalization values are transmitted onto the signal path concurrently with corresponding symbol reception intervals. As discussed below, the equalizεr clock signal may bε furthεr offsεt from thε rεcεivε clock signal as shown by arrow 245 to account for the time required for the εqualization data (i.ε., selected tap values) to propagatε through the equalizing output driver 140 or other equalizing circuit.
Figure 19 illustrates a current-sinking output driver 250 that may be usεd to implεmεnt thε equalizing output driver 140 of Figure 16. The output driver includes a plurality of sub-driver circuits 251^251^ each sub-driver circuit 251 including a current source 257, clocking transistor 255 and data tap transistor 253 coupled in seriεs between an output node 254 and a refεrεncε voltage (ground in this examplε). Control terminals (e.g., gate terminals) of the data tap transistors 253 of the sub-driver circuits 251 arε couplεd to rεcεive respεctive data tap values (designatεd EQDΪ-EQDN in Figure 19) from a selεct circuit, control terminals of the current sources 257 are coupled to respεctivε tap wεight valuεs, EQWPEQWN, and control terminals of the clocking transistors are coupled in common to rεcεive thε εqualizεr clock signal, EQCLK. By this arrangεmεnt, when the equalizer clock signal goes liigh, εach of thε sub-drivεr circuits will source a current according to its respεctivε tap wεight and data tap inputs. For εxamplε, referring to sub-driver circuit 251ι, if tap data value EQDΪ is low, no current (or negligiblε) current will be drawn via output node 254. By contrast, if tap data value EQDi is high, thεn thε sub-drivεr circuit 251 \ will draw a current from the output node
254 (and therefore from the signal path 122) according to the tap weight,
EQWt. As discussed bεlow, thε tap wεights providεd to thε output drivεr 250 or othεr εqualizing circuits described herein may be prεdεtεrminεd valuεs, or may be determinεd dynamically according to thε lεvεl of the distortions to be reduced. Because the sub-driver circuits 251 are coupled in parallel to the output node, the overall equalization signal genεratεd by output driver 250 during a given symbol time is the sum of contributions from the individual sub-driver circuits 251. Note that the output driver 250 outputs an equalization signal only when the equalizer clock signal is high (i.e., evεn phasεs of EQCLK). An additional instance of output driver 250 may be provided to output an equalization signal when a complemεnt εqualizεr clock signal (i.e., /EQLCK) is high.
Figure 20 illustratεs an embodiment of a push-pull type of sub-driver circuit 260 that may be used within an εqualizing output driver instεad of thε pull-down sub-drivεr circuits 251 described in refεrεncε to Figure 19. hi the push-pull type of sub-driver circuit 260, current is eithεr sourcεd or sunk via the driver output according to the state of the tap data value, EQDi. Thε sub- drivεr circuit 260 includes switching transistors 263 and 265, and AND gate 261. A first input of the AND gate 261 is coupled to receivε the tap data value, EQDj, and a sεcond input of thε AND gatε 261 is couplεd to a clock line to receivε thε εqualizεr clock signal, EQCLK. Thε output of thε AND gatε 261 is coupled to the gate terminals of transistors 263 and 265 such that, during each high phase of the equalizer clock signal, thε tap data valuε is passεd to thε gatε tεrminals of transistors 263 and 265 to εstablish thε output statε of thε sub-drivεr circuit 260. That is, εvεry other half cycle of the equalizer clock signal constitutes an output enable interval for the sub-driver circuit 260. If the tap data value, EQDj, is high during a given output enable interval, transistor 265 is switched on, causing thε sub-drivεr circuit 260 to sink current via the output nodε (OUTj). Conversely, if the tap data value is low during the output enable interval, transistor 263 is switched on to source current via the output nodε. Also, though not shown in Figurε 20, a pull-down biasing circuit (ε.g., current source) may be coupled between the pull-down data tap transistor 265 and ground, and a pull-up biasing circuit may be coupled betwεεn the pull-up data tap transistor 263 and the supply reference voltage (e.g., VDD) to enable weighted control of the current sourcing and sinking strength of the push-pull sub-drivεr circuit 260. Further, an additional instance of the sub-driver circuit 260 may be provided with a complement equalizer clock signal (/EQCLK) and complemεnt tap data valuε (/EQDj) being input to AND gate 261 to εnable the sub-driver circuit 260 to output an equalizing signal during the alternatε half cycle of the equalizer clock signal.
Figure 21 illustrates another embodimεnt of a sub-driver circuit 275 that may be used within an equalizing output driver. The sub-driver circuit 275 includes a differential transistor pair 277 having control terminals coupled to outputs of AND gates 261 \ and 2612, respectively. A tap data value (EQDi) and an equalizεr clock signal (EQCLK) are input to AND gate 261 \, and a complemεnt of thε tap data valuε (/EQDj) and thε equalizer clock signal are input to AND gate 2612- By this arrangement, the tap data value and complement tap data value are applied to respective inputs of the differential pair 277 during evεry other half cycle of the equalizer clock signal. Output nodes of the differential pair 277 are pulled up through respεctivε rεsistivε loads 283 (R), and source terminals of the differential pair are coupled to ground via a current source 281. The resistivε loads 283 may bε, for example, termination elεments coupled to thε signal path (not shown) rather than resistive εlεments included within the sub-driver circuit 275. Accordingly, the sub-driver circuit 275 is enabled, during evεry other half cycle of the equalizer clock signal, to output a differential εqualizing signal on output nodεs OUT,- and /OUT; in accordance with the complemεntary tap data valuεs, EQDj and /EQDi. A counterpart instance of sub-driver circuit 275 may be provided to generatε a diffεrential equalizing signal during the alternate half clock cycle of the equalizεr clock signal. The current source 281 is controlled by the tap weight value, EQW,-, in the manner described in reference to Figure 19, though different weighting schemes may be used in alternative embodimεnts (e.g., using weight-biasεd pull-up εlεmεnts in place of resistive elεmεnts 283).
Figure 22 illustrates an alternativε typε of εqualizing circuit 290 that may bε usεd in εmbodimεnts of thε invεntion. Instεad of driving an εqualization signal onto thε signal path to affect the signal levεl of an incoming signal, εqualization is pεrformεd in conjunction with preamphfication of thε incoming signal, and therefore affects the level of preamphfication applied to thε incoming signal. That is, thε εqualizing circuit
290 affects the preamplifiεd signal lεvεl instεad of thε signal level present on the signaling path.
Equalizing circuit 290 includes a differential amplifier 294 formed by differential transistor pair 291, biasing current source 292 and resistive loads
293. Differential input signals are supplied to gate terminals of transistor pair
291 such that differentially amplified output signals are gεnerated on output lines POUT and /POUT- In one embodimεnt, output lines POUT and /POUT are coupled to input terminals of a differential amplifier within a sampling circuit so that amplifier 294 effεctively forms a first stage in a two-stage amplifier (i.e., amplifier 294 is a preamplifier).
Equalizing circuit 290 additionally includes a level shifting circuit 296 coupled to the differεntial amplifier 294 to provide preamplifiεr equalization. The levεl shifting circuit 296 includes a pair of sub-circuits 2981 and 2982 εach coupled betwεen a respective one of the diffεrential amplifier outputs
(POUT and POUT) and a clocking transistor 299. Each of the signal subcircuits
298 includes a respective plurality of data tap transistors (295!-295N and 297!-
297N) coupled in parallel betwεεn thε differential amplifier output and the clocking transistor 299. The control terminals of the data tap transistors 295!-
295N are coupled to receivε thε sεlεcted data tap values, EQD!-EQDN, respεctively, and the control terminals of the data tap transistors 297!-297N are similarly coupled to receive complemεnt vεrsions of thε sεlected data tap values, /EQD1-/EQDN. h one embodiment, each of the data tap transistors 295 is sized (e.g., by width-length ratio) to achieve a respective tap weight EQ N-EQWi. By this arrangemεnt, each data tap value may be coupled to the control terminal of a selεctεd onε of thε data tap transistors 295 according to the desirεd tap wεight. Thε transistors 297 are similarly weighted and therefore allow coupling of the complemεnt data tap valuεs according to desired tap weights. The weights of the individual data tap transistors 295 (and 297) may bε incrεmεntally rεlatεd (i.e., EQW!=EQW2+K=EQW3+2K ..., where K is a constant), exponentially related (i.e., EQW!=EQW *K=EQW3*K2...) or may have any othεr dεsirεd relationship (including having the same weight values or including subsets of weight values that are thε same).
The clocking transistor 299 is switched on during every other half cycle of thε equalizer clock signal to enable the operation of the subcircuits 298. The subcircuits 298 operate to increasε or dεcrease the difference between the prεamplifiεd output signals (or εvεn change the polarity of thε diffεrence) by drawing more current from one of the preamplifier output lines (POUT or /POUT) than the other in accordance with the selεctεd data tap valuεs. Thus, the subcircuits 298 act to differentially shift the level of the preamplified output signal generated by differential amplifier 294. An additional instance of the equalizing circuit 290 may be provided to enable preamplifier equalization during thε alternate half cyclε of thε εqualizεr clock signal.
Figure 23 illustrates an alternative levεl shifting circuit 305 that may be substituted for circuit 296 of Figure 22. In circuit 305, differential pairs of data tap transistors 307 307N are coupled to output lines POUT and /POUT in the same manner as in circuit 296, but instead of sizing the data tap transistors to achieve tap weighting, tap weighted current sources 311!-3 HN are coupled in series with the diffεr ntial pairs of data tap transistors 307!-307N, respectively. For examplε, current source 31^ is controlled by (i.e., draws a bias current according to) weight value EQWi and is couplεd via clocking transistors 309! to data tap transistors 307]. Similarly, current source 3112 is controlled by weight valuε EQW2 and is couplεd via clocking transistors 3092 to transistors 3072, and so forth. By this arrangement, the weight values EQWJ-EQWN may be configured (e.g., via run-time calibration or production time programming) as necessary to establish a desirεd equalizing signal contribution from each differεntial pair of data tap valuεs 307. An additional instance of thε equalizing circuit 290 may be provided to enable preamplifier equalization during the alternate half cyclε of thε εqualizεr clock signal (i.e., by driving clocking transistors 309 with complement equalizing clock, /EQCLK).
Figure 24 illustrates anothεr typε of εqualizing circuit 320 that may be used in embodiments of the invεntion. Instead of driving an equalization signal onto the signal path to affect thε signal lεvel of an incoming signal, or affecting the preamplified signal levεl, a lεvel shifting circuit 330 is coupled to low impedance inputs of a differεntial sampling circuit 328, and is usεd to affect the levεl of thε input signal bεforε the sampled signal is captured. The sampling circuit includes differential transistor pair 329 to prechargε input nodes SΓN and /SΓN according to thε state of a differential input (e.g., the output of a preamplifier 294 of Figure 22, or a differential data signal), during a first half cycle of the receive clock (which enablεs clocking transistor 331).
During a second half cycle of the receivε clock signal, transistors 321 and 325 arε switched on by the low-going recεivε clock signal, thereby enabling a cross-coupled latch formed by transistors 322, 323, 325 and 326 to latch the state of the prechargεd signal lεvεls on nodεs SΓN and /SΓN-
The lεvεl shifting circuit 330 is similar to thε circuit 296 of Figurε 22 εxcεpt that clocking transistor 341 is εnablεd by thε receive clock signal
(RCLK) instead of the equalizer clock signal, the equalizer clock signal being used to switch on switching transistors 335!-335N and 3391-339N during every other half cycle. Data tap transistors 333!-333N, which are controlled by respective tap data values EQD^EQDN, are coupled in sεries with the switching transistors 335]-335N, respεctivεly. Similarly, data tap transistors 337!-337N arε couplεd in sεries with switching transistors 339!-339N and are controlled by respective complemεnt tap data valuεs /EQD!-/EQDN- hi onε εmbodimεnt, thε data tap transistors 333, 337 and switching transistors 335, 339 are sized to provide different current draws according to predεtεrminεd weights, EQW1-EQWN, thereby permitting different data taps to make different level-shifting contributions, hi one embodimεnt, for εxamplε, the switching transistors 335 and 339 are binary weighted such that, when switched on, the current draw through transistor pair 333N/335 is 2N-1 times the current through transistor pair 3331/3351 (and the current draw through transistor pair 337N/339N is 2 _1 times the current through transistor pair 337^339! . Other weighting schemes may also be used including, without limitation, thermomεtεr coding of high-gain transistor pairs, linear weighting schemes, or any combination of exponential (e.g., binary), linear and fhermometεr coded weightings.
In one embodiment, the εqualizεr clock is phasε advanced relative to the receive clock signal such that transistors 337 and 339 are switched on in advance of clocking transistor 341. By this arrangement, transistors 333 and 337 arε poised to shift the levεl of thε sampling circuit input nodes, SIN and
/SΓN, when thε receive clock signal goes high. Thus, when the recεivε clock signal goes high, sampling circuit input nodes SIN and /SΓN are diffεrentially discharged according to the tap data values EQDι-EQDN, /EQD!-/EQDN and the respεctive weights of transistors 333 and 337. Consεquεntly, thε signal lεvεls at thε input nodεs, SIN and /SIN, of sampling circuit 328 arε differentially shifted by the levεl shifting circuit 330 to reduce static offsets in the incoming data signal (applied to control terminals of differential pair 329) caused by reflections or other distortions. Figure 25 illustrates an alternativε levεl shifting circuit 342 that may bε substitutεd for circuit 330 of Figurε 24. The level shifting circuit 342 includes data tap transistors 333, 33 and equalizεr-clock-εnablεd switching transistors 335, 339 couplεd as described in reference to Figure 24. However, rather than being couplεd to a clocking transistor 335, thε source terminals of transistors 335I-335N are coupled to ground via capacitive εlements 334r 334N, respectively, and the source terminals of transistors 339!-339 are similarly coupled to ground via capacitive elements 338^338N- By this arrangemεnt, respective variable capacitances are coupled to the low impedance inputs, SΓN and /SIN, of the sampling circuit 328 according to the states of the tap data values EQD!-EQDN and complement data tap values EQD!-EQDN applied to the inputs of data tap transistors 333 and 337. Thus, different levels of capacitance are addεd to thε sampling circuit input nodεs, STN and /SIN, according to the tap data values, effectively changing the discharge rates of the input nodes and therεforε affecting the prechargεd signal lεvel at the input nodes as desired to reduce signal distortions. In the embodiment of Figure 25, the data tap transistors 333, 337 and switching transistors 335, 339 have uniform sizes (i.ε., uniform weighting), and the capacitive elements 334, 338 have weighted capacitive values to permit a broad range of capacitances to be coupled to thε input nodεs of sampling circuit 328. For example, in onε embodiment, the capacitive elεments 334 are implemεntεd by source-to-drain coupled transistors and are binary wεightεd
(ε.g., by adjusting transistor width-length ratios) such that capacitive element
335 has twice the capacitance of capacitive elεmεnt 335ι, and capacitive elemεnt 335N has 2N"1 timεs thε capacitance of capacitive εlεment 335i. Other weighting relationships (e.g., thermomεtεr coding, linear, uniform, etc.) may also be used. Also, the data tap transistors 333, 337 and/or switching transistors 335, 339 may be weighted in alternativε εmbodiments instead of
(or in addition to) the capacitive elemεnts 334, 338.
High Speed Tap Selector
As discussed above in refεrεncε to Figure 3, an incoming data signal may include two symbols per receivε clock cyclε (sometimes referred to as a "double data ratε" signal), and εach symbol may havε more than two possiblε statεs (i.ε., may have a signal levεl falling within morε than two distinct ranges of signals). Also, the receivε clock frequency may be so high that by the time a sampled data value is loaded into thε buffεr circuit 132, the data value already has a latency of several symbol times. All thesε factors present challengεs to thε buffεring and sεlεction of tap valuεs dεscribεd in reference to Figure 3.
Figure 26 illustratεs an equalizing recεiver 350 according to an .embodiment of the invεntion. Thε rεcεivεr 350 includes a double data rate sampling circuit 351, shift registεr 353, sεlεct circuit 355 and equalizing output drivεr 357. Thε sampling circuit 351 includes a pair of sub-circuits 36l! and 3612 to sample the incoming data signal in response to rising edges in the receivε clock (RCLK) and complement receive clock (/RCLK), respεctively. Falling clock edges may alternatively be usεd to timε thε sampling instant. Data samples captured in responsε to εdges of the rεcεivε clock arε referred to herein as even phase data, and data samples captured in rεsponsε to εdges of the complemεnt receivε clock arε rεfεrrεd to as odd phasε data. Thus, sampling circuit 351 outputs εvεn phasε data (EVEN IN) and odd phasε data (ODD IN) to the shift rεgistεr 353 via signal linεs 362i and
3622, rεspεctivεly. Thε even and odd phase data values are stored within the shift registεr to providε a sourcε of sεlεctablε tap values to the selεct circuit
355. In thε εmbodimεnt of Figurε 26, thε dεad rangε is assumεd to bε fivε symbol latεnciεs (othεr dεad rangεs may be used) such that data values Dτ+5-
Dτ+χ are provided to the selεct circuit 355, subscript T+5 indicating a latεncy of fivε symbol timεs relative to sampling instant, T. The selεct circuit 355 includes N tap selectors, 365!-365N, that selεct from among thε plurality of data valuεs stored within the shift registεr 353 and output a sεlεcted tap data value to a respective one of N output sub-drivers 369!-369N within the equalizing output drivεr 357. Each of thε output sub-drivεrs 369, in turn, drivεs a component εqualizing signal onto thε signal path 122. In altεrnativε εmbodimεnts, thε εqualizing output drivεr 357 may bε replaced by an equalizing circuit that operates within a preamplifiεr circuit (not shown in Figurε 26) or sampling circuit 351 as described above in refεrence to Figures 17-20.
Figure 27 illustrates the shift register 353 and one of the tap selectors 365 of Figure 26 according to more specific embodiments. Thε shift rεgistεr includes a pair of shift sub-circuits 383] and 3832 to store evεn phasε data and odd phase data, respectively. In one embodimεnt, εach of the shift sub- circuits 383 includes a numbεr of storagε εlεmεnts 381 (e.g., latches) coupled in a daisy chain configuration (i.e., output to input) to enablε an input data valuε to bε shiftεd progressively from a first (i.e., leftmost) storage elεmεnt 381 in thε chain to a last (rightmost) storage εlεment 381 in the chain. Each of the shift sub-circuits 383 is responsive to the recεivε clock and complεmεnt rεcεivε clock signals such that the contents of each shift sub-circuit 383 is shifted during each half clock cycle of the receivε clock signal. Thus, assuming that a stream of incoming symbols includes the data sequence A, B,
C, D, etc., then evεn phasε data values A, C, E, G, I, etc. will be shifted into shift sub-circuit 383ι and odd phase data values B, D, F and H will be shifted in to shift sub-circuit 3832. Because the contents of the shift sub-circuit 383! arε shifted twicε pεr εvεn phasε data reception, two instances of each even phase data value will be stored in the shift sub-circuit 383χ. The second instance of each even phase data value stored in shift sub-circuit 383ι is designated by a prime (i.e., ') in Figurε 27 to indicate that the data value was loadεd synchronously with thε loading of a newly received odd phase data value into shift sub-circuit 3832. Similarly, two instances of each odd phasε data valuε arε stored in the shift sub-circuit 3832, with the second instance of the odd phase data value being designatεd by a primε to indicate that the data valuε was loadεd synchronously with thε loading of a newly received even phase data value into shift sub-circuit 383!. Thus, from the pεrspεctive of the tap selector 365, the shift sub-circuits 383 collectively contain a sequence of data values, A', B, C, D, E' F, G', H, that may be usεd to generate odd phase equalizing signals (i.e., driving an equalizing signal onto thε signal path or affεcting signal levels within a preamplifier or sampling circuit during odd phase symbol reception), and a sequεncε of data valuεs, B', C, D', E, F', G, H', I, that may be usεd to gεnεratε εvεn phasε εqualizing signals. Accordingly, thε outputs of each of the storage elements 381 within shift sub- circuit 383! are coupled to respective inputs of an even tap data select circuit 387! within the tap selector 365, and the outputs of each of the storage elεmεnts 381 within thε shift sub-circuit 3832 are coupled to respective inputs of an odd tap data sεlect circuit 3872 within the tap selector 365. The even and odd tap data selεct circuits 387 are responsive to a select signal, S[2:0], to output selεctεd tap data values from the even and odd phases sequences of data values, respεctively. Thε sεlect signal may be generated, for example, by tap the select logic 139 described in refεrεncε to Figurε 3. The output of the evεn tap data sεlεct circuit is clocked into a flip-flop
3911 (or other storage elεmεnt) at thε rising εdge of thε rεcεive clock signal
(RCLK) so that, at any given time, the output of flip-flop 3911 is delayed by two symbol times relative to the most latεnt data valuε supplied to the evεn tap data sεlεct circuit 387!. Similarly, thε output of thε odd tap data select circuit
3872 is clocked into a flip-flop 3912 (or other storage elemεnt) so that, at any givεn timε, the output of flip-flop 3912 is delayed by two symbol times relativε to thε most latεnt data valuε suppliεd to thε odd tap data select circuit
3872. Thus, the flip-flops 391 effεctivεly increasε the latency of selected even and odd data tap values by two symbol times. Sεlεct circuits 393i and 3932 arε provided to extεnd thε ovεrall latεncy rangε of thε even and odd data tap selεctions within tap sεlector 365 by allowing sεlection of tap data directly from the evεn and odd data inputs to the shift registεr 353 (i.ε., EVEN IN and ODD IN) or from the outputs of flip-flops 391. Selεct bit S[3] is provided (ε.g., by the tap select logic 139 of Figure 3) to select between the fast path data (i.e., connections 384! and 3842 to the inputs of the sub shift circuits 383) and the selected data values stored in flip-flops 391. Flip-flops 395ι and 3952 (or other storage elemεnts) arε providεd to synchronizε thε outputs of multiplexers 393ι and 3932 with the receivε clock and complement receive clock, respεctivεly. Thus, εven and odd data tap values, ETD and OTD, each having a range of latencies according to the depth of the shift sub-circuits 383 and the number of fast path taps (of which signal lines 384! and 384 are εxamples) are output to the equalizing circuit (not shown in Figure 27) to enablε even and odd phase equalization of an incoming signal. Figurε 28 illustrates an equalizing receiver 405 for receiving a double data rate, multilevel input signal according to an embodiment of the invention. The receiver 405 includes a sampling circuit 407, shift register 411, select circuit 421 and εqualizing output drivεr 427. Thε sampling circuit includes evεn and odd phasε sampling sub-circuits 409i and 4092 to capture even and odd phase samples of the incoming multilevel data signal and to generate a multi-bit output indicative of the sampled signal levεl. For εxamplε, in onε εmbodiment, the incoming data signal has one of four possible signal levεls, εach lεvel being defined by a distinct range of voltages. In the specific embodiment depicted in Figure 28, each sample is resolved (i.e., by sampling sub-circuits 409) to a thermomεter code in which bits A, B, and C havε valuεs according to which of four voltage ranges the sampled signal level falls within. Referring to Figure 29, for example, bits A,B and C are set according to the following relationships betwεen the sampled signal, Vs, and high, middle and low threshold voltage lεvεls:
Figure imgf000044_0001
Table 3
Other encoding schemεs may be usεd in alternative embodiments. Also, more or fewer threshold lεvels (and thεrεfore signal ranges) may be used, and current levels may be used to indicate signal levεl instead of voltage levels.
Once the samplεd signal is r solvεd to a pattern of binary bits, A, B and C (or some other number of bits), each of thε bits is input to a respective one of shift registers 413A-413C and used to source a tap value for sεlection by a respective set of select circuits 422A~422Q (each selεct circuit including N tap sεlεct sεlεctors 423!-423N). Each of thε shift rεgistεrs 413 and select circuits 422 operates generally as described in reference to Figures 21 and 22 to gεnεrate a set of selected tap values, 424A-424C- Corresponding tap values from within each set 424 are provided to a respective one of output sub-drivers 429!-429N within εqualizing output drivεr 427, whεre thεy arε used to genεratε a multi-level equalization signal. For example, the tap valuεs output by tap sεlector 4231 within each of the select circuits 422 are input to output sub-driver 429 j of the εqualizing output drivεr 427.
Equalization Clock Signal Generation
As discussed briefly in reference to Figure 18, it is desirable for the equalization signal genεratεd by a rεceive-sidε equalizing output driver to bε drivεn onto thε signal path in phasε alignment with data eyes in the incoming data signal. While the recεivε clock (or complεmεnt rεcεivε clock) may bε usεd to clock thε εqualizing output drivεr (or preamp or sampling circuit equalizer), propagation delay through the equalizing driver tends to become significant in high frequεncy systems, producing undesired timing offset betwεεn thε incoming data signal and thε εqualization signal, hi onε εmbodimεnt, clock data recovery circuitry within an equalizing receiver is used to genεratε an εqualization clock signal (EQCLK) that is phasε advanced relative to the receive clock signal according to the propagation delay (i.e., clock-to-Q) of an equalizing output driver. By this timing arrangement, illustrated in Figure 30, the equalizing output driver outputs an equalization signal having the desired phase relation with the incoming data signal. As shown, by advancing thε εqualization clock relative to the receive clock according to the clock-to-Q delay of the) εqualizing output drivεr, a dεsired phase relationship bεtwεεn thε incoming data signal (RX DATA) and εqualization signal (EQ DATA) is achieved. Note that, in the exεmplary diagram of Figurε 30, the equalization data tap is assumed to have a symbol latency of five symbol times, such that an equalization signal basεd on received symbol A is transmitted by the equalizing output driver during the reception interval for symbol F. Figurε 31 illustratεs an embodiment of an equalizing receiver 450 that generates recεivε and εqualization clock signals having the phase relationship shown in Figure 30. The receiver 450 includes a sampling circuit 451, shift register 453, clock-data-recovεry (CDR) circuit 457, application logic 455, tap data selεctor 461, signal generator 462, equalizer clock genεrator 459, and εqualization data source selεctor 463. An incoming data signal (DATA) on signal path 122 is sampled by the sampling circuit 451 in response to a recεive clock signal (RCLK). The samples are output to the shift register 453 where they are stored for parallel output to the application logic 455 and the CDR circuit 457. In the εmbodimεnt of Figurε 31, thε receive clock signal includes multiple component clock signals including a data clock signal and its complemεnt for capturing even and odd phase data samples, and an εdge clock signal and complemεnt edgε clock signal for capturing εdgε samples (i.e., transitions of the data signal between successive data eyes). The data and edgε samplεs are shifted into the shift registεr 453 and then supplied as parallel words (i.ε., a data word and an εdgε word) to a phasε control circuit 467 within the CDR circuit 457. The phasε control circuit 467 compares adjacent data samplεs (i.e., successivεly receivεd data samples) within the data word to determine when data signal transitions havε taken place, then compares an intervεning εdgε samplε with the preceding data sample (or succεεding data samplε) to detεrminε whεthεr thε εdgε sample matches thε preceding data sample or succeeding data sample. If the εdge samplε matches the data sample that precεdεd thε data signal transition, then the edge clock is deεmεd to be early relativε to thε data signal transition. Conversely, if the edgε samplε matches the data sample that succeeds the data signal transition, then the edge clock is deemεd to be latε relativε to thε data signal transition. Depending on whether a majority of such εarly/latε determinations indicate an early or late edgε clock (i.e., thεrε arε multiple such determinations duε to thε fact that εach edge word/data word pair includes a sequεnce of edge and data samplεs), thε phasε control circuit 467 asserts an up signal (UP) or down signal (DN). If there is no early/latε majority, neither the up signal nor the down signal is assertεd. So long as a calibration signal 474 (CAL) from thε application logic 455 remains dεassεrtεd, the up and down signals, when assertεd, pass through AND gates 4681 and 4682, respectively, to up/down inputs of mix logic 471.
The mix logic circuit 471 receivεs a set of phase vectors 472 (i.e., clock signals) from a reference loop circuit 470. The phase vectors have incrementally offset phase angles within a cycle of a reference clock signal (REF CLK). For examplε, in onε εmbodimεnt, thε rεference loop outputs a sεt of εight phasε vεctors that arε offsεt from one another by 45 degrees (i.e., choosing an arbitrary one of the phase vectors to have a zεro dεgreε anglε, the remaining sεvεn phase vectors have phase angles of 45, 90, 135, 180, 225, 270 and 315 degreεs). The mix logic 471 maintains a phase count value which includes a vεctor sεlεct component to selεct a phasε-adjacent pair of the phase vectors (i.e., phase vectors that bound a phase angle equal to 360°/N, where N is the total number of phase vectors), and an interpolation component (TNT) which is output to a mixer circuit 473 along with the sεlεctεd pair of phasε vectors (VI, V2). The mixεr circuit mixes the selected pair of phase vectors according to the interpolation component of the phase count to genεratε complementary edgε clock signals and complemεntary data clock signals that collectively constitute the receivε clock signal.
Thε mix logic 471 increments and decrements the phase count value in response to assertion of the up and down signals, respεctivεly, thεreby shifting the interpolation of the selεcted pair of phase vectors (or, if a phase vector boundary is crossed, selεcting a nεw pair of phasε vectors) to incremεntally retard or advance the phase of the recεivε clock signal. For example, when the phase control logic 467 determines that the edge clock leads the data transition and asserts the up signal, the mix logic 471 increments the phase count, thereby incrementing thε interpolation component of the count and causing the mixer to incrementally increasε thε phase offsεt (retard the phasε) of thε receive clock signal. At some point, the phasε control signal output begins to dither between assertion of the up signal and the down signal, indicating that edgε clock components of the recεivε clock signal havε bεcome phase aligned with the edges in the incoming data signal.
The equalizεr clock gεnεrator 459 receives the phase vectors 472 from the reference loop 470 and includes mix logic 481 and an equalizer clock mixer 483 that operate in the same manner as the mix logic 471 and receive clock mixer 473 within the CDR circuit 457. That is, the mix logic 481 maintains a phasε count valuε that is incrementally adjusted up or down in response to the up and down signals from the phase control circuit 467. The mix logic selects a phase-adjacεnt pair of phase vectors 472 based on a vector select component of the phasε count, and outputs thε sεlεctεd vectors (VI, V2) and interpolation component of the phasε count (INT) to the equalizer clock mixer 483. The equalizεr clock mixεr 483 mixεs thε sεlεctεd vεctors in accordance with the interpolation component of the phase count to generate the equalizer clock signal, EQCLK. The equalizer clock signal, which may include complemεntary component clock signals, is output to the equalizing output driver 465 (or othεr typε of εqualization circuit as described above) to time the output of equalizing signals onto signal path 122.
The equalizer data source sεlεctor 463 is rεsponsivε to thε calibration signal 474 to sεlect either the tap selector 461 (which operates as described above to selεct data tap valuεs from the shift register 453 and/or one or morε parallεl rεgistεrs) or the signal generator 462 that outputs clock pattern 10101010 (e.g., a bi-stable storage elemεnt that toggles betweεn statεs in response to each EQCLK transition). When the calibration signal 474 is low, the equalization data source sεlector 463 selects the tap selector 461 to supply selectεd data valuεs to thε equalizing output driver 465. When the calibration signal 474 is high, the recεivεr 450 enters a calibration mode in which the signal generator 462 is selεcted to supply the clock pattern to the equalizing output driver 465. Also, in calibration modε, thε high statε of the calibration signal 474 disables AND gates 468i and 4682 from passing the up and down signals to the mix logic 471. Thus, the phase count within the CDR circuit remains unchanged in calibration mode, whilε up and down signals gεnerated by thε phase control circuit 467 are used to increment and decrement the phase count value within the mix logic 481. In one εmbodimεnt, no signals are transmitted on the signal path 122 while the recεiver 450 is in calibration modε, so that thε only signal prεsεnt at the input of the sampling circuit 451 is the clock pattern output by the equalizing output driver 465. By this arrangemεnt, εdgε and data samples corresponding to the clock pattern are captured in the shift registεr 453 and supplied to the phase control circuit 467 to determinε whether the receive clock signal (RCLK) is early or late relativε to thε clock pattern samples. Accordingly, the phase control circuit 467 will assert an up or down- signal (as the case may bε) to adjust the phase of the receive clock signal relative to the incoming data stream. Because the receive clock phase is effεctively locked, however (i.e., by operation of the AND gates 468), only the phase count within the equalization clock generator will be adjusted. Thus, the normal-mode CDR operation is εffεctively carried out in revεrsε whilε thε receiver 450 is in calibration mode. Instead of shifting the phase of the rεcεivε clock signal to achieve alignment with transitions in the incoming data signal, the phase of the equalizer clock signal is shifted to align transitions in the incoming data signal (i.e., the clock pattern output by thε εqualizing output drivεr) with thε rεcεive clock signal. By this operation, the equalizer clock signal is advanced relative to an edge clock component of the receive clock signal by a time substantially equal to the clock-to-Q delay of thε εqualizing output drivεr 465. Thus, thε overall effect of the calibration mode operation is to advance the phase of the equalization clock according to the clock-to-Q timε of thε εqualizing output drivεr as shown in Figurε 30. In this way, thε εqualizing output driver 465 drives an equalizing signal onto the signal path 122 in phase alignment with the incoming data signal.
In one embodiment, the calibration signal 474 is assertεd for a time interval previously determined to be sufficient to achieve phase alignment between transitions in the transmitted clock pattern and the edgε clock componεnt of thε rεcεivε clock signal. Alternatively, the up and down signals generated by the phase control circuit may bε monitored in the calibration modε to dεtermine whεn thε up and down signals bεgin to alt rnatε, thereby indicating that the desired phase alignment has bεεn obtainεd. In either case, after phase alignment has beεn obtainεd, thε calibration signal is deasserted to enablε normal opεration of the receive circuit. At this point, the CDR circuit returns to adjusting the phasε count within mix logic 471 in response to the up and down signals from the phase control circuit 467. Because the mix logic 481 within the equalizer clock genεrator 459 continues to respond to the same up and down signals, the phase offset betweεn thε εqualizεr clock signal and thε rεcεivε clock signal (i.e., thε phasε offsεt εstablishεd in thε calibration modε) is maintainεd as the phases of the two clocks are adjustεd. Thus, in normal-modε opεration, thε equalizer. clock signal and receive clock signal retain the phase offset established in calibration mode, but otherwise track onε anothεr.
It should bε notεd that signal patterns othεr than thε clock pattern 1010101 may be genεratεd by the signal generator 462 and used to achieve the desired phase relationship between the equalizer clock signal and thε receivε clock signal. For example, the signal genεrator may be implemented by a pseudo random bit sεquence (PRBS) genεrator that gεnerates a pseudo random bit sequence. More generally, any signal generator, random or otherwise, that generates a sequεnce of values having a sufficient transition density (i.e., transitions per unit time) to enable phase locking in the equalizing receiver 450 (i.e., phase locking betwεεn transitions in thε waveform output by output driver 465 and the receive clock signal) may be used to implemεnt signal gεnεrator 462.
Determination of Equalization Tap Latencies, Weights and
Polarities
Rεfεrring again to Figure 3, tap selεction logic may bε implemented in a number of different ways. In one embodiment, for example, the tap sεlect logic 139 includes a configuration circuit that may be programmed with configuration information that specifies the tap data sources to be selected by selεct circuit 128. Thε configuration circuit may include a nonvolatile memory, fusible circuit, εtc. that is programmed at production time according to the symbol latency, amplitude and polarity of empirically observed (or analytically detεrmined) distortions. Alternativεly, the configuration circuit may include memory (volatile or nonvolatile) which is initialized with predetermined configuration information during system startup. In yet anothεr εmbodimεnt, rεfεrrεd to hεrεin as a sεlf-calibrating embodiment, a signaling system includes circuitry to automatically detεrminε thε symbol latency, amplitude and polarity of distortions on the signaling path between a transmitter and receiver, and to program a configuration circuit within the tap selεct logic with configuration information that indicates the tap data sources to be selεctεd by a sεlect circuit and the tap wεights and polarities to be appliεd by an εqualization circuit.
In one sεlf-calibrating embodiment of the invention, a technique called εmbεddεd scoping is used to detεrminε the symbol latency, amplitude and polarity of signal path distortions. The symbol latency of a given distortion, oncε known, is used to select one or more tap data values having corresponding symbol latencies, and the distortion amplitudε and polarity arε used to detεrminε thε weight and polarity to be applied to the selected tap data valuε in genεrating an εqualization response. Also, the symbol latency of a given distortion may be used to detεrmine whether to counteract the distortion through transmitter preεmphasis or rεcεivεr εqualization (or both), and the overall range of symbol latencies for detεctεd distortions may bε used to dεtermine an appropriate dead range for the signaling system.
Embedded scoping involves iterativεly receiving a sequence of symbols in a recεiver and comparing thε rεcεived symbol sequence with a local generation of the sequεnce to confirm error-frεε rεcεption. With εach rεcεivε-and-confirm itεration, a thrεshold voltagε used to distinguish between symbol values in the incoming signal is offset from a calibrated level by a progressively largεr amount until a symbol in thε sεquεncε no longer matches the expected value. Thε threshold voltage offset at which the failure occurs is refεrrεd to hεrein as a pass/fail offsεt and represents a measure of the signal level at the sampling instant at which the failure occurred. Thus, by sweeping the threshold voltagε through a rangε of threshold voltages until the pass/fail offsets for each symbol in the symbol sequεncε havε bεεn detεcted, a sample plot for the incoming signal may be devεlopεd. Furthεr, by sweeping the recεivε clock signal through an incrεmεntal sεquεnce of phase offsets, and detεrmining thε pass/fail offset at each phase offset, a complete trace of the incoming signal may bε generatεd. Also, thε granularity and start stop points of thε phasε offsεts and/or threshold voltage steps may be controlled (e.g., by configuring a programmable circuit or register) to enable the waveform trace to bε constrained to selεcted points of interest in the incoming signal (e.g., +N° from an intεndεd sampling instant, N rεprεsεnting a swεεp anglε). Figure 32 illustrates thε usε of εmbedded scoping to generate a time- based trace 490 of an incoming data signal 486. The range of threshold voltage offsets over which the incoming signal 486 is sampled is indicated by VT, and the range of phase offsets at which thε signal is samplεd is indicated by D . Each sample point within the sweεp is indicated by a respective dot within a grid of sample points 480. Note that the sweep may be obtained by stepping the voltage threshold through the rangε of Vτ values for each valuε of
D, or, altεrnativεly, by stεpping thε clock phase through the range of D values for each value of VT. Still refεrring to Figure 32, 488 indicates a pair of samples for which a pass/fail condition is detected. A corresponding pass/fail offset (PFO) is determined according to the difference between the calibrated VT level
(Vτ(CAL)) and the average of the VT offsets between the pass and fail samples, and recorded as a measure of the incoming signal. That is, the pass/fail offset may be usεd to εstablish a data point within the trace 490 as shown. Aftεr swεεping through all thε samplε points within the grid 480 (which sweεp may be repeated numerous times to obtain an average and to discard statistical outliers), a measure of the incoming signal is obtained as illustrated graphically by the trace 490. Embedded scoping has a number of benefits over traditional signal measuremεnt techniques. First, because the technique is non-invasive (i.e., no probe contact), the elεctrical characteristics of the system under test are unaltered, thereby yiεlding potentially more accurate results. Also, the trace is genεratεd from thε pεrspεctivε of thε receive circuit itself, meaning that any non-ideal characteristics of the recεivε circuit are accounted for in thε resulting signal trace information. Finally, because all components needed for embeddεd scoping may bε included within a finished signaling system, embedded scoping may be used to pεrform numerous run-time analyses, including detεrmining thε latεncy and amplitude of refactions and othεr distortions within thε signaling systεm.
Figure 33 illustrates a signaling system 500 according to an embodimεnt of the invention. The signaling system 500 includes a receive devicε 501 and transmit dεvice 509 that employ embeddεd scoping to determine equalizεr tap sεlections, tap weights and tap polarities. Thε transmit device 501 includes a pattern generator 503, data selector 505, equalizing transmitter 507 and application logic 502. The application logic 502 performs the core function of thε transmitting dεvice (ε.g., signal processing, instruction processing, routing control, or any other function) and provides transmit data (TX DATA) to a first input of the data selector 505. During normal operation, the application logic 502 outputs a logic low scope signal 506 (SCOPE) to the data selεctor 505 to sεlect the transmit data to be passed to the equalizing transmitter 507 for transmission to the recεivε device 509 via signal path 122
(which may be include or be connected to numerous sources of discontinuity such as connectors, vias, stubs, etc.). During a scoping modε of opεration, thε application logic 502 drives the scope signal 506 high to enable a scoping mode of opεration within thε transmit circuit 501. In thε scoping mode, the data selεctor 505 selects a repεating singlε-symbol pulse sequence (e.g., a test signal such as: 00100...00100...00100...) generated by the pattern generator 503 to be transmitted to thε rεcεivε device 509. The receive device 509 includes an equalizing receivεr 510 to recεivε thε incoming data signal, a pattern register 511 to store a local version of thε singlε-symbol pulse sequence, a multiplexεr 512 to εnablε thε pattern register 511 to be switched betwεεn load and barrεl-shifting modεs, a XOR gate 513 to compare the recεivεd data sεquence with thε locally gεnεratεd sεquεncε, and application logic 515 (or other logic) to genεratε a clock adjust signal (CLK ADJ) and threshold voltage adjust signal (THRESH ADJ) to sweεp thε receive clock and threshold voltage usεd within the equalizing receiver through their scoping ranges. The application logic 515 additionally builds a trace record (i.ε., data indicative of the incoming data sequεncε) based on the output of XOR gate 513.
When the receive device 509 is in a scoping mode of operation, the multiplexer 512 is initially set to load the pattern register 511 with the output of the equalizing receiver 510. After a desired sequεnce of data (e.g., the singlε-symbol pulsε sequence) is shifted into the pattern register 511, the multiplexer 512 is set to enable the barrel-shifting mode of the pattern registεr
513. That is, the multiplexεr 512 sεlεcts thε output of the pattern registεr 511 to bε fεd back to thε input of thε pattern registεr 511 so that the contents of the pattern rεgistεr 511 arε continuously rotated through thε pattern register 511
(i.e., a barrel shifting operation). By this arrangemεnt, the data sequεncε loaded into thε pattern rεgistεr 511 is rεpεatedly output, bit by bit, to a first input of the XOR gate 513. The data sequεncε rεcεivεd by the equalizing receiver is input to a second input of the XOR gate 513 so that the received data sequεncε is compared, bit by bit, with thε data sequence stored within the pattern registεr 511. By sεlεcting thε lεngth of thε repεatεdly transmitted data sequεncε to match thε storagε size of the pattern registεr 511, thε pattern registεr contents are repeatedly compared with a newly received version of the same data sequence (i.e., putatively thε samε data sεquεncε). Any reception error will result in a mismatch betwεεn thε receivεd value and the corresponding value within thε pattern register and therefore, when compared by XOR gate 513, will result in an error signal being output from the XOR gatε 513 to the application logic 515. The application logic 515 may then record the adjusted threshold voltage and clock phase offset at which the error occurred to a signal lεvεl for a timing offsεt within a wavεform tracε.
Figure 34 illustrates an exεmplary waveform trace 527 of a pulse data sequence captured by an embεddεd scope within the signaling system of Figure 33. As shown, a primary pulse 529 arrives at the receiver at symbol time, T0; a negative reflεction 531 of thε primary pulsε appεars at symbol timε T5 and a positive reflεction 533 appears at symbol time T12. Thus, referring to Figure 33, the application logic 515 of rεcεivεr 509 may store configuration information in a sεlεct logic circuit within the equalizing receiver 510 (or elsewhεrε within thε receive device 509) to enable selεction of stored data values having symbol latencies of five and twelve symbol times as tap data sourcεs for an equalizing circuit. Alternatively, the application logic 515 may directly output select signals to selεct thε dεsired stored data values as tap data sources. The application logic 515 may also generate tap weights and tap polarity values in accordance with the amplitude and polarity of the distortions 531 and 533, and store or output the weights and polarity values as necessary to apply the appropriate tap weights and polarities within thε εqualizing recεivεr 510.
Figure 35 illustrates a method of setting equalization coefficients in a signaling system according to the invention, hi the embodiment shown, transmit-side equalization coefficients are sεt first (541), thεn rεcεive-side εqualization coefficients are set (551). The transmit-side coefficients are set by transmitting a test signal at 543 (e.g., a pulse signal, stεp, εtc), then genεrating a waveform tracε (545) using thε εmbεdded scoping techniques described above. The transmit-side equalization coefficients, including tap data sources, tap wεights and tap polaritiεs, are then set at 547 to produce a recεivεd waveform trace that most closely corresponds to the ideal waveform (ε.g., pulsε, stεp, etc.) output by the transmitter. The transmit-side equalization coefficients may be dεtεrminεd analytically (i.ε., by computing thε coefficients based on thε wavεform tracε generated at 545) or iteratively, by repεating opεrations 543 and 545 for diffεrent combinations of coefficient settings until a coefficiεnt setting that provides a desired waveform is detεrminεd.
Aftεr thε transmit-side equalization coefficients have been set, the receive-sidε coefficients are set by transmitting the test signal at 553 (i.e., a pulse, step or other signal transmitted with equalization according to the coefficients set at 547), then generating a waveform trace of the received waveform (555) using the embedded scoping techniques described above. The recεivε-side εqualization coefficients, including tap data sources, tap weights and tap polarities, are thεn sεt at 557 to produce a received waveform that most closely corresponds to the ideal waveform (i.e., waveform having reducεd high-latεncy distortion). Thε recεivε-sidε εqualization coefficients may be detεrminεd analytically as described in reference to Figures 31-33, or iterativεly, by repeating operations 553 and 555 for different combinations of coefficient settings until a coefficient setting that provides a desired waveform is detεrminεd.
Notε that selection of tap data sources within the transmitter may include outputting test signals on neighboring signal paths simultanεously with thε tεst signal transmission at 543 to allow determination of which transmit-side equalizer taps, if any, should be sourced by cross-talk cancellation data values (i.e., data values being transmitted on neighboring signal paths) and the corresponding tap weights.
Reducing Equalization Taps Through Path Length Symmetry As discussed above in reference to Figure 3, the tap select logic 139 and select circuit 128 enable equalization ovεr a rεlativεly widε rangε of symbol latεncies using a small numbεr of εqualizεr taps. In εmbodiments of the invention, the total number of equalizer taps is further reduced through symmetry in the electrical distances betweεn signal path discontinuities. Figurε 36 illustratεs a signaling system that employs path length symmetry to reduce the total number of equalization taps needεd to compεnsatε for reflεction-typε ISI. Thε systεm includes a pair of circuit boards 571 and 573 (e.g., line cards, port cards, memory modules, etc.) having integrated circuit (IC) devices 575 and 577 mounted respεctively thereon. IC device 575 includes a transmit circuit coupled to a connector interface 581 (e.g., a connector or a terminal to be received by a connector) via signal path sεgmεnt 582, and IC device 577 includes a receive circuit coupled to a connector interface 585 via signal path segment 586. The connector interfaces 581 and 585 are couplεd to onε anothεr through signal path segment 592 (e.g., backplanε trace, cable, etc.) to form an overall signal path between the transmit circuit and receivε circuit.
Because the connector interfaces 581 and 585 tend to have at least slightly different impedances than the impedance of path segments 582, 586 and 592, reflεctions arε produced at comiector interfaces as shown by reflεction flight paths AT, AR, CT and CR. Morε spεcifically, the reflection flight path indicated by A results from the primary signal reflecting off connector interface 581, and the reflection reflecting off the output node of the transmit circuit within IC 575. Thus, the reflection flight time over path AT excεεds thε unrεflεctεd primary signal flight time by twice the signal propagation time between the connector intεrfacε 581 and the transmit circuit output node; i.e., the signal propagation time on path segment 582. Similarly, the reflection flight time over path AR (reflection off recεiver input, then off connector intεrfacε 585) εxceeds the unreflεctεd primary signal flight timε by twice the signal propagation time between the connector interface 585 and the receive circuit input; the signal propagation time on path segment 586. Accordingly, if path sεgmεnts 582 and 586 arε designed or calibrated to have equal electrical lengths (i.e., equal signal propagation delays), reflections AT and AR will arrive at the input of the receive circuit of IC device 577 at substantially the same time. Consequently, a single equalization tap having a symbol latency that corresponds to the latent arrival of the coincident AT/AR reflections may be used to cancel or at least reduce both reflections. Because reflεction flight paths CT and CR arε madε equal by equalizing the electrical lengths of path segments 582 and 586, a single εqualization tap that corresponds to the latent arrival of coincident CT/CR reflections may be used to cancel or at least reduce both reflections. Thus, by designing or calibrating path segmεnts 582 and 586 to havε equal electrical lengths (which path segmεnts may optionally include an on-chip path segment betweεn thε transmit circuit output and an IC device 575 output node and/or an on-chip path segmεnt bεtwεεn thε receivε circuit input and an IC device 577 input node), one equalization tap within eithεr the transmit circuit or recεivε circuit may bε usεd to cancel or reduce a distortion that would otherwisε require two or more taps. In one embodimεnt, thε εlεctrical lengths of path segments 582 and
586 are made equal (or substantially equal — as achiεvablε through practicable manufacturing techniques) by design which may include, but is not limited to:
1) making the physical lengths of path sεgments 582 and 586 substantially equal, whethεr implemented by printed traces, cables or other types of conductors; 2) including inductive or capacitive structures (e.g., vias, fεrrite materials, narrowed or widened trace regions, or any other impedance-altering structures) statically coupled in seriεs or parallεl with path sεgmεnts 582 and/or 586 to εqualize otherwisε different electrical lengths of the path segmεnts; and/or 3) including inductive and/or capacitive structures that may be run-time coupled (e.g., through pass gates or other electrically or magnetically controllable structures) in series or parallel with path sεgmεnts 582 and/or 586 to εqualizε otherwise different electrical lengths of the path segmεnts. Morε gεnerally, any technique for adjusting the electrical lengths of path segments 582 and 586 to achieve coincident arrival of two or more signal reflεctions at thε input of an εqualizing receivεr may bε usεd without dεparting from thε spirit and scope of the present invention.
Regarding run-time coupling of impedancε-altεring structures to path segmεnts 582 and/or 586, such impedance-altering structures may be selectively coupled to path segmεnts 582 and/or 586 through operation of a configuration circuit (e.g., volatile or non-volatile storage, or fusible or otherwisε one-time programmable circuit). For example a configuration value that corresponds to the dεsired electrical length of a path segment may be programmed into the configuration circuit and used to control pass gates or other switching elements for switchably coupling the impedance-altering structures to the path segmεnt. Thε dεsirεd setting of the configuration value may be determined, for examplε, by using thε εmbεddεd scoping technique described above in refεrencε to Figures 27-29 to determine relative arrival times of signal reflεctions and thereforε propagation timε diffεrences betwεεn signal rεflεctions.
Although the invention has been described with reference to specific exεmplary εmbodimεnts thεrεof, it will bε εvidεnt that various modifications and changes may be made therεto without dεparting from thε broadεr spirit and scope of the invεntion as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

CLALMSWhat is claimed is:
1. An apparatus comprising: a buffer to store a plurality of data valuεs that correspond to data signals transmitted on a signaling path during a first time interval; a select circuit coupled to thε buffεr to select a subset of data values from thε plurality of data valuεs according to a sεlεct value; and an equalizing circuit coupled to receivε thε subset of data values from the sεlεct circuit and adapted to adjust, according to the subsεt of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a sεcond time interval.
2. The apparatus of claim 1 further comprising a receivεr circuit to receive the data signals transmitted on the signaling path during thε first and second time intεrvals, thε rεcεivεr circuit bεing couplεd to output thε plurality of data valuεs to thε buffεr.
3. Thε apparatus of claim 2 whεr in thε εqualizing circuit includes an output driver to output an equalizing signal onto the signaling path to adjust the signal levεl that corresponds to the data signal transmitted on the signaling path during thε sεcond timε intεrval, thε equalizing signal having an amplitude according to the subsεt of data valuεs.
4. The apparatus of claim 2 wherein the second time intεrval is distinct from and subsεquεnt to thε first time interval.
5. The apparatus of claim 2 wherein the receiver circuit includes a preamplifier circuit to generatε thε signal lεvel that corresponds to the data signal transmitted on the signaling path during the second time interval by amplifying the data signal transmitted on the signaling path during the second time interval.
6. The apparatus of claim 5 wherein the equalizing circuit is coupled to thε prε-amplifiεr circuit to adjust amplification of thε signal level within the prε-amplifiεr circuit in accordance with the subset of data values.
7. The apparatus of claim 2 wherein the recεivεr circuit includes a sampling circuit to genεratε thε signal level that corresponds to the data signal transmitted on thε signaling path during thε sεcond timε intεrval by sampling thε data signal transmittεd on the signaling path during the second time interval.
8. The apparatus of claim 7 wherein the equalizing circuit is coupled to the sampling circuit to adjust the signal level genεratεd by the sampling circuit in accordance with the subsεt of data values.
9. The apparatus of claim 2 wherein the receiver circuit is adapted to receivε additional data signals transmittεd on the signaling path during a third time interval, the third time interval being distinct from and occurring bεtwεεn thε first and sεcond time intervals.
10. The apparatus of claim 9 wherein the buffer is adapted to store, in addition to the plurality of data values transmittεd on thε signaling path during thε first timε interval, data values that correspond to at least a portion of the data signals transmitted during the third time interval.
11. Thε apparatus of claim 9 whεrεin thε third time interval corresponds to a time required to receive a predεtεrminεd numbεr of signals in succession.
12. The apparatus of claim 11 wherein thε predetermined number of signals corresponds to a predeterminεd number of data values for which signal levels are adjustεd by a transmit circuit.
13. Thε apparatus of claim 2 further comprising a first transmitter circuit to output transmit data signals on the signaling path during a third timε interval.
14. The apparatus of claim 13 wherein the first transmitter circuit and the receiver circuit are adapted to be coupled to a first end of thε signaling path.
15. Thε apparatus of claim 13 wherein the first transmitter circuit and the receivεr circuit form a transcεivεr circuit couplεd to thε signaling path.
16. Thε apparatus of claim 13 wherein data values that correspond to the transmit data signals are also stored in the buffer circuit.
17. The apparatus of claim 16 wherein the buffer circuit comprises a receive buffer and a transmit buffer, the recεivε buffεr bεing couplεd to rεcεivε thε plurality of data valuεs output by thε receiver circuit and the transmit buffer being coupled to recεivε the data values that correspond to the transmit data signals.
18. The apparatus of claim 17 wherein the select circuit is coupled to the receive buffer and the transmit buffer to select the subset of data values therefrom.
19. The apparatus of claim 13 wherein the first transmit circuit comprises a transmit equalizing circuit to output equalizing signals onto the signal path simultaneously with thε transmit data signals.
20. Thε apparatus of claim 19 further comprising a second transmit circuit to output transmit data signals on another signaling path during thε third timε interval.
21. The apparatus of claim 20 wherein the transmit equalizing circuit comprises: a transmit buffer to store a data value that corresponds to a transmit data signal output onto the signaling path by the transmitter circuit; a multiplexεr having a first input couplεd to receive the data value from the transmit buffer, and a second input coupled to an input of the second transmit circuit; and an output driver having an input coupled to an output of the multiplexεr, and an output to output the εqualizing signals onto the signal path.
22. The apparatus of claim 21 further comprising a configuration circuit having an output couplεd to a control input of the multiplexer to select either the data value stored in the transmit buffer or a data value supplied to the input of the second transmit circuit to be provided to the output driver comprised by the transmit equalizing circuit.
23. Thε apparatus of claim 1 further comprising a first transmit circuit to transmit the data signals transmitted on the signaling path during the first time interval and the data signal transmitted on the signaling path during the second time intεrval.
24. Thε apparatus of claim 23 whεrεin the first transmit circuit comprises a transmit equalizing circuit to output equalizing signals onto the signal path simultaneously with the data signals transmitted on the signaling path by the first transmit circuit.
25. The apparatus of claim 24 further comprising a second transmit circuit to transmit data signals on another signaling path.
26. The apparatus of claim 25 wherein the transmit εqualizing circuit comprises: a transmit buffer to store a data value that corresponds to one of the data signals transmitted on the signaling path by the first transmit circuit; a multiplexer having a first input coupled to rεcεivε thε data valuε from thε transmit buffεr, and a sεcond input coupled to an input of the second transmit circuit; and an output driver having an input coupled to an output of the multiplexer, and an output to output the equalizing signals onto the signal path.
27. The apparatus of claim 26 further comprising a configuration circuit having an output coupled to a control input of the multiplεxer to selεct εithεr thε data valuε storεd in thε transmit buffer or a data value supplied to the input of the second transmit circuit to be providεd to thε output drivεr comprised by the transmit equalizing circuit.
28. The apparatus of claim 23 wherein the equalizing circuit includes an output driver coupled in parallel with the first transmit circuit, the equalizing circuit being adaptεd to transmit an εqualizing signal onto thε signaling path during thε second time interval to adjust the signal levεl of thε data signal transmittεd on thε signaling path during thε second time intεrval, the equalizing signal having an amplitude according to thε subsεt of data values.
29. Thε apparatus of claim 1 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal level that falls within one of at least threε possiblε rangεs of signal lεvεls.
30. Thε apparatus of claim 1 wherein each of the data signals transmitted on the signaling path during the first time interval is represεntativε of at least two binary bits of information.
31. The apparatus of claim 1 further comprising a configuration circuit to store the selεct valuε and to output thε sεlect valuε to thε select circuit, thε sεlect value being output to the select signal as a plurality of signals.
32. The apparatus of claim 31 wherein the configuration circuit is adapted to systematically step thε select value through a sequεncε of tεst valuεs to dεtermine a setting of the selεct value that corresponds to the subset of data values.
33. The apparatus of claim 32 wherein the configuration circuit is adapted to determinε, for each test value in the sequεncε of tεst valuεs, a measure of correctly received data values.
34. Thε apparatus of claim 33 wherein the configuration circuit is further adapted to sεt thε select value according to thε test value for which the measure of correctly received data values is highest.
35. The apparatus of claim 31 wherein the configuration circuit is adapted to adjust thε select value according to thε plurality of data values.
36. The apparatus of claim 31 wherein the equalizing circuit is adapted to adjust the signal level in accordance with the subset of data values and a plurality of weight values that correspond respεctively to the subset of data valuεs.
37. Thε apparatus of claim 36 wherein the configuration circuit is adaptεd to output thε weight values to the equalizing circuit.
38. The apparatus of claim 37 wherein the configuration circuit is adapted to step at least one of thε wεight valuεs through a sεquεnce of test weight values in a calibration opεration.
39. The apparatus of claim 1 wherein the εqualizing circuit is adaptεd to adjust thε signal lεvεl in accordance with the subset of data valuεs and a plurality of wεight valuεs that correspond respectively to the subset of data values.
40. Thε apparatus of claim 39 further comprising a configuration circuit coupled to output thε plurality of wεight valuεs to the equalizing circuit.
41. The apparatus of claim 40 wherein the configuration circuit is adapted to step at least onε of thε plurality of weight values through a sεquεncε of tεst wεight valuεs in a calibration opεration.
42. Thε apparatus of claim 41 wherein the configuration circuit is adapted to determine, for each test weight value in the sεquεncε of test weight values, a measure of correctly recεivεd data valuεs.
43. The apparatus of claim 42 wherein the configuration circuit is further adaptεd to sεt the at lεast one of the plurality of weight values according to the test weight value for which the measure of correctly received data values is highest.
44. The apparatus of claim 40 wherein the configuration circuit is adapted to adjust at least onε of thε plurality of wεight values according to the plurality of data values.
45. The apparatus of claim 1 wherein the equalizing circuit is adapted to adjust thε signal lεvεl in accordance with thε subset of data values and a plurality of polarity values that correspond respεctively to the subset of data values, each polarity value indicating whεthεr a corresponding data value within the subset of data values shall make a positive or negative contribution to the signal level.
46. A receiver circuit to receive data signals transmitted on a signaling path, the receivεr circuit comprising: a buffer to store a plurality of data valuεs that correspond to data signals transmitted on the signaling path during a first time interval; and an equalizing circuit coupled to recεivε a subsεt of thε plurality of data valuεs from thε buffεr circuit and adaptεd to adjust, according to thε subsεt of the plurality of data values, a signal levεl that corresponds to a data signal transmitted on the signaling path during a second time intεrval, thε sεcond timε interval being offset from the first timε interval by a third time interval.
47. The receivεr circuit of claim 46 whεrεin thε third time interval corresponds to a length of time during which a data value that corresponds to a data signal transmitted on the signaling path by a transmit circuit is used within the transmit circuit to genεratε an εqualization signal.
48. Thε rεcεiver circuit of claim 46 wherein the third timε intεrval is dεtεrmined according to a programmable configuration value.
49. The rεcεivεr circuit of claim 46 comprising a configuration circuit store a timing valuε indicative of thε third timε intεrval.
50. Thε rεcεivεr circuit of claim 49 whεrεin the configuration circuit is adapted to systematically step thε timing valuε through a sequence of test values to determine a setting of the timing value.
51. Thε rεcεiver circuit of claim 50 whεrεin thε configuration circuit is adapted to detεrmine, for each test value in the sequence of test values, a measure of correctly receivεd data valuεs.
52. The recεivεr circuit of claim 51 whεrεin thε configuration circuit is further adapted to set the timing value according to thε test value for which the measure of correctly received data values is highest.
53. The recεiver circuit of claim 46 further comprising a select circuit coupled to the buffer and the equalizing circuit, thε sεlεct circuit being adapted to select the subset of the plurality of data values according to a select value and to output the subset of the plurality of data values to the equalizing circuit.
54. The recεiver circuit of claim 53 wherein the plurality of data values includes M data valuεs and the subsεt of the plurality of data valuεs selected by the selεct circuit includes N data values, M being greater than N.
55. The recεivεr circuit of claim 53 further comprising a configuration circuit to store the selεct value and to output the select value to thε sεlect circuit, thε sεlεct value being output to the selεct signal as a plurality of signals.
56. Thε rεcεivεr circuit of claim 55 whεrεin thε configuration circuit is adaptεd to systematically stεp the select value through a sequence of test values to detεrminε a setting of the sεlεct value that corresponds to the subset of the plurality of data values.
57. Thε recεivεr circuit of claim 56 wherein the configuration circuit is adapted to detεrmine, for each test value in the sequence of test values, a measure of correctly received data values.
58. The receivεr circuit of claim 57 wherein the configuration circuit is further adapted to set the selεct valuε according to thε test value for which the measure of correctly received data values is highest.
59. Thε recεivεr circuit of claim 46 whεrεin thε equalizing circuit is adapted to adjust the signal level in accordance with thε subset of the plurality of data values and a plurality of wεight valuεs that correspond respectively to the subset of the plurality of data values.
60. The receiver circuit of claim 59 wherein a configuration circuit is coupled to output thε plurality of wεight values to the εqualizing circuit.
61. Thε rεcεivεr circuit of claim 60 wherein the configuration circuit is adapted to step at least one of the plurality of weight values through a sequence of test weight values in a calibration operation.
62. Thε rεcεivεr circuit of claim 61 whεrεin thε configuration circuit is adapted to determine, for each tεst wεight valuε in thε sεquεncε of tεst wεight valuεs, a measure of correctly recεivεd data valuεs.
63. Thε receiver circuit of claim 62 wherein the configuration circuit is further adapted to set the at least one of thε plurality of wεight valuεs according to the test weight valuε for which the measure of correctly received data values is highest.
64. The recεivεr circuit of claim 46 whεrεin thε εqualizing circuit includes an output driver to output an equalizing signal onto thε signaling path during the second time interval to adjust the signal levεl that corresponds to the data signal transmittεd on thε signaling path during the second time interval, the equalizing signal having an amplitude according to the subset of thε plurality of data valuεs.
65. The receiver circuit of claim 46 further comprising a preamplifier circuit to amplify the data signal transmitted on the signaling path during the second time interval and thereby to generate the signal level that corresponds to the data signal.
66. Thε rεcεivεr circuit of claim 65 wherein the equalizing circuit is coupled to the pre-amplifiεr circuit to adjust amplification of the signal level within the pre-amplifiεr circuit in accordance with the subset of the plurality of data values.
67. Thε rεcεivεr circuit of claim 46 further comprising a sampling circuit to generatε thε signal lεvεl that corresponds to the data signal transmitted on the signaling path during thε sεcond time interval by sampling the data signal transmitted on the signaling path during the second time intεrval.
68. Thε rεcεivεr circuit of claim 46 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal levεl that falls within one of at least three possible ranges of signal levels.
69. The receiver circuit of claim 46 wherein each of the data signals transmitted on the signaling path during the first time interval is representative of at least two binary bits of information.
70. The receiver circuit of claim 46 wherein thε εqualizing circuit is adaptεd to adjust the signal levεl in accordance with the subset of the plurality of data values and a corresponding plurality of polarity values, each polarity value indicating whether a corresponding data value within the subset of the plurality of data values shall make a positive or negative contribution to the signal levεl.
71. A signaling systεm comprising: a signaling path; a transmit circuit couplεd to thε signaling path to transmit a first data signal thεrεon during a first transmit intεrval, thε transmit circuit including a transmit equalization circuit couplεd to thε signal path to transmit a first εqualization signal thεreon during the first transmit interval, the first equalization signal having a signal level according to data signals transmitted on the signaling path by the transmit circuit during a first time interval that precedes the first transmit interval; and a receivε circuit coupled to the signaling path to receive the first data signal during a first receivε interval, the receivε circuit including a rεcεivε εqualization circuit coupled to the signal path to transmit a second equalization signal thereon during the first recεivε intεrval, thε second equalization signal having a signal level according to data signals received via the signaling path during a second time interval that precεdεs thε first rεcεivε interval by an amount of time according to the first time interval.
72. The system of claim 71 wherein the receive equalization circuit comprises: a buffer to store a plurality of data values that correspond to the data signals recεivεd via the signaling path during the sεcond time interval; a sεlεct circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a sεlect value; and an output drivεr to output thε sεcond εqualization signal onto the signaling path, the second equalization signal having an amplitude according to the subset of data values.
73. The system of claim 72 further comprising a configuration circuit to store the select value and to output the select value to the select circuit.
74. The system of claim 73 whεrein thε configuration circuit is adaptεd to systεmatically step the selεct valuε through a sεquence of test values to dεtermine a sεtting of thε sεlεct valuε that corresponds to the subset of data values.
75. The system of claim 74 wherein the configuration circuit is adapted to detεrminε, for εach test value in the sequεncε of test values, a measure of correctly received data values.
76. The system of claim 75 whεrεin the configuration circuit is further adapted to set the selεct valuε according to thε test value for which the measure of correctly received data values is highest.
77. The system of claim 73 wherein the configuration circuit is adapted to adjust the. select value according to the plurality of data signals received during the second time intεrval.
78. Thε system of claim 71 wherein the transmit equalization circuit comprises: a buffεr to store a plurality of data values that correspond to thε data signals transmittεd on the signaling path during the first time interval; a selεct circuit couplεd to thε buffεr to sεlεct a subsεt of data valuεs from the plurality of data values according to a select value; and an output drivεr to output thε first εqualization signal onto thε signaling path, the first equalization signal having an amplitude according to thε subset of data values.
79. The system of claim 78 further comprising a configuration circuit to store the select value and to output the select value to the selεct circuit.
80. Thε systεm of claim 79 wherein the configuration circuit is adapted to systematically step the selεct valuε through a sεquεncε of tεst values to determine a setting of thε sεlεct valuε that corresponds to the subsεt of data values.
81. The systεm of claim 80 whεrεin thε configuration circuit is adaptεd to dεtεrminε, for εach tεst valuε in thε sequence of test values, a measure of correctly recεived data values.
82. The system of claim 81 wherεin the configuration circuit is further adapted to set the select value according to the tεst valuε for which the measure of correctly received data values is highest.
83. The system of claim 79 wherein the configuration circuit is adapted to adjust thε select value according to the plurality of data signals transmittεd during thε first timε intεrval.
84. Thε system of claim 71 wherεin thε first data signal has a signal lεvel that falls within one of at least three possible ranges of signal levels.
85. Thε systεm of claim 71 whεrεin the first data signal is reprεsεntative of at least two binary bits of information.
86. The systεm of claim 71 wherein the recεivε εqualization circuit is adapted to adjust the signal level in accordance with the data signals received during the second time interval and a plurality of weight valuεs that correspond respectively to the data signals recεivεd during thε sεcond time interval.
87. The systεm of claim 86 whεrεin the recεivε circuit further includes a configuration circuit coupled to the rεcεivε equalization circuit to output the plurality of weight values thereto.
88. The systεm of claim 87 whεrεin thε configuration circuit is adaptεd to stεp at lεast onε of thε plurality of weight values through a sequεncε of test weight valuεs in a calibration opεration.
89. The system of claim 88 wherein the configuration circuit is adapted to determine, for each test weight value in the sequence of test weight values, a mεasurε of correctly receivεd data valuεs.
90. The system of claim 89 wherεin thε configuration circuit is further adapted to set the at least one of thε plurality of wεight valuεs according to thε test weight value for which the measure of correctly recεivεd data valuεs is highεst.
91. Thε systεm of claim 87 wherein thε configuration circuit is adaptεd to adjust at lεast one of the plurality of weight valuεs according to the plurality of data signals received during the sεcond timε intεrval.
92. The system of claim 71 wherein the transmit equalization circuit is adapted to adjust the signal levεl in accordance with the data signals transmitted during the first time intεrval and a plurality of wεight values that correspond rεspεctively to the data signals transmittεd during the first time interval.
93. Thε system of claim 92 wherein the transmit circuit further includes a configuration circuit coupled to the transmit εqualization circuit to output thε plurality of weight values thεrεto.
94. Thε system of claim 93 wherein the configuration circuit is adapted to step at least one of thε plurality of wεight values through a sequεncε of tεst weight valuεs in a calibration opεration.
95. The system of claim 94 wherein the configuration circuit is adapted to detεrminε, for each test weight value in the sequεncε of tεst wεight values, a measure of correctly recεivεd data values.
96. Thε system of claim 95 wherein the configuration circuit is further adapted to set thε at lεast onε of the plurality of weight valuεs according to the test weight value for which the measure of correctly received data values is highest.
97. Thε system of claim 71 wherein the receivε εqualization circuit is adaptεd to adjust the signal level of the second equalization signal in accordance with the data signals rεcεivεd during thε sεcond time interval and a plurality of polarity valuεs that correspond respectively to the data signals recεivεd during the second time interval, each polarity value indicating whεthεr a corresponding one of data signals received during the second time intεrval shall makε a positivε or nεgativε contribution to thε signal lεvel of the second equalization signal.
98. A method of operation within an integrated circuit device, the method comprising: storing a plurality of data values, the plurality of data values corresponding to data signals transmitted on a signaling path during a first time interval; selecting a subset of data values from the plurality of data values; and adjusting a signal level according to the subset of data values, the signal level corresponding to a data signal transmittεd on the signaling path during a second time interval.
99. The method of claim 98 wherεin adjusting a signal lεvel according to the subset of data values comprises outputting an equalizing signal onto the signaling path to adjust the signal lεvεl, the equalizing signal having an amplitude according to the subset of data values.
100. The method of claim 98 wherein adjusting the signal level comprises adjusting amplification of the signal lεvεl according to thε subsεt of data valuεs.
101. Thε mεthod of claim 100 whεrεin adjusting amplification of the signal level comprises adjusting amplification of the signal lεvεl within a preamplifier circuit.
102. The method of claim 100 wherein adjusting amplification of the signal levεl comprises adjusting amplification of the signal levεl within a sampling circuit.
103. The method of claim 98 further comprising transmitting thε data signals transmittεd on thε signaling path during the first time interval.
104. The method of claim 98 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal level that falls within one of at least three possible ranges of signal levεls.
105. The method of claim 98 whεrεin each of the data signals transmittεd on thε signaling path during thε first timε intεrval is representative of at least two binary bits of information.
106. The method of claim 98 further comprising storing the select value in a configuration circuit.
107. The method of claim 98 further comprising systematically stepping the select value through a sequence of test values to detεrmine a setting of the sεlect value that corresponds to the subset of data values.
108. The method of claim 107 wherein systematically stepping the select value through a sequence of test valuεs to determine a setting of the selεct valuε that corresponds to the subset of data values comprises: detεrmining, for each test valuε in thε sequence of test values, a measure of correctly received data values; and sεtting the selεct valuε according to the test value for which thε measure of correctly received data values is highest.
109. A method of operating a receiver circuit, the method comprising: storing a plurality of data values that correspond to data signals transmitted on a signaling path during a first time intεrval; and adjusting, according to thε subsεt of the plurality of data values, a signal level that corresponds to a data signal transmitted on thε signaling path during a sεcond timε intεrval, thε sεcond time interval being offset from the first time interval by a third time interval.
110. The mεthod of claim 109 wherein the third time interval corresponds to a length of time during which a data valuε that corresponds to a data signal transmitted on the signaling path by a transmit circuit is used within the transmit circuit to generate an equalization signal.
111. The mεthod of claim 109 further comprising storing, in a configuration circuit, a timing value indicative of the third time interval.
112. The method of claim 109 further comprising selεcting thε subset of the plurality of data valuεs according to a sεlεct value.
113. The method of claim 112 further comprising storing thε sεlect value in a configuration circuit.
114. The mεthod of claim 112 further comprising systematically stepping the selεct valuε through a sequence of test values to determine a setting of the selεct value that corresponds to the plurality of data values.
115. The method of claim 109 wherεin adjusting thε signal level that corresponds to thε data signal transmitted on the signaling path during the second time interval comprises outputting an equalizing signal onto the signaling path during the second time interval to adjust the signal level, the εqualizing signal having an amplitudε according to the subset of the plurality of data values.
116. The method of claim 109 wherein adjusting the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval comprises adjusting amplification of the signal lεvεl within a pre-amplifier circuit in accordance with the subset of the plurality of data values.
117. The method of claim 109 wherεin adjusting thε signal lεvεl that corresponds to the data signal transmitted on the signaling path during the second time interval comprises adjusting amplification of the signal level within a sampling circuit in accordance with the subset of the plurality of data values.
118. The method of claim 109 wherein each of the data signals fransmitted on thε signaling path during thε first timε interval has a signal level that falls within one of at least threε possible rangεs of signal lεvels.
119. The method of claim 109 wherein each of the data signals fransmitted on the signaling path during the first time interval is representative of at least two binary bits of information.
120. A method of operating a signaling system, the method comprising: transmitting a first data signal on a signaling path during a first transmit interval; transmitting a first equalization signal on the signal path during the first transmit interval, thε first εqualization signal having a signal level according to data signals transmitted on thε signaling path during a first time interval that precedes the first transmit interval; receiving the first data signal from the signaling path during a first receive interval; and transmitting a second equalization signal on the signal path during the first receivε intεrval, thε sεcond εqualization signal having a signal lεvεl according to data signals rεcεivεd from thε signaling path during a second time interval that precedεs the first receive interval by an amount of time according to the first time interval.
121. The method of claim 120 whεrεin transmitting a sεcond εqualization signal on thε signal path during thε first timε interval comprises: storing a plurality of data values that correspond to the data signals received from the signaling path during the second time interval; sεlεcting a subsεt of data valuεs from thε plurality of data values according to a sεlεct valuε; and outputting the second εqualization signal onto thε signaling path, the second equalization signal having an amplitude according to the subsεt of data valuεs.
122. Thε mεthod of claim 121 furthεr comprising storing thε sεlect value in a configuration circuit.
123. Thε mεthod of claim 122 furthεr comprising systεmatically stepping the select value through a sequence of test values to determine a setting of the selεct valuε that corresponds to the subsεt of data values.
124. Thε method of claim 123 whεrεin systematically stepping the select value through a sequεnce of test values to determinε a sεtting of thε sεlect valuε that corresponds to the subset of data values comprises: determining, for each test value in the sequence of test values, a measure of correctly recεivεd data values; and setting thε sεlεct valuε according to thε test value for which the measure of correctly recεivεd data valuεs is highest.
125. The mεthod of claim 120 wherein transmitting a first equalization signal on the signal path during the first transmit interval comprises: storing a plurality of data values that correspond to the data signals transmitted on the signaling path during thε first timε intεrval; sεlεcting a subset of data values from the plurality of data valuεs according to a sεlεct value; and outputting the first equalization signal onto thε signaling path, thε first equalization signal having an amplitude according to the subset of data values.
126. The method of claim 120 wherein the first data signal has a signal levεl that falls within one of at least threε possiblε ranges of signal levels.
127. The method of claim 120 wherein the first data signal is represεntative of at least two binary bits of information.
128. An apparatus comprising: a scoping circuit to gεnεratε a wavεform trace of a test signal received via a signal path, the waveform trace indicating a time interval betwεen receipt of a transition of the test signal and receipt of a reflection of the transition; a buffer circuit to store a plurality of data values that correspond to data signals recεivεd via thε signal path; a select circuit coupled to the buffer circuit to select therefrom, according to the time interval indicated by the waveform trace, a first data value of the plurality of data values; and an equalizing circuit to genεratε an εqualizing signal basεd, at lεast in part, on thε first data valuε.
129. Thε apparatus of claim 1 wherein the scoping circuit comprises: a signal genεrator to gεnerate a local version of the test signal; and a comparator to compare the local version of the test signal with the test signal received via the signal path.
130. The apparatus of claim 2 wherein the scoping circuit further comprises a logic circuit to adjust a phase offset of a clock signal used to time reception of the test signal received via the signal path.
131. The apparatus of claim 2 wherein the test signal received via the signal path is a repεating test signal, and wherεin thε logic circuit is adaptεd to incrεmεntally adjust the phase offset of the clock signal after each N repetitions of the test signal, N being an intεger greatεr than zero.
132. The apparatus of claim 4 wherein the each of the incrementally adjusted phase offsεts of thε clock signal correspond to a sample point in the waveform frace.
133. Thε apparatus of claim 2 wherein thε scoping circuit further comprises a logic circuit to adjust a threshold voltage, the threshold voltage bεing usεd to dεtεrmine a data value represented by the test signal receivεd via thε signal path.
134. Thε apparatus of claim 6 wherein the test signal recεivεd via thε signal path is a rεpεating test signal, and wherein the logic circuit is adaptεd to incrementally adjust the threshold voltage after each N repetitions of the test signal, N being an integer greatεr than zεro.
135. Thε apparatus of claim 7 wherein logic circuit is adapted to record the threshold voltage at which thε comparator circuit indicates a mismatch betweεn thε tεst signal received via the signal path and the locally generated version of the tεst signal, thε threshold voltage at which the comparator circuit indicates the mismatch being indicative of the test signal voltage levεl at an instant in timε.
136. The apparatus of claim 8 wherein thε waveform trace is formed by a sequence of test signal voltage lεvεl dεtεrminations, εach test signal voltage level detεrmination corresponding to a thrεshold voltage at which the comparator circuit indicates a mismatch betweεn thε test signal received via the signal path and the locally genεratεd vεrsion of the test signal.
137. The apparatus of claim 1 wherein the scoping circuit comprises circuitry to generate a selεct valuε basεd on the time interval between receipt of the transition of the test signal and receipt of the reflεction of the transition.
138. The apparatus of claim 10 wherein the select circuit is coupled receive the sεlect valuε from the scoping circuit, the select circuit being adapted to selεct thε first data valuε according to thε sεlect value.
139. Thε apparatus of claim 1 furthεr comprising a configuration circuit coupled to the scoping circuit and to the selεct circuit, thε scoping circuit being adapted to generate a selεct valuε basεd on the time interval and to store the selεct valuε in thε configuration circuit, thε sεlεct circuit being adapted to sεlεct thε first data value based on the select value.
140. A method of operation within an integrated circuit device, the method comprising: genεrating a waveform frace of a test signal received via a signal path; selεcting, basεd on thε wavεform trace, a first data value of a plurality of data values that correspond to signals received via the signal path; and generating an equalizing signal based on thε first data valuε.
141. Thε method of claim 13 wherεin gεnerating a waveform frace of the test signal comprises : genεrating a local version of the test signal; and comparing the local version of thε test signal with the test signal receivεd via thε signal path.
142. Thε mεthod of claim 14 whεrεin gεnεrating the waveform frace of the test signal further comprises incrementally adjusting a phase of a clock signal used to time reception of the tεst signal to capture samples of the test signal at differεnt timing offsεts within a data valid window of thε test signal.
143. The method of claim 15 wherein the test signal is a repeating test signal, and wherεin incremεntally adjusting thε phasε of the clock signal comprises incremεntally adjusting thε phasε of the clock signal after εach N repetitions of the test signal, N being an integer greater than zero.
144. The method of claim 16 wherεin εach incrementally adjusted phase of the clock signal corresponds to a sample point in the waveform frace.
145. Thε mεthod of claim 14 whεrεin gεnεrating thε wavεform frace of the tεst signal furthεr comprisεs incrementally adjusting a threshold voltage used to detεrminε a data valuε represented by the test signal.
146. The method of claim 18 wherein the tεst signal is a repeating test signal, and wherein incrementally adjusting the threshold voltage comprises incrementally adjusting the threshold voltage after εach N rεpεtitions of thε tεst signal, N bεing an integer greater than zero.
147. The mεthod of claim 19 further comprising recording the threshold voltage at which a comparison of the local version of the test signal with the test signal received via the signal path yields a mismatch, the threshold voltage at which the comparison yields a mismatch being indicative of a voltagε level of the tεst signal at an instant in time.
148. A signaling system comprising: a transmit device including a transmitter, data selector and pattern genεrator, the data sεlector bεing adaptεd to sεlect the pattern generator to provide a sεquεnce of values to be transmitted by the transmitter during a scoping mode of operation of the transmit device; a signal path coupled to the transmitter of the transmit device; and a receive device including a receivεr, rεcεive-sidε pattern gεnerator, comparator, select circuit, buffer, and equalizer, the receiver being coupled to the signal path to receive the sequεncε of values transmitted by the transmitter, the comparator bεing couplεd to thε rεcεivεr and thε receivε-sidε pattern gεnεrator and adaptεd to compare the sequence of values received by the rεcεivεr with a locally gεnεrated sequεncε of valuεs generatεd by the receive- side pattern generator, the select circuit being adaptεd to sεlεct onε of a plurality of storagε εlements within thε buffer based on the comparison of the received sequence of values and the locally generated sequence of values, the equalizer being coupled to receivε a data value from the one of the plurality of storage elements selected by the select circuit and being adapted to generate an equalizing signal based, at least in part, on the data value.
149. The system of claim 21 wherein the receive device further comprises a logic circuit to incrementally adjust a phasε of a clock signal usεd to time reception of the sequence of data values to achieve a plurality of incrementally phase-offsεt samplεs of εach data value of the sequence of data values.
150. The system of claim 21 wherein the receive device further comprises a logic circuit incremεntally adjust a thrεshold voltagε usεd to resolve each data value of the received sequence of data values to one of a plurality of possible digital values.
151. A method of operation within a signaling systεm, thε mεthod comprising: receiving a test signal via a signal path; comparing the test signal to a separately generated version of the test signal to determine a time intεrval bεtwεεn rεcεption of a transition in thε test signal and reception of a reflection of the transition; sεlecting one of a plurality of storage elεmεnts according to thε timε intεrval; and generating an equalizing signal based on contents of the one of thε plurality of storagε εlements.
152. Thε mεthod of claim 24 further comprising transmitting the test signal on the signal path during a scoping mode of operation within a fransmit dεvicε of thε signaling system.
153. The mεthod of claim 25 wherein transmitting thε tεst signal on thε signal path comprisεs sεlεcting, within the transmit device, a pattern generator to provide a sequεncε of valuεs to be transmitted as the test signal.
154. The method of claim 26 wherein the sequence of values reprεsεnts a pulsε.
155. Thε mεthod of claim 26 wherein comparing thε test signal to a separately genεratεd vεrsion of the test signal to detεrmine a timε interval betwεεn reception of a fransition in the test signal and reception of a reflεction of thε transition comprisεs dεtermining a time interval between reception of the pulse and reception of a reflεction of thε pulse.
156. The method of claim 24 wherein comparing the tεst signal to a sεparatεly generatεd vεrsion of thε test signal to detεrmine a time interval between reception of a transition in the test signal and rεception of a rεflεction of the transition comprisεs: incremεntally adjusting a phasε offsεt of a clock signal usεd to capture samplεs of the test signal; and incremεntally adjusting a thrεshold voltagε usεd to rεsolvε εach of thε samplεs of the test signal to a digital value.
157. The method of claim 29 wherein comparing the test signal to a separately generatεd vεrsion of thε test signal to detεrminε a timε interval between reception of a transition in the test signal and reception of a reflection of the transition further comprises generating a waveform trace of thε test signal based on incremεntally adjusted threshold voltages at which samples of the test signal are resolvεd to digital values that do not match digital values within the locally generated version of the test signal.
158. Thε mεthod of claim 29 wherein comparing thε test signal to a separatεly gεnεratεd vεrsion of thε test signal to determine a time interval between reception of a transition in the test signal and reception of a reflεction of the fransition further comprises determining a time interval between a pulse within the waveform trace and a reflection of the pulse.
159. An integratεd circuit device comprising: a sampling circuit to capture samples of a data signal in response to a sampling clock signal; an output driver couplεd to an input of the sampling circuit and adapted to output an equalizing signal thεrεto in responsε to a first clock signal; and a clock signal generator to adjust a phase of the first clock signal to achieve phasε alignment bεtween transitions of the equalizing signal and transitions of thε data signal.
160. Thε intεgratεd circuit device of claim 1 wherein thε clock signal gεnεrator is adapted to generate the sampling clock signal and, when a control signal is in a first state, to adjust a phase of thε sampling clock signal to reduce to a phase difference between the sampling clock signal and transitions in the data signal.
161. Thε integrated circuit device of claim 2 wherein the clock signal generator is adapted to suspend adjustment of the phase of the sampling clock signal when thε control signal is in a sεcond state.
162. The integratεd circuit device of claim 3 wherein the clock signal genεrator is adaptεd to adjust thε phase of the first clock signal regardlεss of thε statε of the control signal such that, when the control signal is in the first state, a substantially fixed phase offset is maintained betwεεn thε first clock signal and thε sampling clock signal, and, whεn thε control signal is in thε sεcond state, the phase offset betweεn the first clock signal and the second clock signal is adjusted.
163. The integrated circuit device of claim 1 further comprising: a buffer to store data values that correspond to the samples of the data signal; a signal generator to genεrate a predεtermined sεquence of values; and a first sεlεct circuit having a first input coupled to the signal generator, a second input coupled to the buffer circuit, and an output coupled an input of thε output drivεr.
164. Thε intεgrated circuit device of claim 5 wherein the first select circuit has a control input coupled to receivε thε control signal, the first select circuit being adapted to output the predetermined sequence of values to the output driver when the control signal is in thε second state, and to output a valuε stored within the buffer to the output driver when the control signal is in the first statε.
165. Thε intεgratεd circuit dεvicε of claim 6 further comprising a second select circuit coupled between the buffer circuit and the second input of the first selεct circuit, thε second select circuit being adapted to selεct onε of a plurality of storagε εlεments within the buffer to output a data value to the sεcond input of thε first sεlεct circuit.
166. Thε integrated circuit device of claim 5 wherein the predeterminεd sεquεncε of valuεs is an altεmating sεquεncε formed by a first digital value and a second digital valuε.
167. Thε intεgratεd circuit dεvicε of claim 1 whεrεin thε clock signal gεnεrator comprisεs a phasε confrol circuit couplεd to thε sampling circuit to receive the samples therefrom, thε phase control circuit being adapted to generate a phase adjust signal according to whethεr the samples indicate a phase lead or phase lag betweεn a component signal of the sample clock signal and transitions in the data signal.
168. The integratεd circuit dεvicε of claim 9 wherem the clock signal genεrator comprisεs: a refεrεncε loop to gεnεratε a plurality of rεference clock signals having incremεntal phasε offsets relativε to onε anothεr; and a first mix logic circuit couplεd to recεivε the refεrεncε clock signals from thε rεfεrence loop and thε phasε adjust signal from the phase control circuit, the first mix logic circuit being adaptεd to incrεmεnt and dεcrεmεnt a phasε count valuε in rεsponsε to thε phasε adjust signal.
169. Thε intεgratεd circuit dεvicε of claim 10 whεrein the first mix logic circuit is further adapted to selεct a pair of thε reference clock signals based on a first component of the phase count value and to generatε an interpolation value based on a second component of the phasε count valuε.
170. Thε integrated circuit device of claim 11 wherεin the clock signal generator further comprises a first clock mixer coupled to receivε thε pair of the refεrεncε clock signals and the interpolation valuε from thε first mix logic circuit, thε first clock mixεr bεing adaptεd to generatε thε samplε clock signal by interpolating betweεn thε rεfεrεncε clock signals of thε pair of thε rεfεrεnce clock signals in accordance with the intεrpolation valuε.
171. A mεthod of opεration within an intεgratεd circuit dεvicε, thε method comprising: capturing samples of a data signal from a signaling path in response to a sampling clock signal; outputting an equalizing signal onto the signaling path in response to a first clock signal; and adjusting a phase of the first clock signal to achievε phasε alignment betwεεn transitions of thε εqualizing signal and fransitions of thε data signal.
172. Thε mεthod of claim 13 furthεr comprising gεnεrating thε samplε clock signal and, whεn a control signal is in a first statε, adjusting a phasε of thε sampling clock signal to reduce a phase difference betwεen the sampling clock signal and transitions in thε data signal.
173. Thε mεthod of claim 14 furthεr comprising suspending adjustment of the phase of thε sampling clock signal whεn thε control signal is in a sεcond statε.
174. Thε mεthod of claim 15 furthεr comprising adjusting thε phasε of thε first clock signal rεgardlεss of thε statε of thε control signal such that, whεn the confrol signal is in the first state, a substantially fixed phase offset is maintained bεtwεen the first clock signal and the sampling clock signal, and, whεn thε control signal is in the second state, the phase offset betweεn thε first clock signal and thε second clock signal is adjusted.
175. The method of claim 13 further comprising: generating a predεtermined sequεnce of values; and selecting, as a source of equalizεr tap valuεs, εither the predeterminεd sequence of values or data values that correspond to the samples of the data signal, and wherεin outputting thε εqualizing signal onto the signal path comprises outputting an equalizing signal having a sequence of signal levels according to the source of εqualizεr tap valuεs.
176. A mεthod of opεration within an εqualizing receiver, the method comprising: outputting a test signal onto a signal path in responsε to fransitions of a first clock signal; sampling thε tεst signal in responsε to transitions of a second clock signal; and adjusting a phase of the first clock signal until transitions in the tεst signal havε a predetermined phase relationship to the transitions of the second clock signal.
177. The mεthod of claim 18 whεrεin outputting thε test signal onto the signal path in response to transitions of the first clock signal comprises selecting a signal gεnεrator to source a sequence of values to an equalizing output driver, the equalizing output driver outputting the tεst signal according to thε sεquεncε of valuεs.
178. Thε mεthod of claim 19 wherein selεcting the signal gεnεrator to source the sequεncε of values comprises sεlεcting thε signal gεnεrator in rεsponsε to a confrol signal being in a first state.
179. The method of claim 18 wherεin sampling thε tεst signal in responsε to transitions of a sεcond clock signal comprisεs: receiving the test signal at an input of a sampling circuit coupled to the signaling path; and capturing samples of the test signal recεivεd at thε input of thε sampling circuit in rεsponsε to transitions of thε second clock signal.
180. The method of claim 18 wherεin adjusting a phasε of thε first clock signal until transitions in thε test signal have a predetεrminεd phasε relationship to thε transitions of the first clock signal comprises adjusting a phase of thε first clock signal until transitions in thε tεst signal arε phasε aligned with transitions of a third clock signal, the transitions of the third clock signal having a substantially fixed phase relationship with transitions of the second clock signal.
181. Thε mεthod of claim 22 wherein the fransitions of the third clock signal havε a quadrature phase relationship to the transitions of the second clock signal.
182. The mεthod of claim 18 wherein outputting a test signal onto the signal path comprises outputting an alternating sequεnce of two distinct signal levels onto the signal path.
183. A signaling systεm comprising: a transmit circuit; a receive circuit; and a signal path coupled betwεεn thε fransmit circuit and thε rεcεivε circuit, thε signal path including: a first signal path segment coupled between the fransmit circuit and a first interface, a second signal path sεgmεnt couplεd bεtwεεn thε receive circuit and a second interface, the second signal path having an electrical length that is substantially equal to an εlectrical length of the first signal path segmεnt; and a third signal path segment coupled to the first signal path segment via the first interface, and coupled to the second signal path segmεnt via thε second interface.
184. The signaling system of claim 1 further comprising a first integrated circuit device and a second integrated circuit device, the transmit circuit bεing disposed in the first integrated circuit device and the recεivε circuit bεing disposεd in thε second integrated circuit device.
185. The signaling system of claim 2 further comprising: a first substrate having the first integrated circuit device, the first signal path segmεnt and the first intεrfacε disposεd thereon; and a second substrate having the second integratεd circuit dεvicε, fhε second signal path segment and thε sεcond intεrfacε disposεd thereon.
186. The signaling system of claim 3 furthεr comprising a third substrate having the third signal path segment disposed thereon, the third substrate being removably coupled to the first substrate and thε sεcond substrate.
187. The signaling system of claim 4 whεrεin thε third subsfratε is a backplanε and thε first and sεcond subsfrates are respεctivε printed circuit boards.
188. The signaling systεm of claim 1 wherein the first interfacε comprisεs a connector interface for removably coupling thε first signal path sεgment to the third signal path sεgmεnt, and whεrεin thε sεcond intεrfacε comprises a connector intεrfacε for removably coupling the second signal path segmεnt to thε third signal path segment.
189. The signaling system of claim 1 wherεin thε first and second signal path segmεnts havε substantially thε samε physical lengths.
190. The signaling systεm of claim 1 wherein the first and second signal path segments have substantially diffεrεnt physical lengths.
191. The signaling system of claim 8 furthεr comprising an impεdance-altering sfructure coupled to at least one of the first and the sεcond signal path sεgmεnts to reduce a difference between the εlεctrical lengths of the first and second signal path segmεnts, the difference between the εlεctrical lengths resulting from, at lεast in part, thε diffεrent physical lengths of thε first and sεcond signal path sεgmεnts.
192. The signaling system of claim 9 wherεin thε impεdance- altering structure is coupled in seriεs with first and sεcond sub-sεgmεnts of the at least one of the first and sεcond signal path sεgmεnts.
193. The signaling system of claim 10 wherεin thε impedance- altεring structure is a signal path sub-segmεnt having a substantially diffεrεnt cross-sectional area than cross-sectional areas of the first and sεcond sub- sεgmεnts.
194. Thε signaling systεm of claim 9 whεrεin thε impedancε- altering structure comprises at least one via.
195. The signaling system of claim 1 further comprising a plurality of impedance-altering structures switchably coupled to at least one of the first and second signal path segments.
196. The signaling system of claim 1 further comprising a configuration circuit coupled to the plurality of impedancε-altεring structures, the impedance-altering structures being switchably coupled to the at least one of the first and second signal path segmεnts in accordance with a setting of the configuration circuit.
197. The signaling system of claim 14 wherein the configuration circuit comprises a registεr to store a configuration valuε, the impedancε- altering structures being selectively coupled to, or decoupled from, the at least one of thε first and sεcond signal path segments in accordance with the configuration value.
198. A method of operation within a signaling system, the method comprising: storing a configuration value in a configuration circuit of the signaling system; selectively coupling a plurality of impedance-altering structures to a first signal path segment in accordance with the configuration value to make an electrical length of the first signal path segment substantially equal to an εlεctrical length of a second signal path segment, the first signal path segment and the second signal path sεgmεnt collectively forming at least part of a signal path betwεen a transmit device and a receivε dεvice of the signaling system.
199. The method of claim 16 further comprising: determining a difference between the elεctrical lengths of the first and second signal path segments; and generating a configuration value that, when applied to selectively couple the plurality of impedance-altεrfng structurεs to thε first signal path sεgmεnt, will reduce the difference betwεεn the electrical lengths of the first and second signal path segments.
200. The method of claim 17 wherεin determining the difference betwεεn thε εlectrical lengths of the first and second signal path segments comprises detεrmining a difference between propagation times of first and second signal reflections.
201. The method of claim 18 wherein determining the difference betwεεn propagation timεs of thε first and sεcond signal reflections comprises: generating, in the receive device, a waveform trace of a test signal transmitted to the receive device via the signal path; and determining, based on the wavεfoπn trace, a difference betwεεn reception times of the first and second signal reflections.
202. An integrated circuit dεvicε comprising: a signal communication circuit; an output node coupled to thε signal communication circuit and adaptεd to couple thε integrated circuit device to a signal path; and a plurality of impedance-altεring structures switchably couplεd to thε output nodε; and a configuration rεgistεr couplεd to the plurality of impedancε-altering structures to selectively couple the plurality of impedancε-altεring structures to the output node in accordance with a configuration value that corresponds to a desirεd εlectrical length of at least a portion of thε signal path.
203. Thε intεgratεd circuit dεvicε of claim 20 whεrεin thε signal communication circuit is a fransmit circuit.
204. Thε intεgrated circuit device of claim 20 wherein the signal communication circuit is a receivε circuit.
PCT/US2003/021566 2002-07-12 2003-07-10 A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics WO2004008490A2 (en)

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US10/195,130 US7362800B1 (en) 2002-07-12 2002-07-12 Auto-configured equalizer
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006038190A1 (en) * 2004-10-08 2006-04-13 Koninklijke Philips Electronics N.V. Array of capacitors switched by mos transistors
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7412016B2 (en) 2003-04-09 2008-08-12 Rambus Inc. Data-level clock recovery
US7423454B2 (en) 2003-12-17 2008-09-09 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7715471B2 (en) 2003-12-17 2010-05-11 Rambus, Inc. Signaling system with selectively-inhibited adaptive equalization
WO2016114548A1 (en) * 2015-01-12 2016-07-21 Samsung Electronics Co., Ltd. Signal transmission and receiving method, system and apparatus based on filter bank
US9461608B2 (en) 2007-03-05 2016-10-04 Nxp B.V. Radio frequency filter
CN113225278A (en) * 2020-01-21 2021-08-06 默升科技集团有限公司 Digital equalizer with overlapping filter taps
CN113364713A (en) * 2015-07-28 2021-09-07 拉姆伯斯公司 Burst tolerant decision feedback equalization

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4359778A (en) * 1981-02-05 1982-11-16 Zenith Radio Corporation Channel equalizer and method for cancelling ghosts
US4581747A (en) * 1984-03-05 1986-04-08 At&T Bell Laboratories Arrangement for equalizing the variable attenuation of a signal on a communication line
US5691993A (en) * 1995-06-07 1997-11-25 Seagate Technology, Inc. Rate 4/5 trellis code for PR4 channels with improved error propagation
US6304098B1 (en) * 2000-03-14 2001-10-16 Sun Microsystems, Inc. Method and apparatus for reducing noise in communication channels having a shared reference signal
US6344749B1 (en) * 1997-05-29 2002-02-05 Thomas H. Williams Test system for measuring frequency response and dynamic range on cable plant
US20020181360A1 (en) * 2001-05-31 2002-12-05 Fujitsu Clock adjusting device for use with data reproducing apparatus, offset detecting device, and data reporducing apparatus
US6513136B1 (en) * 1999-09-18 2003-01-28 Marconi Communications Limited Communications receiver arrangement
US6530062B1 (en) * 2000-03-10 2003-03-04 Rambus Inc. Active impedance compensation
US6563870B1 (en) * 1997-12-22 2003-05-13 Infineon Technologies Ag Nonlinear echo compensator
US6687311B1 (en) * 2000-02-15 2004-02-03 General Instrument Corporation Direct QAM modulator with digital feedback control and complex pre-equalization for phase and amplitude distortion

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4359778A (en) * 1981-02-05 1982-11-16 Zenith Radio Corporation Channel equalizer and method for cancelling ghosts
US4581747A (en) * 1984-03-05 1986-04-08 At&T Bell Laboratories Arrangement for equalizing the variable attenuation of a signal on a communication line
US5691993A (en) * 1995-06-07 1997-11-25 Seagate Technology, Inc. Rate 4/5 trellis code for PR4 channels with improved error propagation
US6344749B1 (en) * 1997-05-29 2002-02-05 Thomas H. Williams Test system for measuring frequency response and dynamic range on cable plant
US6563870B1 (en) * 1997-12-22 2003-05-13 Infineon Technologies Ag Nonlinear echo compensator
US6513136B1 (en) * 1999-09-18 2003-01-28 Marconi Communications Limited Communications receiver arrangement
US6687311B1 (en) * 2000-02-15 2004-02-03 General Instrument Corporation Direct QAM modulator with digital feedback control and complex pre-equalization for phase and amplitude distortion
US6530062B1 (en) * 2000-03-10 2003-03-04 Rambus Inc. Active impedance compensation
US6304098B1 (en) * 2000-03-14 2001-10-16 Sun Microsystems, Inc. Method and apparatus for reducing noise in communication channels having a shared reference signal
US20020181360A1 (en) * 2001-05-31 2002-12-05 Fujitsu Clock adjusting device for use with data reproducing apparatus, offset detecting device, and data reporducing apparatus

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9025678B2 (en) 2003-04-09 2015-05-05 Rambus Inc. Partial response receiver
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7412016B2 (en) 2003-04-09 2008-08-12 Rambus Inc. Data-level clock recovery
US11502878B2 (en) 2003-04-09 2022-11-15 Rambus Inc. Partial response receiver
US7433397B2 (en) 2003-04-09 2008-10-07 Rambus Inc. Partial response receiver with clock data recovery
US10764094B2 (en) 2003-04-09 2020-09-01 Rambus Inc. Partial response receiver
US10225111B2 (en) 2003-04-09 2019-03-05 Rambus Inc. Partial response receiver
US7715509B2 (en) 2003-04-09 2010-05-11 Rambus Inc. Partial response receiver
US7715501B2 (en) 2003-04-09 2010-05-11 Rambus, Inc. Partial response receiver
US8170163B2 (en) 2003-04-09 2012-05-01 Rambus Inc. Partial response receiver
US9917708B2 (en) 2003-04-09 2018-03-13 Rambus Inc. Partial response receiver
US9407473B2 (en) 2003-04-09 2016-08-02 Rambus Inc. Partial response receiver
US9287909B2 (en) 2003-12-17 2016-03-15 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US11233678B2 (en) 2003-12-17 2022-01-25 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US11706061B2 (en) 2003-12-17 2023-07-18 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US8994398B2 (en) 2003-12-17 2015-03-31 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US9000803B2 (en) 2003-12-17 2015-04-07 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US9705710B2 (en) 2003-12-17 2017-07-11 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US8564328B2 (en) 2003-12-17 2013-10-22 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7715471B2 (en) 2003-12-17 2010-05-11 Rambus, Inc. Signaling system with selectively-inhibited adaptive equalization
US10411923B2 (en) 2003-12-17 2019-09-10 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7423454B2 (en) 2003-12-17 2008-09-09 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7656981B2 (en) 2003-12-17 2010-02-02 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US10771295B2 (en) 2003-12-17 2020-09-08 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
WO2006038190A1 (en) * 2004-10-08 2006-04-13 Koninklijke Philips Electronics N.V. Array of capacitors switched by mos transistors
US9461608B2 (en) 2007-03-05 2016-10-04 Nxp B.V. Radio frequency filter
US10476544B2 (en) 2015-01-12 2019-11-12 Samsung Electronics Co., Ltd. Signal transmission and receiving method, system and apparatus based on filter bank
WO2016114548A1 (en) * 2015-01-12 2016-07-21 Samsung Electronics Co., Ltd. Signal transmission and receiving method, system and apparatus based on filter bank
CN113364713A (en) * 2015-07-28 2021-09-07 拉姆伯斯公司 Burst tolerant decision feedback equalization
CN113225278A (en) * 2020-01-21 2021-08-06 默升科技集团有限公司 Digital equalizer with overlapping filter taps

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