WO2001099105A3 - Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel - Google Patents

Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel Download PDF

Info

Publication number
WO2001099105A3
WO2001099105A3 PCT/US2001/019683 US0119683W WO0199105A3 WO 2001099105 A3 WO2001099105 A3 WO 2001099105A3 US 0119683 W US0119683 W US 0119683W WO 0199105 A3 WO0199105 A3 WO 0199105A3
Authority
WO
WIPO (PCT)
Prior art keywords
loop
synchronization loop
acquisition
interpolator
sampling clock
Prior art date
Application number
PCT/US2001/019683
Other languages
French (fr)
Other versions
WO2001099105A2 (en
Inventor
James Wilson Rae
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Publication of WO2001099105A2 publication Critical patent/WO2001099105A2/en
Publication of WO2001099105A3 publication Critical patent/WO2001099105A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Abstract

Systems and methods for reading information stored on a magnetic medium are described. Data symbols are generated from a signal encoded at a baud rate with data including an acquisition preamble (54) defining an acquisition frequency and an acquisition phase. The system includes an inventive dual loop synchronizer (100) that is optimized to improve the operating efficiency and reduce the overall latency of the read channel (70). In one aspect, the dual loop synchronizer (100) includes a frequency synchronization loop (102), a signal sampler (84), an interpolator (88), and a phase synchronization loop (104). The frequency synchronization loop (102) is configured to generate a sampling clock (124) synchronized approximately to the acquisition frequency and the acquisition phase of the encoded data signal. The signal sampler (84) is coupled to the frequency synchronization loop (102) and is configured to sample the encoded data signal in response to the sampling clock (124) to produce a plurality of data samples. The interpolator (88) is coupled to the frequency synchronization loop (102) and is configured to produce in response to the sampling clock (124) interpolated samples from the data samples. The phase synchronization loop (104) is coupled to the interpolator (88) and is configured to synchronize the interpolator (88) to the baud rate of the encoded data signal. In another aspect, the frequency synchronization loop (102) includes a delay-locked loop (116) configured to synthesize the sampling clock (124).
PCT/US2001/019683 2000-06-20 2001-06-20 Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel WO2001099105A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US21290300P 2000-06-20 2000-06-20
US60/212,903 2000-06-20
US09/882,084 2001-06-13
US09/882,084 US6816328B2 (en) 2000-06-20 2001-06-13 Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel

Publications (2)

Publication Number Publication Date
WO2001099105A2 WO2001099105A2 (en) 2001-12-27
WO2001099105A3 true WO2001099105A3 (en) 2002-03-28

Family

ID=26907592

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/019683 WO2001099105A2 (en) 2000-06-20 2001-06-20 Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel

Country Status (2)

Country Link
US (1) US6816328B2 (en)
WO (1) WO2001099105A2 (en)

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3949357B2 (en) * 2000-07-13 2007-07-25 富士通株式会社 Demodulator
US7304545B1 (en) 2000-11-30 2007-12-04 Marvell International Ltd. High latency timing circuit
US6732286B1 (en) * 2000-11-30 2004-05-04 Marvell International, Ltd. High latency timing circuit
US7082005B2 (en) * 2001-10-24 2006-07-25 Agere Systems Inc. Servo data detection in the presence or absence of radial incoherence using digital interpolators
US7019922B2 (en) * 2003-04-29 2006-03-28 International Business Machines Corporation Apparatus and method to read information from a tape storage medium
TWI231475B (en) * 2003-09-15 2005-04-21 Mediatek Inc Method for estimation parameter adaptability adjustment of an optical storage device
US6987633B2 (en) * 2003-10-10 2006-01-17 International Business Machines Corporation Apparatus and method to read information from a tape storage medium
US7317586B1 (en) * 2004-06-07 2008-01-08 Maxtor Corporation Methods and structure for general purpose interval accumulating filter for measuring operational parameters of a digital read channel
EP1622300A1 (en) * 2004-07-30 2006-02-01 STMicroelectronics S.r.l. Method for improving the robustness of synchronization system in the Hard Disk Drive through a minimum latency loop
JP2006127661A (en) * 2004-10-29 2006-05-18 Toshiba Corp Digital data reproducing apparatus and method
US7583459B1 (en) 2004-11-18 2009-09-01 Marvell International Ltd. Method and apparatus for write precompensation in a magnetic recording system
US7167328B2 (en) * 2004-12-17 2007-01-23 Agere Systems Inc. Synchronizing an asynchronously detected servo signal to synchronous servo demodulation
JP4459094B2 (en) * 2005-03-14 2010-04-28 東芝ストレージデバイス株式会社 Medium storage device and method for synchronizing rotation of medium of medium storage device
US7773324B2 (en) * 2005-04-12 2010-08-10 Stmicroelectronics, Inc. Phase acquisition loop for a read channel and related read channel, system, and method
US7768732B2 (en) 2005-04-12 2010-08-03 Stmicroelectronics, Inc. Gain controller for a gain loop of a read channel and related gain loops, read channels, systems, and methods
WO2007007421A1 (en) * 2005-07-07 2007-01-18 Matsushita Electric Industrial Co., Ltd. Timing extraction device and image display device
JP4179418B2 (en) * 2005-07-13 2008-11-12 京セラ株式会社 Wireless receiver
US7394608B2 (en) * 2005-08-26 2008-07-01 International Business Machines Corporation Read channel apparatus for asynchronous sampling and synchronous equalization
US7738200B2 (en) * 2006-05-01 2010-06-15 Agere Systems Inc. Systems and methods for estimating time corresponding to peak signal amplitude
US7605737B2 (en) * 2007-03-08 2009-10-20 Texas Instruments Incorporated Data encoding in a clocked data interface
US8619532B1 (en) * 2007-04-17 2013-12-31 Marvell International Ltd. Asynchronous asymmetry compensation
US8054931B2 (en) * 2007-08-20 2011-11-08 Agere Systems Inc. Systems and methods for improved timing recovery
US8254049B2 (en) * 2007-08-20 2012-08-28 Agere Systems Inc. Systems and methods for improved synchronization between an asynchronously detected signal and a synchronous operation
CN101647062B (en) * 2007-10-30 2012-07-18 艾格瑞系统有限公司 Systems and methods for inter-location control of storage access
EP2179417A4 (en) * 2007-12-14 2013-12-18 Lsi Corp Systems and methods for fly-height control using servo address mark data
KR101481203B1 (en) 2007-12-14 2015-01-09 엘에스아이 코포레이션 Systems and methods for adaptive cbd estimation in a storage device
KR101481202B1 (en) * 2007-12-14 2015-01-09 엘에스아이 코포레이션 Systems and methods for fly-height control using servo data
US7813065B2 (en) * 2008-04-29 2010-10-12 Agere Systems Inc. Systems and methods for acquiring modified rate burst demodulation in servo systems
US7768437B2 (en) * 2008-04-29 2010-08-03 Agere Systems Inc. Systems and methods for reducing the effects of ADC mismatch
US8018360B2 (en) * 2008-05-19 2011-09-13 Agere Systems Inc. Systems and methods for mitigating latency in a data detector feedback loop
US7929237B2 (en) * 2008-06-27 2011-04-19 Agere Systems Inc. Modulated disk lock clock and methods for using such
CN101821808B (en) * 2008-07-28 2014-03-19 艾格瑞系统有限公司 Systems and methods for fly height measurement for between a head assembly and a storage medium
US8705673B2 (en) 2008-09-05 2014-04-22 Lsi Corporation Timing phase detection using a matched filter set
US8976913B2 (en) * 2008-09-17 2015-03-10 Lsi Corporation Adaptive pattern dependent noise prediction on a feed forward noise estimate
US8243381B2 (en) 2008-11-13 2012-08-14 Agere Systems Inc. Systems and methods for sector address mark detection
US9305581B2 (en) 2008-12-04 2016-04-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for memory efficient repeatable run out processing
US7982985B1 (en) * 2009-04-17 2011-07-19 Marvell International Ltd. Method and apparatus for adapting a finite impulse response equalizer in a hard disk drive read channel
US8154972B2 (en) 2009-06-24 2012-04-10 Lsi Corporation Systems and methods for hard disk drive data storage including reduced latency loop recovery
US8174949B2 (en) * 2009-07-02 2012-05-08 Lsi Corporation Systems and methods for format efficient timing recovery in a read channel
CN101964654A (en) 2009-07-22 2011-02-02 Lsi公司 System and method for high-order asymmetric correction
US8456775B2 (en) * 2009-12-31 2013-06-04 Lsi Corporation Systems and methods for detecting a reference pattern
US8566381B2 (en) 2010-08-05 2013-10-22 Lsi Corporation Systems and methods for sequence detection in data processing
US8237597B2 (en) 2010-09-21 2012-08-07 Lsi Corporation Systems and methods for semi-independent loop processing
US8566378B2 (en) 2010-09-30 2013-10-22 Lsi Corporation Systems and methods for retry sync mark detection
US8879185B1 (en) * 2010-11-03 2014-11-04 Marvell International Ltd. Disk synchronous write architecture for bit-patterned recording
US8614858B2 (en) 2010-11-15 2013-12-24 Lsi Corporation Systems and methods for sync mark detection metric computation
US8498072B2 (en) 2010-11-29 2013-07-30 Lsi Corporation Systems and methods for spiral waveform detection
US8526131B2 (en) 2010-11-29 2013-09-03 Lsi Corporation Systems and methods for signal polarity determination
US8411385B2 (en) 2010-12-20 2013-04-02 Lsi Corporation Systems and methods for improved timing recovery
US8325433B2 (en) 2011-01-19 2012-12-04 Lsi Corporation Systems and methods for reduced format data processing
US8261171B2 (en) 2011-01-27 2012-09-04 Lsi Corporation Systems and methods for diversity combined data detection
US8749908B2 (en) * 2011-03-17 2014-06-10 Lsi Corporation Systems and methods for sync mark detection
US8565047B2 (en) 2011-04-28 2013-10-22 Lsi Corporation Systems and methods for data write loopback based timing control
US8665544B2 (en) 2011-05-03 2014-03-04 Lsi Corporation Systems and methods for servo data detection
US8874410B2 (en) 2011-05-23 2014-10-28 Lsi Corporation Systems and methods for pattern detection
US8498071B2 (en) 2011-06-30 2013-07-30 Lsi Corporation Systems and methods for inter-track alignment
US8669891B2 (en) * 2011-07-19 2014-03-11 Lsi Corporation Systems and methods for ADC based timing and gain control
US8780476B2 (en) 2011-09-23 2014-07-15 Lsi Corporation Systems and methods for controlled wedge spacing in a storage device
US8773811B2 (en) 2011-12-12 2014-07-08 Lsi Corporation Systems and methods for zone servo timing gain recovery
US8625216B2 (en) 2012-06-07 2014-01-07 Lsi Corporation Servo zone detector
US8681444B2 (en) 2012-06-07 2014-03-25 Lsi Corporation Multi-zone servo processor
US8564897B1 (en) 2012-06-21 2013-10-22 Lsi Corporation Systems and methods for enhanced sync mark detection
US8751915B2 (en) * 2012-08-28 2014-06-10 Lsi Corporation Systems and methods for selectable positive feedback data processing
US9019641B2 (en) 2012-12-13 2015-04-28 Lsi Corporation Systems and methods for adaptive threshold pattern detection
US8773799B1 (en) 2012-12-21 2014-07-08 Lsi Corporation Signal processing circuitry with frontend and backend circuitry controlled by separate clocks
US9053217B2 (en) 2013-02-17 2015-06-09 Lsi Corporation Ratio-adjustable sync mark detection system
US9214959B2 (en) 2013-02-19 2015-12-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for skip layer data decoding
US9385858B2 (en) * 2013-02-20 2016-07-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Timing phase estimation for clock and data recovery
US8780470B1 (en) 2013-03-11 2014-07-15 Western Digital Technologies, Inc. Disk drive adjusting digital phase locked loop over sector data with frequency induced phase error measured over preamble
US9196297B2 (en) 2013-03-14 2015-11-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for enhanced sync mark mis-detection protection
US9274889B2 (en) 2013-05-29 2016-03-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for data processing using global iteration result reuse
US9275655B2 (en) 2013-06-11 2016-03-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Timing error detector with diversity loop detector decision feedback
US8959414B2 (en) 2013-06-13 2015-02-17 Lsi Corporation Systems and methods for hybrid layer data decoding
US10152999B2 (en) 2013-07-03 2018-12-11 Avago Technologies International Sales Pte. Limited Systems and methods for correlation based data alignment
US8917466B1 (en) 2013-07-17 2014-12-23 Lsi Corporation Systems and methods for governing in-flight data sets in a data processing system
US8817404B1 (en) 2013-07-18 2014-08-26 Lsi Corporation Systems and methods for data processing control
US9129650B2 (en) 2013-07-25 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with frequency division multiplexing
US8908307B1 (en) 2013-08-23 2014-12-09 Lsi Corporation Systems and methods for hard disk drive region based data encoding
US9196299B2 (en) 2013-08-23 2015-11-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for enhanced data encoding and decoding
US9129646B2 (en) 2013-09-07 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with mixed synchronization
US9400797B2 (en) 2013-09-17 2016-07-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for recovered data stitching
US9219503B2 (en) 2013-10-16 2015-12-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-algorithm concatenation encoding and decoding
US9323625B2 (en) 2013-11-12 2016-04-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for lost synchronization data set reprocessing
US9323606B2 (en) 2013-11-21 2016-04-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for FAID follower decoding
RU2014104571A (en) 2014-02-10 2015-08-20 ЭлЭсАй Корпорейшн SYSTEMS AND METHODS FOR AN EFFECTIVE PERFORMANCE AREA FOR DATA ENCODING
US9378765B2 (en) 2014-04-03 2016-06-28 Seagate Technology Llc Systems and methods for differential message scaling in a decoding process
US9224420B1 (en) 2014-10-02 2015-12-29 Avago Technologies General Ip (Singapore) Pte. Ltd. Syncmark detection failure recovery system
US9734860B2 (en) 2015-09-18 2017-08-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for a data processing using integrated filter circuit
JP6249029B2 (en) * 2016-03-08 2017-12-20 Ｎｔｔエレクトロニクス株式会社 Data phase tracking device, data phase tracking method, and communication device
CN114675790B (en) * 2022-05-24 2022-08-23 华中科技大学 Self-correcting method for synchronous data storage of multichannel parallel sampling system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61189093A (en) * 1985-02-15 1986-08-22 Sony Corp Synchronous circuit
EP0618574A2 (en) * 1993-03-31 1994-10-05 Sony Corporation Clock reproducing apparatus and data reproducing apparatus
EP0777211A2 (en) * 1995-12-05 1997-06-04 Cirrus Logic, Inc. A magnetic disk sampled amplitude read channel employing interpolated timing recovery for synchronous detection of embedded servo data
US5835295A (en) * 1996-11-18 1998-11-10 Cirrus Logice, Inc. Zero phase restart interpolated timing recovery in a sampled amplitude read channel
US6028727A (en) * 1997-09-05 2000-02-22 Cirrus Logic, Inc. Method and system to improve single synthesizer setting times for small frequency steps in read channel circuits
US6111712A (en) * 1998-03-06 2000-08-29 Cirrus Logic, Inc. Method to improve the jitter of high frequency phase locked loops used in read channels

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920002273B1 (en) * 1989-07-08 1992-03-20 삼성전자 주식회사 Quadrature modulation and demodulation method and circuit using remoting pll
US5424881A (en) 1993-02-01 1995-06-13 Cirrus Logic, Inc. Synchronous read channel
US5696639A (en) 1995-05-12 1997-12-09 Cirrus Logic, Inc. Sampled amplitude read channel employing interpolated timing recovery
US5943369A (en) 1996-02-27 1999-08-24 Thomson Consumer Electronics, Inc. Timing recovery system for a digital signal processor
US6307696B1 (en) * 1999-05-06 2001-10-23 Maxtor Corporation Digital zero-phase restart circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61189093A (en) * 1985-02-15 1986-08-22 Sony Corp Synchronous circuit
EP0618574A2 (en) * 1993-03-31 1994-10-05 Sony Corporation Clock reproducing apparatus and data reproducing apparatus
EP0777211A2 (en) * 1995-12-05 1997-06-04 Cirrus Logic, Inc. A magnetic disk sampled amplitude read channel employing interpolated timing recovery for synchronous detection of embedded servo data
US5835295A (en) * 1996-11-18 1998-11-10 Cirrus Logice, Inc. Zero phase restart interpolated timing recovery in a sampled amplitude read channel
US6028727A (en) * 1997-09-05 2000-02-22 Cirrus Logic, Inc. Method and system to improve single synthesizer setting times for small frequency steps in read channel circuits
US6111712A (en) * 1998-03-06 2000-08-29 Cirrus Logic, Inc. Method to improve the jitter of high frequency phase locked loops used in read channels

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Infineon Technoligies Launches Integrated CMOS Read-Channel IC Chipset for System-on-Chip Performance in Hard Disk Drives", INTERNET ARTICLE, 15 May 2000 (2000-05-15), XP002186309, Retrieved from the Internet <URL:http://www.infineon-ncs.com/articles/05-15-00_Read_Channel_PressRelease.pdf> [retrieved on 20011213] *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 017 (E - 471) 17 January 1987 (1987-01-17) *
SPURBECK M ET AL: "INTERPOLATED TIMING RECOVERY FOR HARD DISK DRIVE READ CHANNELS", 1997 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS. MONTREAL, JUNE 8 - 12, 1997, IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), NEW YORK, IEEE, US, vol. 3, 8 June 1997 (1997-06-08), pages 1618 - 1624, XP000748916, ISBN: 0-7803-3926-6 *

Also Published As

Publication number Publication date
US6816328B2 (en) 2004-11-09
US20020021519A1 (en) 2002-02-21
WO2001099105A2 (en) 2001-12-27

Similar Documents

Publication Publication Date Title
WO2001099105A3 (en) Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel
US5293369A (en) Asynchronous sampling digital detector system for magnetic and optical recording channels
US8411385B2 (en) Systems and methods for improved timing recovery
JP2003281831A5 (en)
JP4133474B2 (en) Information recording / reproducing apparatus, signal recording / reproducing circuit, and information recording / reproducing method
EP0777211A3 (en) A magnetic disk sampled amplitude read channel employing interpolated timing recovery for synchronous detection of embedded servo data
KR970072661A (en) Gain and Phase Limit Adaptive Equalizer Filters on Sample-Amplitude Read Channels for Magnetic Recording
EP0805447A3 (en) Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording
CA2110826A1 (en) Clock Recovery Circuit of Demodulator
EP0769781A3 (en) Cost reduced interpolated timing recovery in a sampled amplitude read channel
WO2001078275A3 (en) Clock recovery in a packet-based data network
US7193942B2 (en) Phase difference correction apparatus and data reproduction apparatus including data header detection apparatus
EP0889473A3 (en) Method and apparatus for recovering digital data by employing asynchronous data sampling technique
JP3220715B2 (en) Apparatus and method for synchronizing clock signals
EP0805438A3 (en) Servo circuit, digital PLL circuit and optical disk device
TW336313B (en) Phase locked loop system and method for use in a data channel
WO2008078545A1 (en) Information reproducing apparatus
GB2353618A (en) Multiple synthesizer based timing signal generation scheme
US6845490B2 (en) Clock switching circuitry for jitter reduction
CN1238879A (en) Carrier phase synchronization by reverse playback
JP2001210020A5 (en)
EP1217622A3 (en) Digital data play back apparatus and method for playing back digital data
TW200518467A (en) Phase error determination method and digital phase-locked loop system
EP1045392A3 (en) Sampling clock apparatus for a data reproduction system
US7372797B2 (en) Data reproduction device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR SG

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): CN JP KR SG

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP