WO2001054125A1 - Appareil d'enregistrement/reproduction numeriques de donnees - Google Patents
Appareil d'enregistrement/reproduction numeriques de donnees Download PDFInfo
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- WO2001054125A1 WO2001054125A1 PCT/JP2001/000235 JP0100235W WO0154125A1 WO 2001054125 A1 WO2001054125 A1 WO 2001054125A1 JP 0100235 W JP0100235 W JP 0100235W WO 0154125 A1 WO0154125 A1 WO 0154125A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
- G11B20/10277—Improvement or modification of read or write signals bit detection or demodulation methods the demodulation process being specifically adapted to partial response channels, e.g. PRML decoding
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
- G11B20/10231—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein an asynchronous, free-running clock is used; Interpolation of sampled signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
- G11B20/1024—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10305—Improvement or modification of read or write signals signal quality assessment
- G11B20/10398—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
- G11B20/10425—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors by counting out-of-lock events of a PLL
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10305—Improvement or modification of read or write signals signal quality assessment
- G11B20/10398—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
- G11B20/10444—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors by verifying the timing of zero crossings
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/00007—Time or data compression or expansion
- G11B2020/00014—Time or data compression or expansion the compressed signal being an audio signal
- G11B2020/00065—Sigma-delta audio encoding
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
- G11B2020/1264—Formatting, e.g. arrangement of data block or words on the record carriers wherein the formatting concerns a specific kind of data
- G11B2020/1265—Control data, system data or management information, i.e. data used to access or process user data
- G11B2020/1287—Synchronisation pattern, e.g. VCO fields
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
Definitions
- the present invention relates to a digital recording data reproducing apparatus for reproducing digital data recorded on a recording medium, and more particularly to a digital recording data reproducing apparatus for improving phase locked loop and offset correction. Under poor conditions such as waveform quality deterioration, reproduction under poor signal / noise ratio, and frequent occurrence of diff, etc., not only the reproduced digital data quality is improved, but also playability, that is, The present invention relates to a device having features such as improved reproducibility.
- Tilt refers to the deviation of the angle between the perpendicular to the signal surface of the optical disc and the optical axis of the laser beam, and the differential is the reproduction of scratches on the signal surface of the optical disc, adhesion of fingerprints, etc. It is a disturbance factor of the waveform.
- a method for recording digital data on an optical disk medium a method for keeping the linear velocity constant and uniform recording density on the recording medium, such as a compact disk (DVD) or a DVD, is often used. I have.
- the reproduction linear velocity period is detected based on a specific pulse length and pulse interval included in the reproduction signal to control the rotation speed of the disk and to run the phase locked loop by itself. By controlling the frequency, the normal position It has been attempted to enable phase synchronization pull-in.
- FIG. 24 (a) there is a disk reproducing system as shown in FIG. A digital recording code as shown in FIG. 24 (a) is recorded on the optical disc 55 so that the linear recording density is constant. It is assumed that the recorded data is data regulated such that the number of consecutive “0” s or “1” s is 3 or more and 14 or less, for example, in an 8- 16 modulation method.
- the signal obtained by reproduction by the reproduction means 56 such as an optical pickup is converted into a high-frequency component as the recording density in the linear direction of the recording data increases. Indeed, the amplitude attenuates. This is because the influence of interference becomes noticeable as the recording density increases.
- the signal obtained by reproduction is amplified by a preamplifier (not shown), the high-frequency Is corrected to emphasize.
- the reproduced signal subjected to high-frequency emphasis is sampled into a multi-bit digital signal by an analog / digital converter 3 as a means for converting an analog signal into a digital signal.
- the reproduced clock generated by the VCO (voltage-controlled oscillator) 40 is used as a sampling clock, and the phase of the reproduced clock by VC040 and the phase of the clock component of the reproduced signal by the reproducing means 56 are If are synchronized, sampled data as shown in Fig. 24 (c) can be obtained.
- Fig. 24 (c) shows sampled data particularly suitable for a partial response maximum likelihood (hereinafter abbreviated as PRML) signal processing method.
- PRML partial response maximum likelihood
- the amplitude of the high-frequency component of the signal is degraded as the recording density in the linear recording direction increases, and the signal interference ratio is increased.
- the error rate of the reproduced data can be improved by using the maximum likelihood decoding method that demodulates the likely sequence by probabilistic calculation considering the power and the waveform interference without using the high frequency component in the reproduced signal. It is a method that
- the offset correcting means 4 By inputting the sampled multi-bit digital signal to the offset correcting means 4, the offset component included in the reproduced digital signal is corrected. Then, the reproduced digital signal subjected to the offset correction is transmitted to the transversal filter 6. Input and perform partial response equalization.
- the application of the partial response equalization has a feature that the equalized output signal is multi-valued as shown in FIG. 24 (d).
- the weight coefficients of the taps of the transversal filter 6 are determined by using a least mean square (LMS) algorithm that minimizes the root mean square value of the equalization error. It is supplied by weight coefficient setting means 57.
- LMS least mean square
- the multi-level output signal of the transversal filter 6 is demodulated by a Viterbi decoder 58, which is a kind of maximum likelihood decoder, to obtain binary digital data.
- the phase-synchronized reproduction clock used for sampling by the analog-to-digital converter 3 is controlled as follows. That is, from the output signal of the offset correction means 4, the position where this output signal crosses zero level is continuously detected, and the output of the zero cross length detector 59 which counts the number of samples between adjacent zero crosses is used. By detecting the synchronization pattern length in a specific period of one frame or more, and detecting the detection period of the synchronization pattern by the frequency error detector 13, the frequency error for controlling the frequency of the reproduction clock is determined. The amount is determined. Also, the phase information of the reproduced digital data is detected by the phase comparator 9 using the output signal of the offset correction means 4, and the phase error amount for performing the phase synchronization control between the reproduced clock and the reproduced digital data is determined. .
- VCO 40 is controlled by digital / analog converter 4 2 b.
- the phase control loop filter 60 and the digital / analog converter 42 a are used to generate VC 0 40 so that the reproduced clock is synchronized with the reproduced digital signal using the phase error amount output from the phase comparator 9.
- the phase error detection which is one end of the phase locked loop
- the deterioration of the reproduced signal due to the tilt and the equalization characteristic of the waveform equalization means If the phase error is insufficient, the phase error information will be inaccurate and the jitter of the phase locked loop will increase.
- the signal sampled by the analog-to-digital converter is no longer in a normal phase state, so that the partial response equalization by the transversal filter cannot exhibit its performance sufficiently.
- the signal quality of the reproduced signal is degraded, and the error rate may be degraded.
- the present invention has been made in view of such circumstances, and is suitable for partial response equalization, has a high phase synchronization pull-in capability, and has a high error rate even under conditions in which characteristic degradation due to tilt and analog equalization are insufficient. It is an object of the present invention to provide a digital recording / reproducing apparatus capable of reducing the data. Disclosure of the invention
- the digital recording data reproducing apparatus samples a reproduction signal of a recording medium into digital data asynchronously with a phase of a click component included in the signal.
- An interpolation filter for reproducing a signal at a normal sampling phase from the response-equalized signal by interpolation, and adapting a filter coefficient of the equalization filter based on an output signal of the interpolation filter so that an equalization error is minimized.
- Filter coefficient control means for controlling the phase error, and detecting the phase error based on the output signal of the interpolation filter,
- a phase-locked loop that updates the filter coefficients of the above, and a maximum likelihood decoder that performs data demodulation by performing maximum likelihood decoding according to the type of the partial response obtained by equalizing the output signal of the interpolation filter with the equalization filter described above. It is provided with. This makes it possible to perform maximum likelihood decoding based on interpolation data at a regular sampling phase, and to perform digital data demodulation suitable for partial response maximum likelihood decoding without being affected by waveform degradation due to tilt of the reproduced signal. It becomes possible, and has a recording operation.
- the digital recording data reproducing apparatus samples a reproduction signal of a recording medium into digital data asynchronously with a phase of a clock component included in the signal.
- Analog-to-digital conversion means, digital data correction means for correcting an offset component and amplitude from the sampled signal, an equalization filter for performing partial response equalization on the corrected signal, and the equalization filter A phase-locked loop for detecting a phase error based on the output signal of the equalizing filter; and adaptively controlling a filter coefficient of the equalizing filter based on an output signal of the equalizing filter so that the equalizing error is minimized.
- a filter coefficient control means for controlling a filter coefficient so as to eliminate a phase error based on an output of the synchronous loop;
- a maximum likelihood decoder that performs data demodulation by performing maximum likelihood decoding in accordance with the type of the equalized partial response is provided.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 1 or 2, wherein: A clock generating means for generating a clock whose phase is asynchronous with the clock signal included in the clock signal; and controlling a frequency of a clock generated by the clock generating means based on an output of the phase locked loop. Frequency control means, and a clock position generated by the clock generation means based on an output of the phase locked loop. And phase synchronization maintaining means for performing control so that the phases maintain a synchronized state.
- the digital recording data reproducing apparatus is the digital recording data reproducing apparatus according to claim 3, wherein the frequency control means and the phase synchronization maintaining means Delta-sigma modulation means for performing a delta-sigma modulation on the control signal from the controller, and a low-pass filter for removing a high-frequency component of the output signal of the delta-sigma modulation means. .
- the disturbance of the phase locked loop when switching from rough control to up / down control can be suppressed, smooth frequency tracking can be performed, more stable phase lock-in can be achieved, and the error rate of the playback data is improved. it can.
- the control of the clock generation means may be designed mainly in consideration of the improvement of the control performance of the rough control, it has an effect that the analog circuit can be simplified.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 4, wherein a time constant of the low-pass filter is changed. This is provided with a time constant varying means for causing the time constant to be changed.
- the reproduction time of the recording medium changes, the time constant can be varied according to the change speed.
- the reproduction time does not depend on the reproduction speed. It has the function of enabling smooth frequency tracking.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 1 or 2, wherein the digital data correction means is When performing offset adjustment, the amplitude component of that point is added at the point where the center line of the sampled waveform crosses the zero level, and at the other points where the sign is fixed, According to the raw code, a predetermined value corresponding to the polarity is added. As a result, the accuracy of the offset error information is increased, and even when the offset adjustment is made to respond to DC fluctuations including high-frequency components, the operation can be stabilized and the noise after the adjustment can be reduced. It has the effect of realizing effective data reproduction means.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 1 or 2, wherein the digital data correction means is When performing offset adjustment, the amplitude component of the sampled waveform is added at the point where the center line of the sampled waveform crosses the zero level, and at other points where the sign is fixed, playback is performed. According to the sign, a value corresponding to the polarity is added, and the added value is made different between the seek operation and the rest.
- the accuracy of the offset error information is increased, and even when the offset adjustment is made to respond to DC fluctuations including high-frequency components, the operation can be stabilized and the noise after the adjustment can be reduced.
- an effective data reproducing means can be realized, and control according to the operating condition can be performed, so that playability can be improved.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 7, wherein the digital data correction unit is configured to perform a seek operation.
- the value of the addition value is increased, and the value of the addition value is reduced in the phase synchronization state.
- the tracking performance is improved during the seek operation, and the control noise can be suppressed when the phase is in the synchronized state, so that the optimum offset control can be performed.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 1 or 2, wherein the digital data correction means is When performing offset adjustment, the cumulative addition value of the sampled waveform at each point for a predetermined time is monitored, and the DC error amount is discretely fed back to the DC component. .
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 2, wherein the filter coefficient control means includes a phase synchronization pull-in. After that, partial response equalization is performed continuously, and the loop gain is set sufficiently lower than that of the phase-locked loop.After that, when the equalization error becomes small, switching to intermittent control operation is performed. is there.
- a digital recording data reproducing apparatus comprises: a preamplifier for enhancing an output amplitude of a reproduction signal from a recording medium; and a predetermined frequency band of the enhanced signal.
- Analog equalizer that samples the equalized signal into multi-bit digital data asynchronously with the phase of the clock component included in the signal by means of a waveform generated by an oscillator and a clock generated by an oscillator.
- a transversal inode that performs partial response equalization on the signal, and a signal at a regular sampling phase from the partial response equalized signal.
- a high-order interpolation filter for reproducing by high-order interpolation, tap weight coefficient control means for adaptively controlling a weight coefficient of a tap of the transversal filter from the interpolation output signal so that an equalization error is minimized;
- a phase comparator for detecting a phase error from the interpolation output signal, a loop filter for smoothing the phase error signal, and a partial response type in which the interpolation output signal is equalized by the transversal filter.
- a maximum likelihood decoder that performs data demodulation by performing maximum likelihood decoding in response to the data, and demodulates the data by demodulating data by asynchronously sampling the signal sampled in a partial response, compensating for phase synchronization using a phase interpolation type digital phase locked loop, and demodulating data. Is performed.
- a digital recording data reproducing apparatus comprises: a preamplifier for enhancing an output amplitude of a reproduction signal from a recording medium; and a predetermined frequency band of the emphasized signal.
- the equalized signal is sampled into multi-bit digital data asynchronously with the phase of the clock component included in the signal by the waveform equalizing means for enhancing the frequency and the clock generated by the oscillator.
- Analog to digital conversion means offset correction means for reducing an offset component from the sampled signal, auto gain control means for adjusting the amplitude of the output signal to a required level, a transversal filter, It also has the function of the next interpolation filter, performs partial response equalization on the signal whose amplitude has been adjusted, and performs the partial response equalization on the signal.
- a phase interpolation type transversal filter for reproducing a signal at a normal sampling phase by higher-order interpolation, a phase comparator for detecting a phase error from the output signal, and smoothing the phase error signal to obtain phase information.
- a loop filter for obtaining the phase interpolation type transversal filter, wherein the phase information and the output signal of the phase interpolation type transversal filter are used to minimize an equalization error and reproduce a normal sampled signal.
- Tap weighting factor setting means for setting the weighting factor setting of the tap of the filter; and data demodulation by performing maximum likelihood decoding in accordance with a partial response type obtained by equalizing the interpolation output signal with the phase interpolation type transversal filter.
- Maximum likelihood decoder that performs partial response equalization and digital phase locked loop It is obtained so as to achieve in filter.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 12, wherein the tap weight coefficient setting unit is configured to: Having a filter coefficient for each phase, which is divided into The filter coefficient is updated, and based on the output signal of the phase interpolation type transversal filter, the filter coefficient for partial response equalization is updated so as to minimize the equalization error.
- the weight coefficient of the tap of the phase interpolation type transversal filter is set by superimposing the response equalization filter coefficient.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 12, wherein the tap weight coefficient setting unit is configured to: A provisional decision circuit for detecting an equalization target value corresponding to the partial response method based on the output signal of the versal filter, and an equalization for detecting an equalization error based on the equalization target value and the output signal of the higher-order interpolation filter An error detector, a correlator for detecting a correlation between the equalization error and an output signal of the higher-order interpolation filter, and a feedback gain adjustment for adjusting a feedback gain by multiplying an output of the correlator by the same number as a gain.
- a tap coefficient updating unit that adds the output of the feed-pack gain adjuster to the weight coefficient of each tap to update the tap coefficient; and a Nyquist characteristic
- a first register that stores each amplitude value corresponding to each tap when the channel rate is divided in the time direction, and Nyquist interpolation for each tap and each phase stored in the first register
- Tap coefficient convolution means for superimposing a coefficient and a weight coefficient of a tap for partial response equalization output from the tap coefficient update unit, and a signal on which the partial response equalization is performed is input to a delay element at a first stage.
- a plurality of delay elements having a unit delay time delay amount connected in series with each other, an input of a first-stage delay element among the plurality of unit delay elements, a connection point between the delay elements, and a final stage A multiplier provided corresponding to the output of the delay element, an adder for calculating the sum of the outputs of the multiplier and generating the output of the tap weight coefficient setting means, and a multiplier provided corresponding to the multiplier.
- a second register that is, the tap coefficient convolution means
- Register value updating means for updating the value of the second register based on the output; provided in correspondence with the second register; stored in the second register in accordance with output phase information of the loop filter; And a selector for selecting an amplitude value and outputting the selected amplitude value to the corresponding multiplier.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 12, wherein a frequency error is calculated from an output of the transversal filter.
- a frequency error detector that detects the frequency error, and a frequency control loop filter that smoothes the detected frequency error and provides the control signal to the oscillator as a control signal, wherein the frequency error is reduced to a predetermined value or less.
- the gain of the frequency control loop including the loop filter is reduced, the frequency lock control is shifted to the phase lock pull-in control, and when a predetermined number of synchronization patterns are detected, the phase control loop including the phase comparator is controlled.
- the loop response is reduced, and the partial response adaptation by the phase interpolation type tap weight coefficient control means is performed.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 12, wherein the tap weighting factor setting means includes: The feedback gain at the time of updating the phase control filter coefficient is set to be sufficiently larger than the feedback gain at the time of updating the partial response equalization filter coefficient. The filter coefficient is discretely updated.
- a digital recording data reproducing apparatus comprises: a preamplifier for enhancing an output amplitude of a reproduced signal from a recording medium; and a predetermined frequency band of the emphasized signal.
- Analog equalizer that samples the equalized signal into multi-bit digital data asynchronously with the phase of the clock component included in the signal by means of a waveform generated by an oscillator and a clock generated by an oscillator.
- Digital conversion means offset correction means for reducing an offset component from the sampled signal; auto gain control means for adjusting the amplitude of the output signal to a required level;
- a transversal filter that performs partial response equalization, and a signal at a normal sampling phase is extracted from the partial response equalized signal.
- a high-order interpolation filter that reproduces by the next interpolation, a tap weight coefficient control unit that adaptively controls a weight coefficient of the tap of the transversal filter from the interpolation output signal so that an equalization error is minimized,
- a phase comparator for detecting a phase error from the output signal; a loop filter for smoothing the phase error signal; and a type of a partial response obtained by equalizing the interpolation output signal with the transversal filter.
- a maximum likelihood decoder for performing data demodulation by performing maximum likelihood decoding, and as means for controlling the frequency of the output clock of the oscillator, detecting a period of a synchronization pattern included in recording data and detecting the synchronization pattern.
- Frequency control means that performs control based on the time width of the After being pulled into the vicinity, the control range of the loop filter is monitored, and before the phase control signal reaches the region where the phase synchronization cannot be controlled, the phase synchronization for performing clock frequency up / down control so as to return to the normal operation range.
- a maintenance means, and an oscillator control means for controlling the oscillator based on an output signal of the frequency control means and an output signal of the phase synchronization maintenance means.
- the digital recording data reproducing apparatus is the digital recording data reproducing apparatus according to claim 17, wherein the oscillator control means is configured to maintain the phase synchronization.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 18, wherein the cut-off frequency of the low-pass filter is And a cut-off frequency varying means for switching according to the reproduction speed of the digital recording data.
- the response characteristics suitable for each reproduction speed can be realized, the reproduction characteristics can be maintained even under the condition where the reproduction speed greatly changes.
- a digital recording data reproducing apparatus is a digital recording data reproducing apparatus according to any one of claims 11, 12, and 17.
- the offset correction means includes: an offset detection means for detecting an offset component of the sampled signal; a smoothing means for smoothing the detected offset component; And subtracting means for subtracting the sampled signal from the sampled signal.
- a digital recording data reproducing apparatus comprises: a preamplifier for enhancing an output amplitude of a reproduction signal from a recording medium; and a predetermined frequency band of the emphasized signal.
- Analog equalizer that samples the equalized signal into multi-bit digital data asynchronously with the phase of the clock component included in the signal by means of a waveform generated by an oscillator and a clock generated by an oscillator.
- Digital conversion means offset correction means for reducing an offset component from the sampled signal; auto gain control means for adjusting the amplitude of the output signal to a required level;
- a phase comparator for detecting a phase error from the interpolation output signal, a loop filter for smoothing the phase error signal, and a partial response type in which the interpolation output signal is equalized by the transversal filter.
- a maximum likelihood decoder that performs data demodulation by performing maximum likelihood decoding in response to the data, demodulates the data by demodulating the asynchronously sampled signal to partial response equalization, compensating for phase synchronization using a phase interpolation type digital phase locked loop, and demodulating data.
- the offset correction means refers to the output of the higher-order interpolation filter and performs offset correction. In which was to perform.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 21, wherein the offset correction unit is configured to: For a sampled signal at the position where the output signal of the filter crosses zero, a zero-cross amplitude output means that outputs a component in the amplitude direction, and for a sampled signal that is not at the zero-cross position, a fixed amount according to the sign polarity of the signal.
- Polarity value output means for outputting a value having a different polarity of an output signal; an offset correction loop filter for smoothing an output signal of the zero cross amplitude output means and an output signal of the polarity value output means; Offset removal means for directly removing the output signal of the analog / digital converter from the output signal of the analog / digital converter. In which was to so that.
- the digital recording data reproducing apparatus is the digital recording data reproducing apparatus according to claim 22, wherein the offset correction unit is configured to output the polarity value.
- the polarity of the code is mainly controlled during seek when the follow-up to the level fluctuation is more important than the accuracy of the reproduced signal, and the zero-cross amplitude is mainly controlled during the continuous data reproduction where the accuracy of the reproduced signal is required.
- This has the effect of making it possible to perform optimal offset correction according to the situation, and to contribute to the convergence of control, so that high-speed phase lock-in after seek is possible.
- the digital recording data reproducing apparatus according to the invention described in claim 24 of the present application is the digital recording data reproducing apparatus according to claim 22.
- the output value of the polarity value output means is zero.
- the digital recording data reproducing apparatus is the digital recording data reproducing apparatus according to claim 22, wherein the offset correction means performs a predetermined time.
- the digital recording data reproducing apparatus is the digital recording data reproducing apparatus according to any one of claims 11, 12, 17, and 21.
- the transversal filter includes a plurality of delay units each having a delay amount of a unit delay time, wherein the signal whose amplitude has been adjusted is input to the first-stage delay element.
- a plurality of delay elements a multiplier provided corresponding to an input of the first-stage delay element among the plurality of unit delay elements, a connection point between the delay elements, and an output of the last-stage delay element;
- An adder that takes the sum of the outputs of the multipliers and generates an output of the present filter, and realizes a required equalization characteristic by changing a weight coefficient input to the other input of the multiplier. Things. As a result, even if the characteristics of the reproduced signal are degraded due to tilt or the analogization of the analog signal is insufficient, not only will the error rate be reduced, but also the phase synchronization pull-in capability will be high and stable digital data reproduction will be possible. Has an effect that a configuration for performing partial response equalization can be realized.
- a digital recording data reproducing apparatus is a digital recording data reproducing apparatus according to any one of claims 11, 17, and 21.
- the high-order interpolation filter includes a plurality of delay elements having a delay amount of a unit delay time, wherein a signal subjected to the partial response equalization is input to a first-stage delay element, and the plurality of delay elements are connected in series with each other.
- a multiplier provided corresponding to the input of the first-stage delay element among the plurality of unit delay elements, the connection point between the delay elements, and the output of the last-stage delay element;
- An adder for taking the sum and generating the output of the present filter, and realizing required equalization characteristics by changing a weight coefficient input to the other input of the multiplier.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 27, wherein the high-order interpolation filter has a Nyquist characteristic.
- the interpolation is performed on the basis of the interpolation.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 27, wherein the high-order interpolation filter is A register for storing each amplitude value when the channel rate of the Nyquist characteristic is divided in the time direction; and a register provided for the register in accordance with the output phase information of the loop filter. A selector for selecting the amplitude value stored in the register and outputting the selected amplitude value to the corresponding multiplier.
- the high-order interpolation filter is A register for storing each amplitude value when the channel rate of the Nyquist characteristic is divided in the time direction; and a register provided for the register in accordance with the output phase information of the loop filter.
- a selector for selecting the amplitude value stored in the register and outputting the selected amplitude value to the corresponding multiplier.
- a digital recording data reproducing apparatus is a digital recording data reproducing device according to any one of claims 11, 17, and 21.
- the tap weight coefficient control means determines a weight coefficient of the transversal filter by a least mean square algorithm.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 30, wherein the tap weight coefficient control unit is configured to: A provisional decision circuit for detecting an equalization target value corresponding to the partial response method based on the output signal of the next interpolation filter, and detecting an equalization error based on the equalization target value and the output signal of the higher-order interpolation filter An equalization error detector, a correlator for detecting a correlation between the equalization error and an output signal of the higher-order interpolation filter, and a filter for adjusting a feedback gain by multiplying an output of the correlator by the same number as a gain. And a tap coefficient updating unit for adding the output of the feedback gain adjuster to the weight coefficient of each tap and updating the tap coefficient. .
- Transverser The weighting coefficient is set so as to realize the partial response equalization function to be performed by the filter.
- the digital recording data reproducing device is the digital recording data reproducing device according to claim 15, wherein the frequency error detector is the higher order A zero-cross length detector that detects an interval at which the output signal of the interpolation filter crosses a zero level; and a recording medium that detects whether or not this matches a predetermined synchronization pattern length based on a ratio of adjacent zero-cross lengths.
- a synchronization pattern length detector that obtains first cycle information reflecting the playback speed of the synchronization pattern, and an interval until the synchronization pattern is detected, and a second synchronization information based on this and a predetermined period.
- a synchronous pattern interval detector for detecting As a result, a stable phase-locked loop can be realized after shifting from the rough control to the phase-locked state, and a configuration for detecting a frequency error can be realized in a device that can prevent the control from falling into an uncontrollable state.
- FIG. 1 is a block diagram showing a configuration of a digital recording data reproducing apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a block diagram showing a configuration of the offset correction means 4 according to the first embodiment.
- FIG. 3 is an explanatory diagram showing a difference between a PR (3,4,4,3) equalization method realized by the transversal filter 6 in the first embodiment and a general binarization discrimination method. .
- FIG. 4 is a diagram showing frequency characteristics of various partial response systems realized by the transversal filter 6 in the first embodiment.
- FIG. 5 is an explanatory diagram of the Nyquist characteristic relating to the filter coefficient setting of the higher-order interpolation filter 7 according to the first embodiment.
- FIG. 6 is a block diagram showing a configuration of the higher-order interpolation filter 7 according to the first embodiment.
- FIG. 7 is a professional diagram showing the configuration of the tap weight coefficient control means 8 in the first embodiment.
- FIG. 7 is a professional diagram showing the configuration of the tap weight coefficient control means 8 in the first embodiment.
- FIG. 8 is an explanatory diagram of the principle of a Viterbi decoder which is one of the maximum likelihood decoders 12 in the first embodiment.
- FIG. 9 is a block diagram showing a configuration of frequency error detector 13 in the first embodiment.
- FIG. 10 is a block diagram showing a configuration of a digital recording data reproducing apparatus according to Embodiment 2 of the present invention.
- FIG. 11 is a block diagram showing a configuration of a phase interpolation type tap weight coefficient control means 33 according to the second embodiment.
- FIG. 12 is a flowchart illustrating a control method of frequency control, phase synchronization control, and LMS adaptation automatic equalization control according to the second embodiment.
- FIG. 13 is a block diagram showing a configuration of a digital recording data reproducing apparatus according to Embodiment 3 of the present invention.
- FIG. 14 is an explanatory diagram of the operation principle of the phase synchronization maintaining means 38 and the VCO control means 39 in the third embodiment.
- FIG. 15 is a block diagram showing the configuration of the VCO control means 39 according to the third embodiment, and an explanatory diagram of the principle of operation.
- FIG. 16 is a block diagram showing a configuration of the VCO control means 39 in the third embodiment, and an explanatory diagram of an operation principle for different reproduction speeds.
- FIG. 17 is a block diagram showing a configuration of a digital recording data reproducing apparatus according to Embodiment 4 of the present invention.
- FIG. 18 is a block diagram showing a configuration of the offset correction means 4 according to the fourth embodiment.
- FIG. 19 is an explanatory diagram of the operation principle of the offset correction means 4 according to the fourth embodiment.
- FIG. 20 is a block diagram showing a configuration of the offset correction means 4 according to the fourth embodiment.
- FIG. 21 is a block diagram showing a configuration of the offset correction means 4 according to the fourth embodiment.
- FIG. 22 is a block diagram showing a configuration of the offset correction means 4 according to the fourth embodiment.
- FIG. 23 is a block diagram showing a configuration of a conventional optical disc reproducing apparatus.
- FIG. 24 is a diagram showing recording data of a conventional optical disc reproducing apparatus and an output signal waveform in each function block.
- a signal obtained by performing a partial response equalization by a transversal filter using a non-synchronous clock for sampling by an analog-to-digital converter and a signal at a normal sampling phase by a high-order interpolation filter is used. Is reproduced, a phase error is detected based on the output signal, and a digital phase locked loop for controlling the filter coefficient of the higher-order interpolation filter so as to reduce the phase error is configured.
- Embodiment 1 corresponding to a playback apparatus will be described with reference to FIGS. 1 to 9.
- FIG. 1 after the output amplitude of an optical disc reproduction signal obtained by a reproduction means (optical pickup or the like) not shown is emphasized by a preamplifier 1, correction is made by a waveform equalization means 2 to emphasize a high frequency band.
- the waveform equalizing means 2 is composed of, for example, a filter such as a higher-order equiripple filter that can set the boost amount and the cutoff frequency arbitrarily.
- the output signal of the waveform equalizing means 2 is sampled into a multi-bit digital signal by an analog-to-digital converter 3 as a means for converting an analog signal to a digital signal.
- a clock that is generated by the oscillator 15 and that is asynchronous with the clock component of the reproduction signal is used.
- the offset component contained in the reproduced digital signal is corrected by inputting the multi-bit digital signal sampled by the analog / digital converter 3 to the offset correcting means 4.
- the offset correction means 4 may have a configuration as shown in FIG. 2, for example.
- FIG. 2 shows an offset detecting means 16 for detecting an offset component of the reproduced digital signal, a smoothing means 17 for smoothing the offset signal detected thereby, and an output of the smoothing means 17. It comprises a subtraction means 18 for subtracting a signal from a reproduced digital signal.
- the auto gain control 5 may be, for example, a type that detects an envelope of a signal waveform and controls the difference between an arbitrary set value and the envelope signal to be zero.
- the output signal of the auto gain control 5 is input to the transversal filter 6 to perform partial response equalization.
- the Persian noiseless equalization is performed, for example, in a DVD-ROM (Read Only Memory) capable of digitally recording 4.7 Gbytes on one side, as shown in Fig. 3 (c).
- the PR (3, 4, 4, 3) method is used in which the waveform amplitude after equalization is divided into five values (0, 4 XA, 7 XA, — 4 XA, -7 XA).
- digital data demodulation has been performed from a waveform equalized output signal as shown in FIG. 3 (a) by binarization discrimination using a slice level. Also, in the case of sampling, as shown in FIG. 3 (b), sampling was performed, and the multi-bit digital signal was subjected to binarization discrimination using slice levels.
- the PR (3, 4, 4, 3) method is a feature (3 + 4 * D +) in which sampled data at four different times are added at a ratio of 3: 4: 4: 3. 4 * D 2 + 3 * D4), and adds the characteristics of a low-pass filter to the reproduced signal as shown in FIG.
- the MTF indicates the optical reproduction characteristics of the DVD-ROM, and it can be said that the closer to this frequency characteristic, the more advantageous the partial response method is.
- the method is not limited to the method, and there is no problem if another method is used as long as it can achieve the required performance.
- the transversal filter 6 is a FIR (Finite Impulse response Filter) filter composed of finite taps, for example.
- the equalization characteristic by the FIR filter is realized by changing the weight coefficient of the tap.
- the transversal signal is converted into a signal at the normal sampling phase by the high-order interpolation filter 7 from the signal obtained from the transversal filter.
- the high-order interpolation filter 7 may be based on, for example, Nyquist interpolation characteristics as shown in FIG.
- each amplitude value is stored in a register, and the phase indicated by that is indicated according to the phase control information.
- the phase interpolation is performed while switching the register to be set so as to set the coefficient.
- the high-order interpolation filter 7 connects the delay elements 19a to 19f to the series, and taps extracted therefrom, that is, the input of the delay elements 19a to 19f and the delay element.
- Multiplying elements 20 a to 20 f and 20 g that multiply the output of 19 f by tap coefficients S 1 to S 6 and S 7, and multiplying elements 20 a to 20 f or 20 f and 20 g An FIR filter composed of an adding means 21 for adding outputs may be used.
- the filter coefficients held in the registers 22a to 22g as shown in FIG. 6 are obtained.
- Selector S 1 while switching from 23 a to 23 g The tap coefficients from S to S7 are set.
- the coefficients of the registers 22a to 22g are obtained by dividing the Nyquist characteristic value for each phase in FIG. 5 by N. For example, as shown in FIG. The area is divided and areas 1 to 7 are stored in advance so as to correspond to each tap of the FIR filter shown in FIG.
- the filter coefficient at the phase of e is set as the tap coefficient of S1 to S7.
- the output signal of the high-order interpolation filter 7 is input to tap weight coefficient control means 8, and adaptively controls the weight coefficient of the tap of the transversal filter 6 so as to minimize the equalization error.
- the tap weight coefficient control means 8 may use, for example, a least mean square algorithm as shown in FIG. That is, the temporary decision circuit 24 detects an equalization target value corresponding to the partial response method from the output signal of the high-order interpolation filter 7, and subtracts the output signal of the high-order interpolation filter 7 from the equalization target value.
- An equalization error detector 25 for detecting an equalization error, a correlator 26 for calculating a correlation between an output signal of the equalization error detector 25 and an output signal of the high-order interpolation filter 7, and a correlator 2 It is composed of a feedback gain adjuster 27 that adjusts the feedback gain by multiplying the output of 6 by the same number as the gain, and a tap coefficient updater 28 that adds the output to the weight coefficient of each tap and updates the tap coefficient. Is what is done.
- phase comparator 9 for detecting a phase error from the output signal of the high-order interpolation filter 7, a loop filter 10 for smoothing a phase error signal output from the phase comparator 9, and an output
- a digital phase locked loop 11 is formed by a feedback loop that controls a filter coefficient of the high-order intercept filter 7 using a signal as phase control information.
- the maximum likelihood decoder 1 2 is, for example, a Viterbi decoder No. may be used.
- the Viterbi decoder calculates the probability according to the law of correlation of the intentionally added code based on the type of the partial response, and reproduces a likely sequence. For example, when the applied partial response type is PR (3, 4, 4, 3), the state changes based on the state transition diagram as shown in Fig. 8 (a). This takes into account, in particular, the 8 -16 modulation code used in DVDs, and also relates to the fact that the run-length length is limited to 2, so that the reproduced sequence S 0 It can be expressed by six state transitions up to S5.
- XZY indicates that X represents the transition of the recording code, and Y represents the signal amplitude at that time.
- One state is represented by three different time codes. For example, in the state transition from S 4 “1 10” to S 3 “100”, the code “0” is added to “1 10”. Shifting to the left means that the leftmost "1" disappears and state S3 becomes "100".
- the change over time is represented by a trellis diagram as shown in Fig. 8 (b). Therefore, the probabilistic length of each path 1 k ab (hereinafter referred to as the branch metric) is calculated, and when transitioning to each state, the branch metric is added.
- k represents a temporal transition
- a b represents a branch metric at the transition from the state Sa to S b.
- the added value in each state of the branch metric is called a metric, and the path with the minimum metric is used as a surviving path and sequentially output to be demodulated into binary digital data. is there. That is, if demodulation is performed according to the recording code in FIG. 8 (b), the path indicated by the solid line is the surviving path.
- the means for controlling the sampling clock of the analog / digital converter 3 detects the pattern length of the synchronization pattern or the interval at which the synchronization pattern occurs from the output signal of the high-order interpolation filter 7 and converts it into period information.
- a frequency error detector 13 as a means for outputting a frequency error signal
- a frequency control loop filter 14 as a means for smoothing the frequency error signal output from the frequency error detector 13, and an analog / digital converter. This is realized by a frequency control loop composed of an oscillator 15 which supplies the converter 3 with power.
- the frequency error detector 13 may have, for example, a configuration as shown in FIG.
- the zero-cross length detection means configured by means for holding in a register.
- the ratio of adjacent zero-cross lengths in the period established by the frame counter 30 composed of means for counting a specific period of one frame or more using the output of the unit 29 is the ratio of the synchronous pattern, For example, in the DVD-ROM, only when 14: 4 is satisfied, the synchronous pattern length detector 31 composed of means for detecting the maximum value obtained by adding the count value and holding it in a register is used.
- Period information 1 that is inversely proportional to the linear velocity period of the reproduced digital data is obtained.
- the synchronization pattern length detector 31 detects the synchronization pattern in order to further approximate the frequency of the clock component of the recovered clock.
- a pattern flag is output, and a period in which a synchronous pattern is generated is detected by a synchronous pattern interval detector 32 constituted by means for counting an interval until the next synchronous pattern flag is detected.
- a difference from 1488 T (where T indicates one channel bit) is obtained as period information 2. With these period information 1 and period information 2, the oscillation clock of the oscillator 15 is controlled up to the frequency region where phase synchronization is possible.
- a digitally recorded data reproducing apparatus characterized in that such asynchronously sampled signals are subjected to partial response equalization, phase synchronization is compensated by a phase complementary digital phase locked loop, and data demodulation is performed. Even under conditions where the characteristics of the reproduced signal are degraded due to tilt and analog equalization is insufficient, phase error information is detected after partial response equalization to reduce jitter in the phase locked loop and obtain an optimal partial response equalized signal. Because it can be reproduced, it not only leads to a lower error rate, but also has a high phase synchronization pull-in capability, enabling stable digital recorded data reproduction.
- phase synchronization is compensated by a phase interpolation type digital phase locked loop, and data demodulation is performed.
- phase error information is detected after partial response equalization, which reduces jitter in the phase locked loop and optimizes the partial response equalization signal. Therefore, it is possible to realize a digital recording data reproducing apparatus that not only leads to a reduction in error rate but also has a high phase synchronization pull-in capability and enables stable digital recording data reproduction.
- FIG. 10 after an optical disc reproduction signal obtained by a reproduction means (optical pickup or the like) not shown is emphasized by a preamplifier 1, an output amplitude is enhanced, and a waveform equalization means 2 is corrected to emphasize a high band.
- the waveform equalizing means 2 is composed of a filter, such as a high-order equiripple filter, which can arbitrarily set a boost amount and a cutoff frequency.
- the output signal of the waveform equalizing means 2 is sampled into a multi-bit digital signal by an analog / digital converter 3 as means for converting an analog signal into a digital signal.
- a clock generated by the oscillator 15 and asynchronous with the clock component of the reproduced signal is used.
- the offset correction means 4 By inputting the multi-bit digital signal sampled by the analog / digital converter 3 to the offset correction means 4, the offset component contained in the reproduced digital signal is corrected.
- the offset correction means 4 may have a configuration as shown in FIG. 2, for example. That is, an offset detecting means 16 for detecting an offset component of the reproduced digital signal, a smoothing means 17 for smoothing the offset signal detected thereby, and an output signal of the smoothing means 17 It comprises a subtraction means 18 for subtracting from a signal.
- the output signal of the offset correction means 4 is input to the auto gain control 5, whereby the amplitude of the reproduced digital signal is adjusted to an arbitrary value.
- Auto gain The control 5 may detect the envelope of the signal waveform, for example, and control the difference between an arbitrary set value and the envelope signal to be zero.
- the output signal of the auto gain control 5 is input to the transversal filter 6, and phase interpolation and partial response equalization for achieving phase synchronization are performed.
- the partial response equalization may use the PR (3, 4, 4, 3) method described in the first embodiment.
- the transversal filter 6 is composed of finite taps.
- the transversal filter 6 may be a FIR (Finite Impulse response Filter) filter as shown in FIG.
- the equalization characteristic and the phase interpolation characteristic by the FIR filter are realized by changing the weight coefficient of the tap.
- a phase interpolation type tap weight coefficient control means 33 is provided as a means for controlling the weight coefficient of the tap. That is, the transversal filter 6 includes a phase interpolation type tap weight coefficient control means 33 as means for controlling the weight coefficient of the tap based on the equalized output signal so as to minimize the partial response equalization error.
- An adaptive control loop a phase comparator 9 for detecting a phase error of an output of the transversal filter 6, a loop filter 10 for smoothing a phase error signal output from the phase comparator 9, A phase interpolation type tap weight coefficient control means 33, and a digital phase as means for controlling a filter coefficient of the phase interpolation type tap weight coefficient control means 33, using an output signal of the loop filter 10 as phase control information. It is controlled by two types of control loops:
- the maximum likelihood decoder 12 may be, for example, a Viterbi decoder.
- the Viterbi decoder performs probability calculation according to the type of partial response and the law of correlation of intentionally added codes, and reproduces a likely sequence. For example, PR (3, 4) , 4, 3) ML method, that is, a PRML method in which the applied partial response is PR (3, 4, 4, 3).
- the phase interpolation type tap weight coefficient control means 33 is, for example, as shown in FIG. It may have such a configuration. That is, when performing the phase interpolation control, based on the phase control information which is the output signal of the loop filter 10, the filter coefficients held in the registers 22a to 22g as shown in FIG. While switching by the selectors 23a to 23g, the tap coefficients of the IR filters 31 to 37 are set as shown in FIG.
- the coefficients of the registers 22a to 22g are determined by both coefficient control by partial response adaptive automatic equalization and coefficient control by Nyquist phase interpolation control.
- the coefficient control by the partial response adaptive automatic equalization may be, for example, a method using a least mean square algorithm as shown in FIG. That is, the provisional decision circuit 24 detects an equalization target value corresponding to the partial response method from the output signal of the transversal filter 6, and subtracts the equalization target value from the output signal of the transversal filter 6 for equalization.
- An equalization error detector 25 for detecting an error
- a correlator 26 for calculating a correlation between an output signal of the equalization error detector 25 and an output signal of the transversal filter 6, and an output of the correlator 26
- a feedback gain adjuster 27 as a means for adjusting the feedback gain by multiplying the output gain by the same number as the gain
- a tap coefficient updater 2 as a means for adding the output to the weight coefficient of each tap and updating the tap coefficient.
- the Nyquist characteristic is divided into 8 from a to h, and areas 1 to 7 are further divided into taps of the FIR filter shown in FIG. And stored in register 35.
- Nyquist interpolation coefficients E m to D m for each tap and each phase stored in register 35 in FIG. 11 (m is equivalent to tap number and area number), tap
- the weight coefficient of the tap for partial response equalization which is the output signal of the coefficient update unit 28, is superimposed by the tap coefficient convolution means 34, and each of the registers 22a to 22g is registered by the register value update means 36.
- the means for controlling the sampling clock of the analog-to-digital converter 3 is based on the output signal of the transversal filter 6 and the pattern length of the synchronization pattern.
- a frequency error detector 13 as a means for detecting the interval at which the synchronization pattern occurs and converting it into period information to output a frequency error signal, and a frequency error output from the frequency error detector 13
- a frequency control loop constituted by a frequency control loop filter 14 as a means for smoothing a signal and an oscillator 15 for supplying a power to the analog-digital converter 3.
- the frequency error detector 13 may have, for example, a configuration as shown in FIG. That is, a zero-cross length detector constituted by means for continuously detecting the position where the signal crosses the zero level from the output signal of the transversal filter 6 and counting the number of samples between adjacent zero-crosses and holding it in a register. 29
- the ratio of adjacent zero-cross lengths in the period established by the frame counter 30 composed of means for counting a specific period of one frame or more using the output of 9 is the ratio of the synchronization pattern, For example, in the DVD-ROM, only when the ratio of 14: 4 is satisfied, the synchronous pattern length detector 31 configured by detecting the maximum value obtained by adding the count value and holding it in a register is used.
- Period information 1 that is inversely proportional to the linear velocity period of the reproduced digital data is obtained.
- the synchronization pattern length detector 31 determines that the pattern is a synchronization pattern in order to further approach the frequency of the clock component of the reproduction clock.
- a synchronization pattern flag is output at the position, and a synchronization pattern interval detector 32 constituted by means for counting an interval until the next synchronization pattern flag is detected detects a period in which a synchronization pattern is generated.
- the difference from 148 T (where T indicates one channel bit) is obtained as period information 2.
- the period information 1 and the period information 2 control the oscillation clock of the oscillator 15 to a frequency region in which phase synchronization is possible.
- Digital recording characterized by realizing partial response equalization and phase interpolation type digital phase-locked loop of such asynchronously sampled signal by one system of transversal filter, and performing data demodulation.
- the transversal filter and the high-order interpolation filter which account for a large proportion of the entire circuit scale, can be shared, so that the circuit scale can be reduced and power consumption can be reduced, especially during high-speed reproduction.
- Buoy for phase control The means for setting the filter coefficient and the means for setting the weight coefficient of the tap for partial response equalization are operated independently, so that both partial response equalization and data reproduction interpolation at the normal sampling phase are performed. Accurate and efficient control is possible without impairing the characteristics.
- the circuit scale can be reduced, and especially in high-speed playback. Power consumption in the system.
- the control method of the frequency control, phase synchronization control, and partial response adaptive automatic control in the second embodiment may be, for example, as shown in the flowchart of FIG.
- the control is started, as a first step, the frequency is pulled in by the frequency control loop (step 101). If the deviation between the frequency of the clock component of the resulting reproduced signal and the clock frequency generated from the oscillator 15 is within ⁇ A% (step 102), the phase synchronization pull-in control of the second stage is performed. (Step 103), and switches the loop gain in the frequency acquisition to the low gain mode. If the frequency deviation is not within ⁇ A%, continue the frequency pull-in control.
- Step 104 the third-stage LMS algorithm PR adaptive automatic equalization control (Step 105), and switches the loop gain in the phase synchronization pull-in to the low gain mode. If the synchronization pattern cannot be confirmed for a certain number of consecutive times, the phase synchronization pull-in control is continued.
- the fourth stage interval control PR The process shifts to the adaptive automatic equalization control, and if not within ⁇ B%, the LMS algorithm PR adaptive automatic equalization control is continuously performed in the low gain mode (step 107).
- the interval control type PR adaptive automatic equalization control does not sequentially feed back the weight coefficient of the tap for partial response equalization, but has a correlation at each tap for a certain fixed period. Control that cumulatively adds the equalization error amount to the tap weighting coefficients discretely Is the way.
- the loop gain of the LMS algorithm PR adaptive automatic equalization control and the loop gain of the inter-control type PR adaptive automatic equalization control must be sufficiently lower than the loop gain of the phase synchronization pull-in control. Does not occur, and stable control is possible.
- the optical disc reproduction signal obtained by a reproducing means (optical pickup or the like) not shown is emphasized by a preamplifier 1 to enhance the output amplitude, and then corrected by a waveform equalizing means 2 to emphasize a high band.
- the waveform equalizing means 2 is composed of a filter capable of arbitrarily setting a boost amount and a cutoff frequency. For example, higher-order ripple filters.
- the output signal of the waveform equalizing means 2 is sampled into a multi-bit digital signal by an analog / digital converter 3 as means for converting an analog signal into a digital signal.
- a clock generated by the VCO 40 and asynchronous with the clock component of the playback signal is used.
- the offset correcting means 4 By inputting the sampled multi-bit digital signal to the offset correcting means 4, the offset component included in the reproduced digital signal is corrected.
- the offset correction means 4 may have a configuration as shown in FIG. 2, for example. That is, an offset detecting means 16 for detecting an offset component of the reproduced digital signal, and a smoothing means for smoothing the offset signal detected thereby. It comprises a stage 17 and subtraction means 18 for subtracting the output signal of the smoothing means 17 from the reproduced digital signal.
- the output signal of the offset correction means 4 is input to the auto gain control 5, whereby the amplitude of the reproduced digital signal is adjusted to an arbitrary value.
- the auto gain control 5 may be one that detects the envelope of the signal waveform and controls the difference between an arbitrary set value and the envelope signal to be zero.
- the output signal of the auto gain control 5 is input to the transversal filter 6 to perform partial response equalization.
- the partial response equalization is performed, for example, in a DVD-ROM (Read Only Memory) capable of digital recording of 4.7 Gbytes in one layer on one side, as shown in FIG. 3 (c).
- the PR (3,4,4,3) method is used so that the waveform amplitude after conversion is divided into five values (0, 4 XA, 7 XA, -4 XA, and 17 XA).
- partial response types other than the PR (3, 4, 4, 3) method. However, if not only limited to a specific method but also a method that meets the performance, other partial response types can be used. There is no problem with using the method.
- the likelihood is certain by using the correlation of the added data.
- PRML signal processing which is advantageous for high-density reproduction in the linear recording direction, is realized.
- the transversal filter 6 is a FIR (Finite Impulse response Filter) filter composed of finite taps, for example.
- the equalization characteristic by the FIR filter is realized by changing the weight coefficient of the tap.
- the signal subjected to the partial response equalization by the transversal filter 6 is converted by the high-order interpolation filter 7 into a signal having a regular sampling phase.
- the high-order interpolation filter 7 may be based on, for example, Nyquist interpolation characteristics as shown in FIG. In the Nyquist characteristics shown in Fig. 5, When the amplitude (IT) is divided by N in the time direction, each amplitude value is stored in a register, and according to the phase control information, the register to be selected is switched so that the coefficient of the phase indicated by the phase control information is set. Perform phase interpolation. As a result, the reproduction signal sampled asynchronously is converted into a reproduction equalization signal equivalent to the normal sampling phase.
- the high-order interpolation filter 7 is composed of a delay element 19a to a delay element 19f, a multiplication element 20a to 20g, and an FIR It may be.
- the filter coefficients held in the registers 22a to 22g as shown in FIG. 6 are obtained.
- the tap coefficients from S1 to S7 are set while switching with the selectors 23a to 23g.
- the coefficients of the registers 22a to 22g are obtained by dividing the Nyquist characteristic value for each phase in FIG. 5 into N, for example, as shown in FIG.
- Areas 7 to 7 are stored corresponding to each tap of the FIR filter shown in Fig. 6. For example, if the current phase control information obtained from the loop filter 10 is a sampling phase that differs by 180 ° from the normal phase, the “na” in areas 1 to 7 shown in FIG.
- the filter coefficient at the phase of e is set as the tap coefficient of S1 to S7.
- the output signal of the high-order interpolation filter 7 is input to tap weight coefficient control means 8 and adaptively controls the weight coefficient of the tap of the transversal filter 6 so as to minimize the equalization error.
- the tap weight coefficient control means 8 may use, for example, a least mean square algorithm as shown in FIG. That is, the temporary decision circuit 24 detects an equalization target value corresponding to the partial response method from the output signal of the high-order interpolation filter 7, and subtracts the output signal of the high-order interpolation filter 7 from the equalization target value.
- An equalization error detector 25 for detecting an equalization error
- a correlator 26 for calculating a correlation between an output signal of the equalization error detector 25 and an output signal of the high-order interpolation filter 7, and a correlator.
- a feedback gain adjuster 27 as a means for adjusting the feedback gain by multiplying by the same number as the above, and a tap coefficient updating unit 2 8 as a means for adding the output to the weight coefficient of each tap and updating the tap coefficient It is composed of
- phase comparator 9 for detecting a phase error from the output signal of the high-order interpolation filter 7, a loop filter 10 for smoothing a phase error signal output from the phase comparator 9, and an output
- a digital phase locked loop 11 is formed by a feedback loop that controls the filter coefficient of the higher-order interpolation filter 7 using the signal as phase control information.
- the maximum likelihood decoder 12 performs decoding in accordance with the type of the partial response, using the partial response equalized waveform at the normal phase output by a series of operations.
- the maximum likelihood decoder 12 may be, for example, a Viterbi decoder.
- the Viterbi decoder performs probability calculation according to the type of partial response and the law of correlation of intentionally added codes, and reproduces a likely sequence.
- the means for controlling the sampling clock of the analog-to-digital converter 3 detects the pattern length of the synchronization pattern or the interval at which the synchronization pattern occurs from the output signal of the high-order interpolation filter 7 and converts it into period information.
- Frequency error signal 13 as a means for outputting a frequency error signal
- a frequency control loop filter 14 as a means for smoothing the frequency error signal output from the frequency error detector 13.
- the frequency control means 37 which controls the rough frequency control, and monitors the phase control information output from the loop filter 10 after the frequency and the frequency of the clock component included in the reproduced signal are pulled in close to each other. Before the phase control signal reaches the phase synchronization uncontrollable region, the clock frequency is increased or decreased so as to return to the normal operation range.
- phase synchronization maintaining means 38 for controlling and the rough control signal of frequency and the up / down control signal, it controls the oscillation frequency of VCO 40 that supplies the analog to digital converter 3 This is realized by a frequency control loop constituted by the VCO control means 39.
- the frequency control means 37 may be, for example, one obtained by connecting a frequency control loop filter 14 to the configuration shown in FIG. That is, higher-order interpolation
- the output of the zero cross length detector 29 composed of means for continuously detecting the position where the signal crosses the zero level from the output signal of the buinoleta 7, counting the number of samples between adjacent zero crosses, and holding in a register ,
- the ratio of adjacent zero-cross lengths in the period established by the frame counter 30 composed of means for counting a specific period of one or more frames is the ratio of the synchronization pattern, for example, DVD-ROM.
- the synchronous pattern length detector 31 composed of means for detecting the maximum value obtained by adding the count value and holding it in the register is used to reproduce the digital data line Obtain period information 1 that is inversely proportional to the speed period.
- the synchronization pattern length detector 31 detects the synchronization pattern flag at the position determined to be a synchronization pattern. Then, the synchronization pattern interval detector 32 constituted by means for counting the interval until the next synchronization pattern flag is detected detects the period in which the synchronization pattern is generated.
- the phase synchronization maintaining means 38 may be based on, for example, a control method as shown in FIG.
- a control method as shown in FIG.
- the frequency of the oscillation clock of the VCO is pulled down to the frequency region where the phase can be synchronized by the frequency control means 37
- the phase which is the output signal of the loop filter 10 as shown in FIG. 14 (a) is obtained.
- an arbitrary phase maintenance level is set in both the leading direction and the lagging direction of the phase, and if the phase control signal exceeds the phase maintaining level in the leading direction, it is increased.
- a down control signal is supplied to the VCO control means 39.
- the frequency of the oscillation clock of the VCO 40 is controlled so that it stays within the phase-synchronizable region, enabling smooth phase-synchronization control without phase discontinuities.
- the control of the oscillation frequency of VC ⁇ 40 draws a frequency curve as shown in FIG. 14 (b).
- the frequency of the asynchronous clock when sampling the reproduced signal can always be maintained within the controllable range of the digital phase locked loop. Therefore, there is no discontinuity during phase synchronization control, and not only stable digital recording data reproduction is possible, but also frequency control and phase control can be considered separately.
- the means can also be realized with a simple configuration. In particular, analog circuits such as VCOs are subject to aging and performance variations, so a compensation circuit is required.However, using the control method of the present invention simplifies the circuit configuration. This is effective for cost reduction and low power consumption.
- the transversal filter 6 the high-order interpolation filter 7, the tap weighting factor control means 8, the phase comparator 9, and the loop filter 10
- the transversal filter 6, the phase comparator 9 The loop filter 10 and the phase interpolation type tap weight coefficient control means 33 may be used.
- the VCO control means 39 may be, for example, as shown in FIG. 15 (a). That is, the frequency rough control signal output from the frequency control means 37 and the frequency up / down control signal output from the phase synchronization maintaining means 38 are input to the delta-sigma modulator 41, respectively. After modulating in the time direction using sampling, the output is input to a digital-to-analog converter 42 to convert the digital control signal into a voltage value. The converted voltage value is input to a low-pass filter 43 as a means for smoothing, and is re-shaped to a smooth VC ⁇ control voltage, whereby the oscillation frequency originally possessed by the VCO 40 is obtained. This enables finer control than the minimum control amount. At this time, the relationship between the V CO control voltage and the output of the delta-sigma modulator 41 is as shown in FIG. 15 (b).
- the 0 control means 39 may be, for example, as shown in FIG. 16 (a).
- the frequency rough control signal output from the frequency control means 37 and the frequency up / down control signal output from the phase synchronization maintaining means 38 are input to the delta-sigma modulator 41, respectively.
- the output is input to a digital-to-analog converter 42 to convert the digital control signal into a voltage value.
- the converted voltage value is input to a low-pass filter 43 as a means for smoothing, and is re-shaped to a smooth VCO control voltage. Finer control than the minimum control amount is possible.
- the cut-off frequency setting means as means for switching the cut-off frequency of the low-pass filter 43 in accordance with the amount of change in the reproduction speed, such as the double speed mode for reproduction or the difference between the inner and outer circumferences during disc reproduction. It has.
- the cutoff frequency can be changed in conjunction with the frequency of the reproduction clock, the performance will be further improved.
- the relationship between the VCO control voltage and the output of the delta-sigma modulator 41 is as shown in FIG. 16 (b).
- the cutoff frequency of the low-pass filter is fixed, normal reproduction can be performed at 2x speed, but if the reproduction channel rate becomes 1x speed, that is, the reproduction channel rate becomes twice as long, the VCO control voltage will be disturbed .
- smooth control can be maintained as shown in FIG. 16 (b). The same effect can be obtained for the difference between the inner and outer circumferences of the playback speed, which exists in the CAV playback system, which is a system for keeping the spindle motor rotation speed constant during disk playback.
- the waveform equalizing means 2 is composed of, for example, a filter such as a high-order equiripple filter, which can arbitrarily set a boost amount and a cutoff frequency.
- the output signal of the waveform equalizing means 2 is sampled into a multi-bit digital signal by an analog / digital converter 3 as means for converting an analog signal into a digital signal.
- a clock generated by the oscillator 15 and asynchronous with the clock component of the reproduced signal is used.
- the offset correcting means 4 By inputting the sampled multi-bit digital signal and the output signal of the high-order interpolation filter 7 to the offset correcting means 4, the offset component contained in the reproduced digital signal is corrected.
- the offset correction means 4 may have, for example, a configuration as shown in FIG. That is, from the output signal of the high-order interpolation filter 7, a position where the signal crosses zero level is detected, and a zero-cross position detecting means 45 having a function of outputting a zero-cross flag is provided.
- the zero-cross function configured to output the amplitude difference (E in the figure) between the true DC level and the false DC level shown in Fig.
- Amplitude output means 46 and, for a sampled signal not at the zero cross position, a polarity value output means 4 7 having a function of outputting a certain value X or one X according to the polarity of the signal
- the selector 48 which is a means for switching and outputting by the zero-cross flag
- the offset correction loop filter 4 9 is input to the offset correction loop filter 4 9 for smoothing.
- the output signal of the offset correction loop filter 49 is directly subtracted from the output signal of the analog / digital converter 3 by the subtraction means 18, The offset correction is performed.
- the offset correction means 4 as shown in FIG. 18 the offset error amount can be developed in the time direction by appropriately selecting the value of X shown in FIG. This makes it possible to detect a more accurate offset error signal, which cannot be obtained only by the polarity of the signal.
- the output signal of the offset correction means 4 is input to the auto gain control 5 so that the amplitude of the reproduced digital signal is adjusted to an arbitrary value.
- the auto gain control 5 may be, for example, a type that detects the envelope of a signal waveform and controls the difference between an arbitrary set value and the envelope signal to be zero.
- the output signal of the auto gain control 5 is input to the transversal filter 6 to perform partial response equalization.
- the partial response equalization is performed, for example, in a DVD-ROM (Read Only Memory) capable of digital recording of 4.7 Gbytes in one layer on one side, as shown in FIG. 3 (c).
- the PR (3,4,4,3) method shall be used so that the waveform amplitude after conversion is divided into five values (0, 4XA, 7XA, -4XA, -7XA).
- partial response types other than the PR (3, 4, 4, 3) method. However, if not only a specific method but also a method that meets the performance can be realized, other methods will be used. There is no problem using the above method.
- the transversal filter 6 is composed of a finite tap, for example, a FIR (Finite Impulse response Filter) filter. The equalization characteristics of this FIR filter are realized by varying the tap weighting coefficients.
- FIR Finite Impulse response Filter
- the signal that has been subjected to partial response equalization by the transversal filter 6 is converted by the high-order interpolation filter 7 into a signal at a regular sampling phase.
- the higher-order interpolation filter 7 may be based on Nyquist interpolation characteristics as shown in FIG. 5, for example.
- Nyquist characteristic as shown in Fig. 5 when the channel rate (1T) is divided into N in the time direction, each amplitude value is stored in a register, and the phase indicated by that is indicated according to the phase control information.
- the phase interpolation is performed while switching the register to be selected so as to set the coefficient.
- the reproduced signal sampled asynchronously is converted into a reproduced equalized signal equivalent to the normal sampling phase.
- the high-order interpolation filter 7 is composed of a delay element 19a to a delay element 19f, a multiplication element 20a to 20g, and an FIR It may be.
- the filter coefficients held in the registers 22a to 22g as shown in FIG. 6 are obtained.
- the tap coefficients from S1 to S7 are set while switching with the selectors 23a to 23g.
- the coefficients of the registers 22 a to 22 g are obtained by dividing the Nyquist characteristic value for each phase in FIG. 5 into N, for example, as shown in FIG. Area 7 is stored corresponding to each tap of the FIR filter shown in Fig. 6. For example, if the current phase control information obtained from the loop filter 10 is a sampling phase that differs by 180 ° from the normal phase, the “reference” from areas 1 to 7 shown in FIG.
- the filter coefficient at the phase of e is set as the tap coefficient of S1 to S7.
- the output signal of the high-order interpolation filter 7 is input to the tap weight coefficient control means 8.
- the weight coefficient of the tap of the transversal filter 6 is adaptively controlled so as to minimize the equalization error.
- the tap weight coefficient control means 8 may use, for example, a least mean square algorithm as shown in FIG. That is, the temporary decision circuit 24 detects an equalization target value corresponding to the partial response method from the output signal of the high-order interpolation filter 7, and subtracts the output signal of the high-order interpolation filter 7 from the equalization target value.
- An equalization error detector 25 for detecting an equalization error
- a correlator 26 for calculating a correlation between an output signal of the equalization error detector 25 and an output signal of the high-order interpolation filter 7, and a correlator.
- a feedback gain adjuster 27 as a means for adjusting the feedback gain by multiplying the output of 26 by the same number as the gain, and a means for updating the tap coefficient by adding the output to the weight coefficient of each tap.
- a tap coefficient updating unit 28 for example, a least mean square algorithm as shown in FIG. That is, the temporary decision circuit 24 detects an equalization target value corresponding to the partial response method from the output signal of the high-order
- phase comparator 9 for detecting a phase error from the output signal of the high-order interpolation filter 7, a loop filter 10 for smoothing a phase error signal output from the phase comparator 9, and an output
- a digital phase locked loop 11 is formed by a feedback loop that controls the filter coefficient of the higher-order interpolation filter 7 using the signal as phase control information.
- the maximum likelihood decoder 12 performs decoding in accordance with the type of the partial response, using the partial response equalized waveform at the normal phase output by a series of operations.
- the maximum likelihood decoder 12 may be, for example, a Viterbi decoder.
- the Viterbi decoder performs probability calculation according to the type of partial response and the law of correlation of intentionally added codes, and reproduces a likely sequence.
- the means for controlling the sampling rate of the analog-to-digital converter 3 detects the pattern length of the synchronization pattern or the interval at which the synchronization pattern occurs from the output signal of the high-order interpolation filter 7, and A frequency error detector 13 as a means for outputting a frequency error signal by converting the information into information, and a frequency control loop filter 1 as a means for smoothing the frequency error signal output from the frequency error detector 13 4 and an oscillator 15 that supplies the analog-to-digital converter 3 with a clock.
- the frequency error detector 13 may have, for example, a configuration as shown in FIG.
- the zero-cross length detection means configured by means for holding in a register.
- the ratio of adjacent zero-cross lengths in the period established by the frame counter 30 composed of means for counting a specific period of one frame or more using the output of the unit 29 is the ratio of the synchronous pattern, For example, in the DVD-ROM, only when 14: 4 is satisfied, the synchronous pattern length detector 31 composed of means for detecting the maximum value obtained by adding the count value and holding it in a register is used.
- Period information 1 that is inversely proportional to the linear velocity period of the reproduced digital data is obtained.
- the synchronization pattern length detector 31 determines that it is a synchronization pattern in order to further approach the frequency of the clock component of the playback clock.
- a synchronization pattern flag is output by the device, and a synchronization pattern interval detector 32 constituted by means for counting an interval until the next synchronization pattern flag is detected detects a period in which a synchronization pattern is generated.
- the difference from 1488 T (where T indicates one channel bit) is obtained as period information 2. With these period information 1 and period information 2, the oscillation clock of the oscillator 15 is controlled up to the frequency region where phase synchronization is possible.
- control noise does not increase even if the loop gain is increased, which not only reduces the degradation of the reproduction signal quality due to offset correction, but also increases the DC frequency with higher frequency components.
- High tracking performance and stable operation are guaranteed for abnormal signals generated by level fluctuations, amplitude modulation, and scratches. This makes it possible to improve playability even during playback under abnormal conditions.
- the transversal filter 6 the high-order interpolation filter 7, the tap weighting factor control means 8, the phase comparator 9, and the loop filter 10
- the transversal filter 6, the phase comparator 9 The loop filter 10 and the phase interpolation type tap weight coefficient control means 33 may be used.
- the offset correction means 4 may have a configuration as shown in FIG. That is, from the output signal of the high-order interpolation filter 7, a zero-cross position detecting means 45 having a function of detecting a position where the signal crosses a zero level and outputting a zero-cross flag is referred to in FIG.
- the zero-cross function configured to output the amplitude difference (E in the figure) between the true DC level and the false DC level shown in Fig. 19 It has an amplitude output means 46 and a polarity value output means 47 having a function of outputting a given value X or one X according to the polarity of the sampled signal which is not a zero cross position.
- An arbitrary gain can be set for the output signal of the polarity value output means 47 by the gain adjustment means 50.
- the offset correction control can be performed by changing the ratio with the amplitude error amount at the zero-cross position to the zero cross amplitude output means 46. It is possible to adjust which of the output signals of the polarity value output means 47 is mainly controlled. When the output signal of the zero-cross amplitude output means 46 is mainly used, it is possible to perform advantageous control for DC level fluctuations after phase lock-in, but if phase lock-in is broken, offset correction control is also performed at the same time. Crumble. Conversely, when the output signal of the polarity value output means 47 is mainly used, the control noise increases, but the offset correction can be performed quickly and reliably.
- the output signals of the zero-cross amplitude output means 46 and the gain adjustment means 50 obtained as described above are integrated as an offset error signal by the selector 48, which is a means for switching and outputting the output signals with the zero-cross flag, and then smoothing. Is input to the offset correction loop filter 49 for conversion. Finally, the subtractor 18 directly subtracts the output signal of the offset correction loop filter 49 from the output signal of the analog-to-digital converter 3 to perform offset correction.
- the offset correction means 4 may have a configuration as shown in FIG.
- a zero-cross position detecting means 45 constituted by a function of detecting a position where the signal crosses a zero level and outputting a zero-cross flag is indicated by " ⁇ " in FIG.
- the zero-cross amplitude output consisting of the function to output the amplitude difference (E in the figure) between the true DC level and the false DC level shown in Fig.
- Any gain can be set to the output signal of the polarity value output means 47 by the gain adjustment means 50.
- a mode control means 51 is provided as a means for controlling the gain adjusting means 50.
- the mode control means 51 for example, at the time of seeking, in order to improve the response performance, the mode is set to a mode mainly controlling the output signal of the polarity value output means 47, and when the phase synchronization is pulled in, the zero cross amplitude output means is set.
- the output signals of the zero-crossing amplitude output means 46 and the gain adjustment means 50 obtained as described above are integrated as an offset error signal by the selector 48, which is a means for switching and outputting the output signals using the zero-cross flag. Is input to the offset correction loop filter 49 for conversion. Finally, the offset correction loop signal is obtained from the output signal of the analog / digital converter 3 by the subtraction means 18. The output signal of the filter 49 is directly subtracted to perform offset correction.
- the offset correction means 4 may have a configuration as shown in FIG.
- a zero-cross position detection means 45 composed of a function of detecting a position where the signal crosses a zero level and outputting a zero-cross flag, and “ ⁇ ” in FIG.
- the zero-cross amplitude output consisting of the function to output the amplitude difference (E in the figure) between the true DC level and the false DC level shown in Fig. 19
- Means 46 and polarity value output means 47 configured to output an arbitrary value X or one X according to the polarity of the signal for the sampled signal not at the cross position.
- the gain adjusting means 50 can set an arbitrary gain to the output signal of the polarity value output means 47.
- the output signal of the polarity value output means 47 is accumulated for an arbitrary constant time set by the counter 52 as a means to restore the normal phase synchronization state.
- the addition is performed by the addition means 53, and the output signal level is monitored by the quasi-phase synchronization determination means 54 to determine whether or not the quasi-phase synchronization state is established.
- the normal phase synchronization state is restored by using the gain adjustment means 50 to enhance the offset correction by the polarity component of the code.
- the output signals of the zero-cross amplitude output means 46 and the gain adjustment means 50 obtained as described above are integrated as an offset error signal by the selector 48, which is a means for switching and outputting with the zero-cross flag, and then smoothing. Input to the offset correction loop filter 49 for conversion. Finally, the output signal of the analog-to-digital converter 3 is output from the offset correction loop filter 49 by the subtraction means 18. The offset correction is performed by directly subtracting the force signal.
- the digital recording data reproducing apparatus is a digital recording data reproducing apparatus that reproduces digital recording data recorded on an optical disc, a part for performing phase equalization of reproduced digital recording data. Suitable for use in
Description
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US09/936,513 US6674707B2 (en) | 2000-01-17 | 2001-01-17 | Digital recorded data reproducing device |
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JP2000008021A JP3486145B2 (ja) | 2000-01-17 | 2000-01-17 | デジタル記録データ再生装置 |
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JP (1) | JP3486145B2 (ja) |
KR (1) | KR100490498B1 (ja) |
CN (1) | CN100405489C (ja) |
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Also Published As
Publication number | Publication date |
---|---|
JP3486145B2 (ja) | 2004-01-13 |
ID30337A (id) | 2001-11-22 |
US6674707B2 (en) | 2004-01-06 |
CN100405489C (zh) | 2008-07-23 |
TW591617B (en) | 2004-06-11 |
US20020159350A1 (en) | 2002-10-31 |
CN1358310A (zh) | 2002-07-10 |
JP2001195830A (ja) | 2001-07-19 |
KR20020006683A (ko) | 2002-01-24 |
KR100490498B1 (ko) | 2005-05-19 |
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