WO1997012363A2 - Improved fault tolerant sync mark detector for sampled amplitude magnetic recording - Google Patents
Improved fault tolerant sync mark detector for sampled amplitude magnetic recording Download PDFInfo
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- WO1997012363A2 WO1997012363A2 PCT/US1996/015582 US9615582W WO9712363A2 WO 1997012363 A2 WO1997012363 A2 WO 1997012363A2 US 9615582 W US9615582 W US 9615582W WO 9712363 A2 WO9712363 A2 WO 9712363A2
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- sync mark
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
- G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
- G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/012—Recording on, or reproducing or erasing from, magnetic disks
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B2020/1476—Synchronisation patterns; Coping with defects thereof
Definitions
- the present invention relates to the control of magnetic storage systems for digital computers, and particularly, to a sampled amplitude read channel inco ⁇ orating a fault tolerant sync mark detector.
- digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written onto the surface of a magnetic medium in concentric tracks.
- the read/write head passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog signal that alternate in polarity. These pulses are then detected and decoded by read channel circuitry to reproduce the digital data.
- Detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel.
- Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and, therefore, are less susceptible to noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
- ISI intersymbol interference
- DPD discrete time pulse detection
- PR partial response
- MLSD maximum likelihood sequence detection
- DFE decision-feedback equalization
- EDFE enhanced decision-feedback equalization
- FDTS/DF fixed-delay tree-search with decision-feedback
- analog circuitry responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head.
- the analog read signal is "segmented” into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a "1" bit, whereas the absence of a peak is detected as a "0" bit.
- Timing recovery then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive "0" bits.
- RLL run length limited
- detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error.
- the ISI effect is reduced by decreasing the data density or by employing an encoding scheme to ensure that a minimum number of "0" bits occur between "1" bits.
- a (d,k) run length limited (RLL) code constrains to d the minimum number of "0" bits between "1” bits, and to k the maximum number of consecutive "0" bits.
- a typical RLL code is a (1 ,7) 2/3 rate code which encodes 8 bit data words into 12 bit codewords to satisfy the (1 ,7) constraint.
- Sampled amplitude detection such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference.
- sampled amplitude recording detects digital data by inte ⁇ reting, at discrete time instances, the actual value of the pulse data.
- the analog pulses are sampled at the baud rate (code bit rate) and the digital data is detected from these discrete time sample values.
- a discrete time sequence detector such as a Viterbi detector, inte ⁇ rets the discrete time sample values in context to determine a most likely sequence for the data. In this manner, the effect of ISI can be taken into account during the detection process, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
- the format of the data stored on the magnetic disk is similar for both peak detection and sampled amplitude read channels.
- the data is stored as a series of concentric tracks 13 each comprising a number of user data sectors 15 and embedded servo data sectors 17.
- the embedded servo data sectors 17 are recorded at the same data rate across the disk's radius.
- the disk is partitioned into a number of zones (e.g., an outer zone 11 and an inner zone 27) and the data rate increased in the outer zones in order to achieve a more constant linear bit density.
- This "zoned" recording technique allows more data to be stored in the outer diameter tracks, thereby increasing the overall capacity of the disk.
- Figure 2B shows the format of a user data sector 15 and a servo data sector 17 comprising a preamble (68,5), sync mark (70,7) and data field (72,3).
- the read channel processes the preamble (68,5) to adjust the magnitude of the read signal (and synchronize timing recovery in sampled amplitude read channels) so that it can accurately read the data field (72,3).
- the sync mark (70,7) demarks the beginning of the data field (72,3), and when the read channel detects the sync mark (70,7), it signals a disk controller (not shown) to begin processing the detected data.
- the sync mark (70,7) must be detected at the correct time or the read channel cannot synchronize to the data field (72,3). Errors due to noise in the system can cause the read channel to detect the sync mark (70,7) too early or fail to detect it altogether. That is, errors in the detected read signal can cause the read channel to falsely detect the sync mark as the end of the preamble concatenated with the beginning of the sync mark. When this happens, error detection circuitry within the disk controller will recognize that the sync mark was falsely detected and initiate a re-try. The storage system will wait for the disk to complete a revolution, which increases the overall access time, and again attempt to accurately detect the sync mark.
- a sync detector in the read channel detects the sync mark (70,7) by correlating a target sync mark with the bit sequence detected from the read signal.
- the sync mark (70,7) is selected to have a minimum correlation with the sync mark (70,7) concatenated with the preamble (68,5). It is also selected for maximum probability of correct detection when the sync mark is corrupted by errors due to noise. This is accomplished with a computer search program which searches for an appropriate sync mark by correlating a target sync mark with shifted values of the target sync mark appended to the preamble. The search program also correlates the target sync mark with corrupted versions of the sync mark appended to the preamble. Selecting a sync mark to have minimum correlation with the preamble increases the fault tolerance of the sync mark detector.
- Prior art sync mark detectors do not use the preamble (68,5) to assist in detecting the sync mark (70,7). Instead, conventional sync mark detectors execute a correlation with each new bit detected from the read signal.
- U.S. Patent No. 5,384,671 issued to Fisher discloses a sync mark detection technique that selects a sync mark to have minimum correlation with the preamble but does not use information from the preamble in the detection process.
- prior art sync mark detectors do not use the sign of the sampled data in order to improve the correlation sensitivity.
- a sampled amplitude read channel employs a fault tolerant sync mark detector that uses information from the preamble to improve the sync mark detection process.
- a state machine generates expected sample values used by a timing recovery circuit to acquire the preamble field.
- the preamble is recorded to the disk in a manner that ensures the state machine will be in a predetermined state when the end of the preamble is encountered. In this manner, the sync mark detector need only execute a correlation of the detected bit sequence with a target sync mark when the state machine is in the predetermined state.
- the sync mark detector correlates the detected bit sequence with a target sync mark and outputs a sync mark detected signal when the sync mark is found.
- the output of the sync mark detector is enabled according to the current state ofthe state machine, i.e , at a predetermined sample period interval In one example embodiment, the end of preamble can occur only when the state machine is in two of four states. Therefore, the sync detector is enabled at every other sample period In another embodiment, the sync mark detector processes the even and odd interleaves of the detected bit sequence in parallel, and the current state of the state machine initializes the sync mark detector rather than enable its output.
- the sync mark detector's output represents the correlation of the bit sequence with the target sync mark only during a predetermined sample period interval This increases the fault tolerance of the sync mark detector and the fault tolerant characteristics of the sync mark itself by allowing the computer search program to search for a sync mark having minimum correlation with the preamble at the predetermined interval
- the present invention achieves further fault tolerance by minimizing a mean squared error between a partial response representation of the detected sync mark and the target sync mark. This increases the correlation sensitivity since a partial response signal provides both sign and magnitude information.
- the read channel's discrete time sequence detector outputs a sign and magnitude of estimated sample values corresponding to a PR4 representation of the detected digital data.
- the PR4 sync mark data is generated by appending a sign bit to the detected binary sequence and normalizing the PR4 values from (-2,0,+2) to (-1 ,0,-1 ).
- the PR4 sync mark data is generated by appending a sign bit to the detected binary sequence (NRZI data) and then encoding the signed NRZI data into a PR4 representation.
- Figure 1 is a block diagram of a conventional sampled amplitude recording channel.
- Figure 2A shows an exemplary data format of a magnetic disk having a plurality of concentric tracks recorded in zones at varying data rates where each track contains a plurality of user data and embedded servo data sectors.
- Figure 2B shows an exemplary format of a user data sector and an embedded servo data sector.
- Figure A3 is a block diagram of the sampled amplitude read channel of the present invention comprising automatic gain control, DC offset control, timing recovery, a first and second synthesizer for processing user and servo data respectively, an asynchronous servo address mark detector, and a sync mark detector for detecting user data and servo data sync marks.
- Figure C3 is a block diagram of a sampled amplitude read channel timing recovery circuit comprising a VFO for generating a sampling frequency.
- Figure C4 shows more details of the data/servo sync detector and particularly the operation with respect to the timing recovery control signal.
- Figure C5A shows the acquisition read signal with corresponding actual and estimated sample values.
- Figure C5B is a detailed diagram of the preferred embodiment for the expected sample value generator and phase error detector used in the timing recovery circuit.
- Figure C6 is an alternative embodiment for the data/servo sync detector which processes the even and odd interleaves of the read signal in parallel.
- Figure C7 shows an EPR4 or EEPR4 sequence detector having a signed NRZI to PR4 data encoder.
- Figure C8 shows an implementation of a sync mark detector that compares a PR4 representation of the detected sync mark with the target sync mark.
- Figure C9 shows yet another implementation of the sync mark detector having a preamble synthesizer for generating an enable and sign control signals in response to the recorded preamble.
- Figure C10 shows an implementation of the preamble synthesizer of Figure C9.
- FIG. 1 is a detailed block diagram of a conventional sampled amplitude read channel.
- a data generator 4 for example 2T preamble data
- An RLL encoder 6 encodes the user data 2 into a binary sequence b(n) 8 according to an RLL constraint.
- a precoder 10 precodes the binary sequence b(n) 8 in order to compensate for the transfer function of the recording channel 18 and equalizing filters to form a precoded sequence ⁇ b(n) 12.
- Write circuitry 9 responsive to the symbols a(n) 16 modulates the current in the recording head coil at the baud rate 1/T to record the binary sequence onto the media.
- a frequency synthesizer 52 provides a baud rate write clock 54 to the write circuitry 9.
- the recorded data is referred to as NRZI data where each magnetic transition represents a "1" bit and each non-transition represents a "0" bit.
- timing recovery 28 is first locked to the write frequency by selecting, as the input to the read channel, the write clock 54 through a multiplexor 60. Once locked to the write frequency, the multiplexor 60 selects the signal 19 from the read head as the input to the read channel in order to acquire the acquisition preamble.
- a variable gain amplifier 22 adjusts the amplitude of the analog read signal 58, and an analog filter 20 provides initial equalization toward the desired response.
- a sampling device 24 samples the analog read signal 62 from the analog filter 20, and a discrete time filter 26 provides further equalization of the sample values 25 toward the desired response. In partial response recording, for example, the desired response is often selected from Table 1.
- a DC offset circuit 1 responsive to the equalized sample values 32 computes and subtracts the DC offset 29 from the analog read signal 62.
- the equalized sample values 32 are applied to decision directed gain control 50 and timing recovery 28 for adjusting the amplitude of the read signal 58 and the frequency and phase ofthe sampling device 24, respectively.
- Timing recovery adjusts the frequency of sampling device 24 over line 23 in order to synchronize the equalized samples 32 to the baud rate.
- Frequency synthesizer 52 provides a coarse center frequency setting to the timing recovery circuit 28 over line 64 in order to center the timing recovery frequency over temperature, voltage, and process variations.
- Gain control 50 adjusts the gain of variable gain amplifier 22 over line 21.
- the equalized samples Y(n) 32 are sent to a discrete time sequence detector 34, such as a maximum likelihood (ML) Viterbi sequence detector, to detect an estimated binary sequence ⁇ b(n) 33.
- the discrete time sequence detector operates according to the selected equalization (PR4, EPR4, EEPR4, etc.), and for PR4 equalization, the preferred embodiment is two sliding threshold detectors for processing the even and odd interleaves, respectively.
- An RLL decoder 36 decodes the estimated binary sequence A b(n) 33 into estimated user data 37.
- a data sync mark detector 66 detects the sync mark 70 (shown in Figure 2B) in the data sector 15 in order to frame the operation of the RLL decoder 36 and signal the beginning of user data 72.
- the estimated binary sequence A b(n) 33 equals the recorded binary sequence b(n) 8
- the decoded user data 37 equals the recorded user data 2
- Figure A3 is a block diagram of the improved sampled amplitude read channel of the present invention comprising a user data frequency synthesizer A100 and a servo data frequency synthesizer A102.
- a control line U/S selects the output A114 of the user data synthesizer A100 as the lock to reference frequency through a multiplexor A104
- the control line U/S also selects the coarse center frequency setting A110 of the user data synthesizer A100 through multiplexor A112 as the timing recovery control signal 64
- the control line U/S selects the output A106 of the servo data synthesizer A102 as the lock to reference frequency through multiplexor A104
- the control line U/S also selects the coarse center frequency setting A108 from the servo data synthesizer A102 through multiplexor A112 as the timing recovery control signal 64
- the read channel further comprises an asynchronous servo address mark detector A126 for generating a control signal A118 indicating when the servo address mark has been detected
- the servo address mark detector A126 switches operation of the gain control circuit over line A118 to compensate for the unpredictable amplitude fluctuations caused by the inter-track head position and the wide range of user to servo data densities
- a data servo sync mark detector A120 responsive to the detected binary sequence 33 from the sequence detector 34, detects both user data and servo data sync marks and generates framing signals (A121 ,A119) to frame operation of a user data RLL decoder 36 and a servo data RLL decoder A122, respectively.
- the sync detector A120 is also responsive to a control signal A124 from the timing recovery circuit 28 to aid in the sync mark detection process
- the read channel further comprises auxiliary analog inputs for sampling other analog signals generated within the disk drive such as the driving current for a Voice Coil Motor in a servo system, or the output of a temperature sensor A multiplexor A101 selects, as the input to sampling device 24, the analog read signal 62 from the analog receive filter 20 or one of a plurality of auxiliary input signals A103.
- a microcontroller such as a servo controller.
- a data/servo sync mark detector A120 of Figure A3 searches for the sync mark (70,7) which demarks the beginning of the user or servo data fields.
- the data servo sync detector A120 enables operation of the RLL data decoder 36 or the RLL servo decoder A122 in order to frame the user or servo data fields.
- the data/servo sync mark detector A120 detects the sync mark (70,7) by correlating a target sync mark with the estimated bit sequence b(n) 33 from the discrete time sequence detector.
- the sync mark (70,7) is selected to have a minimum correlation with the sync mark (70,7) concatenated with the preamble (68,5). It is also selected for maximum probability of correct detection when the sync mark is corrupted by errors due to noise. This is accomplished with a computer search program which searches for an appropriate sync mark by correlating a target sync mark with shifted values of the target sync mark appended to the preamble. The search program also correlates the target sync mark with corrupted versions of the sync mark appended to the preamble.
- the estimated bit sequence b(n) 33 is shifted into a shift register C100 and the target sync mark (servo or data) is loaded into register C102.
- Registers C100 and C102 are programmable to accommodate various sync mark lengths.
- the corresponding bits of registers C100 and C102 are correlated (using an exclusive-nor gate not shown) and summed with an adder C104.
- a threshold comparator C118 compares the output ofthe adder C104 to a predetermined programmable threshold and outputs a threshold correlation signal C106.
- the threshold correlation signal C106 is enabled through an AND gate C108 by a control signal C194 generated in response to a timing recovery control signal A124.
- the output C114 of the AND gate C 108 is applied to the RLL decoder framing signals (A121.A119) through a de-multiplexor C116 according to the state of the U/S control signal.
- the control signal C194 for enabling the threshold correlation signal C106 is understood in relation to the operation of the timing recovery circuit 28, an overview of which is provided in Figure C3.
- the output 23 of a variable frequency oscillator (VFO) B164 controls the sampling clock of a sampling device 24 which is typically an analog-to-digital converter (A/D) in digital read channels.
- a frequency error detector B157 and phase error detector B155 control the frequency of the VFO B164, and a loop filter B160 provides control over the closed loop characteristics.
- a multiplexor B159 may select the unequalized sample values 25 during acquisition, and the equalized sample values 32 during tracking. From the sample values received over line B149, the frequency error detector B157 generates a frequency error, and the phase error detector B155 generates a phase error.
- the phase error is also computed from expected sample values X(n) from an expected sample generator B151 during acquisition, and estimated sample values ⁇ X(n) from a sample value estimator B141 , such as a slicer according to Table B2, during tracking.
- the phase-lock-loop before acquiring the acquisition preamble (68,5) the phase-lock-loop first locks onto a predetermined nominal sampling frequency according to the zone where the current track is located. In this manner, the phase-lock-loop is close to the desired acquisition frequency when it switches to acquisition mode.
- the acquisition preamble (68,5) is processed during acquisition mode in order to lock the PLL to the desired sampling phase and frequency before sampling the user or servo data fields (72,3).
- the phase-lock-loop switches into tracking mode and, after detecting the sync mark (70,7), begins tracking user or servo data (72,3).
- a data generator 4 connected to the input of the precoder 10 outputs a series of "1" bits to generate a 2T training preamble sequence at the output of the precoder 10 of the form (1 ,1 , 0,0, 1 ,1 ,0,0,1 ,1 ,0,0,).
- This 2T preamble maximizes the magnitude of a PR4 read channel, and during acquisition, it is "side sampled” to generate the following sample sequence: (+A,+A,-A,-A,+A,+A,-A,-A,+A,+A,-A,-A,).
- Figure C5A shows the 2T preamble "side sampled" with the expected samples C120 in relation to the signal samples C122 and a corresponding phase error T.
- Figure C5B shows an implementation of the phase error detector B155 and the expected sample value generator B151 of Figure C3.
- the phase error detector B155 computes a timing gradient which minimizes the mean squared error between read signal sample values and expected sample values.
- the expected sample value is scaled to
- 1 so that the multipliers (C130a,C130b) of the phase error detector B155 multiply by +1 , -1 or 0.
- the expected sample values X(n) C126 are two bits wide in order to represent the ternary values:
- a multiplexor C132 responsive to the outputs (C137.C138) of the counter C128, selects the expected sample values X(n) C126 which correspond to the current counter state.
- the counter C128 is loaded C134 with an initial starting state by logic C136 in response to two consecutive sample values Y(n) C149.
- Table C2 shows the "side sampled" starting state values loaded into counter C128 corresponding to the two consecutive sample values.
- the counter C128 After the counter C128 is loaded with the initial starting state, it sequences through the states according to the expected samples in the 2T preamble at each sample clock 23.
- the four possible sequences are:
- the output 25 of the A/D converter 24 will be the last preamble sample only when the counter C 128 of Figure C5B is in state (-A,-A) or (+A.+A) which corresponds to counter C128 outputs 01 (i.e., the count is one) or 11 (i.e., the count is three). Therefore, the output 25 of the A/D converter 24 will be the first sample of the sync mark only when the counter C128 output is 10 (ie., the count is two) or 00 (i.e., the count is zero).
- the output 33 of the sequence detector 34 will be the first bit of the sync mark only when the counter C 128 output is (2+d) MOD 4 or (0+d) MOD 4.
- the sync mark register C100 is k bits in length, then the sync mark will be completely loaded into the register C100 only when the counter C128 output is (2+d+k) MOD 4 or (0+d+k) MOD 4.
- the data servo sync mark detector A120 is enabled only during these two counts, i.e., only at every other sample period.
- Counter decode logic C190 enables the output of the data/servo sync mark detector A120 through AND gate C108 only when the counter C128 output (C137,C138) equals either of the two counts (2+d+k) MOD 4 or (0+d+k) MOD 4.
- the state of the precoder 10 is initialized to an appropriate value when writing the preamble (68,5) to the disk.
- the delay registers in the 1/1+D 2 precoder 10 are initialized to zero and an even number of 1 bits are output by the data generator 4 to ensure that the preamble ends in either two positive samples or two negative samples.
- Enabling the data/servo sync mark detector A120 at every other sample period aids in the computer search for the optimum fault tolerant sync mark.
- the search program can search for minimum correlation between the sync mark and shifted versions of the sync mark concatenated with the preamble at every other shift rather than at every shift. This increases the probability of finding a sync mark having a higher degree of fault tolerance.
- the sync mark detection technique ofthe present invention can be easily extended to search for the sync mark at every fourth sample period rather than at every other sample period. This requires that the preamble always end in the same two sample values (i.e., the preamble ends with the counter C128 in one out of the four possible states). Further, this technique can easily be extended for use with other preamble formats (e.g., 3T, 4T, 6T, etc) and with other types of PR read channels (e.g., EPR4 and EEPR4).
- preamble formats e.g., 3T, 4T, 6T, etc
- PR read channels e.g., EPR4 and EEPR4
- the data/ servo sync mark detector A120 processes two bits of the detected sequence 33 at a time.
- the target sync mark C102 is separated into in an even and odd interleave and stored in an even register C150 and an odd register C152, respectively.
- Control logic C140 loads the even and odd interleaves (C142.C144) of the detected sequence 33 into respective shift registers (C146,C148) in response to an enable signal C194 from counter decode logic C 190.
- the control logic C140 delays loading the shift registers (C146,C1 8) with the detected sequence 33 until the counter C 128 of Figure C5B is in one of the two enabling states ((2+d) MOD 4 or (0+d) MOD 4).
- the data/servo sync mark detector A120 correlates estimated sample values with expected sample values that corresponded to the target sync mark.
- the data/ servo sync mark detector A120 is specified, in general, as generating channel values in response to the discrete time sample values and correlating the channel values with target values of a target sync mark.
- the estimated and expected sample values of the detected and target sync mark are represented by Partial Response Class-IV (PR4) signals.
- the discrete time sequence detector 34 of Figure A3 outputs a sign and magnitude of the detected binary sequence (i.e., a two bit wide sequence).
- the signed binary output sequence is then encoded into a PR4 signal of estimated sample values. If the discrete time sequence detector 34 is a PR4 detector, then the signed binary output sequence is already in the PR4 format with the estimated samples normalized to (-1 ,0,+1 ). If the discrete time sequence detector 34 is an EPR4 or EEPR4 detector, then the output of the detector (NRZI format) is converted into a PR4 signal by passing the sign and magnitude bits through a (1+D) filter as shown in Figure C7.
- the sync mark detector computes a squared error between the detected PR4 sync mark and the target PR4 sync mark. When the squared error falls below a predetermined programmable threshold Th, the sync mark has been detected.
- COR is either + 2 S k .t k or - 2 S k *t k depending on the polarity of the read signal as determined by the timing recovery control signal C138 of Figure C5B.
- the term 2 S k 2 equals the number of ones in the estimated samples and can be computed by counting the number of ones input into the sync mark detector.
- FIG. C8 A circuit for implementing equations (1 ) and (2) is illustrated in Figure C8.
- a 9-bit target sync mark 010010001 has been selected for the purpose of illustration, but other sync mark lengths and values are equally applicable.
- the circuit of Figure C8 assumes that the preamble always ends in two negative samples resulting in PR4 sample values for the target sync mark of 0+00+000-. If the preamble ends in two positive samples, then the PR4 values for the target sync mark are 0-00-000+ and the correlation is negated as described below.
- control logic C140 responsive to a control signal C194 from counter decode logic C190, delays loading the shift registers with the PR4 data until the counter C128 of Figure C5B is in one of the enabling states as described above.
- an adder C160 adds the estimated PR4 values corresponding to the non-zero target PR4 values. Since the last target PR4 value is a "-1" when the preamble ends in two negative samples, an AND gate C162 negates the last bit of the estimated PR4 values.
- a multiplying circuit C164 multiplies the COR signal by 2, and a multiplexor C166, responsive to the decoded timing recovery control signal C192, selects between an unmodified or a negated 2 » COR signal (i.e., multiplied by -1 C188) depending on whether the preamble ends in - or ++, respectively.
- control signal C192 from the counter decode logic C190 will negate the correlation signal C186 when the output of the timing recovery counter C128 equals (0+d+k) MOD 4 which corresponds to the preamble ending in two positive samples (i.e., the target PR4 sample values are 0-00-000+).
- the circuit C168 for generating the CNT threshold value of equation (1 ) operates as follows. First, a storage register C170 is loaded with a predetermined prgrammable threshold -Th' C172 through a multiplexor C174, and the sync mark detector shift registers are cleared. Then for each clock cycle, counter logic C176 counts the number of non-zero values entering the sync mark detector and subtracts the number of non-zero values exiting the sync mark detector. The output of counter logic C176 (which can take on the values ⁇ 0, ⁇ 1 , ⁇ 2 ⁇ ) is input into an adder C178, added to the content of the storage register C170, and restored to the storage register C170 through multiplexor C174.
- the storage register C170 which contains the CNT value C180 of equation (1 ), is compared to the 2 » COR value C182 at the output of the multiplexor C166 using a comparator C184.
- the output of the comparator C 184 is the output C114 of the sync mark detector.
- Figure C9 illustrates yet another embodiment of the sync mark detector which correlates the PR4 representation of the detected and target sync marks independent of the timing recovery expected sample generator B151 (i.e., independent of the counter C128).
- a preamble synthesizer C196 generates the input control signal C194 and the sign control signal C 192 in response to the recorded preamble.
- the preamble synthesizer C196 locks onto the recorded preamble sequence and then generates the 2T preamble independent of the sampled input sequence. Operation of the preamble synthesizer C196 is understood with reference to Figure C10.
- a counter C208 is cleared and a first shift register C202 is initialized with the sequence 1 ,1 ,0,0,1 ,1 , ...,0,0 which corresponds to the PR4 sign bit sequence of the 2T preamble.
- the PR4 sign bit C200 from the sequence detector 34 is then input into a second shift register C204 and correlated with the first shift register C202 using an adder C206 and exclusive-nor gates not shown.
- the output of the adder C206 is compared to a predetermined threshold using a comparator C210. When the correlation exceeds the predetermined threshold, the preamble synthesizer has locked onto the recorded preamble.
- the counter C208 is enabled and clocked at each sample period to generate the sync mark detector input enable signal C194 and the sign control signal C192 through counter decode logic C190. Operation of the counter decode logic C 190 is as described above except that it does not need to compensate for the delay associated with the equalizing filter 26 and sequence detector 34. That is, the input enable signal C194 is active when the output of the counter C208 is 00 or 10, and the sign control signal C192 is active when the output of the counter C208 is (0+k) MOD 4.
- the CO output of counter C208 is also shifted into the first shift register C202 so that the preamble synthesizer C196 continues to track the recorded 2T preamble. In this manner, the preamble synthesizer filters out errors in the detected 2T preamble caused by noise in the channel.
- Y(k) output C114 of the data/servo sync mark detector A120; k: the sample value index;
- N length of the target sync mark
- I a sample period interval enable signal that is equal to 1 when k modulo Q is a member of a set S and 0 otherwise, where Q is a predetermined integer not equal to 1 ; and Th: a predetermined threshold.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96936042A EP0793843B1 (en) | 1995-09-26 | 1996-09-26 | Improved fault tolerant sync mark detector for sampled amplitude magnetic recording |
JP9513716A JPH10510089A (en) | 1995-09-26 | 1996-09-26 | Improved fault-tolerant synchronous mark detector for sampled amplitude magnetic recording |
DE69617630T DE69617630T2 (en) | 1995-09-26 | 1996-09-26 | IMPROVED ERROR-TOLERANT SYNC BRAND DETECTOR FOR MAGNETIC RECORDING WITH AMPLITUDE SCAN |
HK98102007A HK1002885A1 (en) | 1995-09-26 | 1998-03-13 | Improved fault tolerant sync mark detector for sampled amplitude magnetic recording |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/533,797 | 1995-09-26 | ||
US08/533,797 US5793548A (en) | 1995-05-12 | 1995-09-26 | Fault tolerant sync mark detector for comparing a sign and magnitude of a detected sequence to a target sync mark in sampled amplitude magnetic recording |
Publications (2)
Publication Number | Publication Date |
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WO1997012363A2 true WO1997012363A2 (en) | 1997-04-03 |
WO1997012363A3 WO1997012363A3 (en) | 1997-05-22 |
Family
ID=24127478
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Application Number | Title | Priority Date | Filing Date |
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PCT/US1996/015582 WO1997012363A2 (en) | 1995-09-26 | 1996-09-26 | Improved fault tolerant sync mark detector for sampled amplitude magnetic recording |
Country Status (7)
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US (1) | US5793548A (en) |
EP (1) | EP0793843B1 (en) |
JP (4) | JPH10510089A (en) |
KR (1) | KR100495715B1 (en) |
DE (1) | DE69617630T2 (en) |
HK (1) | HK1002885A1 (en) |
WO (1) | WO1997012363A2 (en) |
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Also Published As
Publication number | Publication date |
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JP2007080514A (en) | 2007-03-29 |
DE69617630D1 (en) | 2002-01-17 |
WO1997012363A3 (en) | 1997-05-22 |
KR980700653A (en) | 1998-03-30 |
JP2011216182A (en) | 2011-10-27 |
JPH10510089A (en) | 1998-09-29 |
KR100495715B1 (en) | 2005-10-12 |
HK1002885A1 (en) | 1998-09-25 |
US5793548A (en) | 1998-08-11 |
EP0793843A1 (en) | 1997-09-10 |
JP4793945B2 (en) | 2011-10-12 |
DE69617630T2 (en) | 2002-05-08 |
JP2009043408A (en) | 2009-02-26 |
EP0793843B1 (en) | 2001-12-05 |
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