WO1994018670A1 - Synchronous read channel - Google Patents

Abstract

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control (32), timing recovery (34), sequence detection (40), RLL (1, 7) encoding (48) and RLL (1, 7) decoding (28), and channel quality measurement (46) is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection (40). These characteristics, together with error-tolerant sync mark detection (26) and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Description

SYNCHRONOUS READ CHANNEL BACKGROUND OF THE INVENTION

In the storage or transmission of digital

information, the bits or symbols of the user data are actually transmitted or stored via a physical media or mechanism whose responses are essentially analog in nature. The analog write or transmit signal going into the storage/transmission media or channel is typically modulated by channel bits (typically run-length limited or RLL bits) that are an encoded version of the original user-data bits (non-return-to-zero or NRZ bits). The analog read or receive signal coming from the media is demodulated to detect or extract estimated channel bits, which are then decoded into estimated user-data bits. Ideally, the estimated user-data bits would be an identical copy of the original user-data bits. In practice, they can be corrupted by distortion, timing variations, noise and flaws in the media and in the write/transmit and read/receive channels.

The process of demodulating the analog read signal into a stream of estimated user-data bits can be

implemented digitally. Digital demodulation in magnetic mass storage systems requires that the analog read signal be sampled at a rate that is on the order of the channel-bit rate. Maximum-likelihood (ML) demodulation is a process of constructing a best estimate of the channel bits that were written based on digitized samples captured from the analog read signal.

FIGURE 1 shows an exemplary read signal 100, which is a positive-going pulse generated by an inductive read head, for example, from a single media transition such as transition 103 from North-South to South-North magnetization of track 104 on a rotating disk.

Typically, the write signal modulates a transition in the state of the media to write a channel bit of 1 and modulates the absence of a media transition to write a 0 channel bit. Thus, transition 103 corresponds to a single channel bit of value 1 in a stream of 0's.

It is common to use run-length-limited (RLL) encoding of the original user data bits, which are arbitrary or unconstrained, into an RLL-encoded stream of channel bits. It may be desirable that there be no less than d zeroes between ones; that is, that the media transitions be spaced by at least d+1 channel bit times. This constraint can help keep to a manageable level the interference effects among the pulses in the analog read signal. On the other hand, because media transitions provide timing information that must be extracted from the read signal to ensure synchronization of the

demodulator with the pulses in the read signal, it may be desirable that there be no more than k zeroes between ones; that is, that there be a media transition at least every k'th channel bit time. An RLL(d,k) code is a code that can encode an arbitrary stream of original user- data bits into a stream of channel bits such that the encoded channel bit stream satisfies these two

constraints. An RLL code has a theoretical capacity which limits the number of user bits which can be represented in a given number of RLL bits. The capacity is a function of the d and k constraints with d=0 and k=infinite being the limiting (unconstrained) case with a capacity of exactly one. The capacity of an RLL (1,7) code for example is just slightly greater than 2/3 and is exactly 2/3 for any practical implementation, meaning that every pair of user bits will map to exactly three RLL bits.

FIGURE 1, sample set 101 shows the values of four samples in the case of side sampling of read signal 100; i.e. 0.333, 1.0, 1.0, and 0.333. Sample set 101 is equivalent to the set 1, 3, 3, 1; that is, only the ratios among samples are significant. A signal model gives rise to an expected sample sequence for a single or isolated transition in media state. Typically, only a few samples of an isolated media transition are nonzero; in this case, four are non-zero. In a side- sampled signal model such as 1, 3, 3, 1, timing

circuitry in the demodulator attempts to maintain a lock on the incoming signal such that two adjacent samples on opposite sides of the peak of an isolated pulse have equal amplitudes and samples are taken at roughly equal time intervals, each a single channel bit time.

Synchronization of the samples with the spacing of the bits written on the media is maintained by a timing recovery loop which is in essence a phase-locked loop. Other sample timing arrangements may be useful. In center sampling, the timing circuitry tries to lock the sample times to the read signal pulses such that one sample occurs at the peak of each pulse. Sample set 102 shows the values of four samples in the case of center sampling of a similar read signal 104; i.e., 0.5, 1.0, 0.5, and 0.0 (or 1.0, 2.0, 1.0 and 0.0 depending on the arbitrary normalization used). An expected sample sequence of 1, 2, 1, 0 corresponds to the signal model known in the prior art as Extended Partial-Response Class IV (EPR4). Such sample sequences are samples of a continuous-time analog read-signal waveform such as may be produced in the readback circuitry of a magnetic storage device. For a system that is bandwidth limited to 1/ (2T), where T is the sample spacing in time, the sampling theorem declares that the continuous time waveform must be superposition of sine functions

(sinc(x) is defined as sin(x)/x for x<>0, and as 1 for x=0), with one sine function centered at each sample point and of amplitude equal to that sample value and with zero crossings at all other sample points. As an example, in saturation magnetic recording, the current in an inductive write head takes, on values of +1 and -1. The basic excitation applied to the recording channel is a step in current from +1 to -1, vice versa, in the analog write signal. This step in write current

produces a transition in the magnetization state of the media as it moves past the head. When an inductive read head is passed over this magnetic media transition, a voltage pulse is induced by the bandwidth limited differentiating interaction of the head with the

magnetization of the media. By suitable filtering or equalization, the sequence of samples on an isolated transition response pulse can be made to {..., 0, 0, 1, 2, 1, 0, 0, ...}, in which case the recording or

transmission channel matches the EPR4 signal model.

Another sample sequence well known in the prior art is the Partial Response Class IV signal model (PR4), which corresponds to an expected sample sequence of 0, 1, 1, 0. Further, as one is designing or taking measurements on a write/media/read channel, it may be desirable to take into account the exact response, noise and

distortion characteristics of the channel in selecting the signal model to be implemented in the demodulator. Thus, there is a need for a demodulator that is

programmable as to the signal model, or expected

sequence of sample values for an isolated media

transition. In situations such as mass information storage in magnetic media, significant storage-system speed and capacity gains can be realized if the

information bits can be closer together in position/time on the media. further, as media transitions are more closely positioned, the writing and reading processes become more sensitive to the distortion, timing

variations and noise that are inevitably introduced in the processes of writing, storing, and reading. Also, as the transitions become closer, the ability of the media to fully transition from, say, North-South magnetization to South-North magnetization may be taxed. Also, as the media transitions become closer,

interference effects increase among adjacent or nearby transitions. FIGURE 2 shows how positive-going pulse 200 from first media transition 201 combines with negative-going pulse 202 from second transition 203 to produce analog read signal 204, which can be viewed as the interference of the two pulses. Adjacent media transitions always give rise to read pulses of opposite polarities because they always are created by

transitions of opposite types, for example North-South changes to South-North in transition 201, so adjacent transition 202 must be South-North changing back to North-South. Read signal 204 might give rise to a sequence of samples such as 0.333, 1.0, 0.667, -0.667, -1.0, 0.333. To the extent that the read process is linear (and it may not be entirely linear), the voltage waveform induced in the read head will be the

superposition of a sequence of pulses, where each pulse is the response to an isolated magnetic transition on the media. Clearly, engineering a high-performance read channel is a complex challenge given the combined effects of the limited sampling rate in a digital demodulator, possibly incomplete transitions in the media, interference among read-signal responses to media transitions, and distortion, timing variations, noise and flaws in the media and in the write and read

channels. The prior art uses a method known as partial- response signaling to increase media transition rates. Partial-response signaling is described in the book "Digital Transmission of Information", by Richard E.

Blahut, 1990, pp. 139-158 and 249-255. This method allows the analog response of the storage/transmission media and of the write/transmit and read/receive

circuitry to a media transition to overlap with the response to adjacent transitions associated with subsequent information bits. If properly implemented, this method can achieve higher information bit

rates/densities than the alternative or requiring the media transitions to be spaced such that the read signal responses do not overlap. Such a method requires a sequence detector which can make its decisions not on a bit-by-bit basis but by examining the context of the surrounding read signal.

In a magnetic disk drive, the surface of the magnetic media is logically divided into concentric rings called tracks. The distance around the track varies as a function of the radius at which the track lies. Since it is desirable to keep the rate of revolution of the disk constant to avoid mechanical delays in accelerating and decelerating the disk, it is necessary to either store an amount of data on each track which is proportional to the length of the track (this requires a different data transfer rate for each track) or to vary the physical transition spacing on the media so that pulses are widely separated at the outside diameter and crowded very close at the inner diameter of the recording surface (this is wasteful of the magnetic media which is only sparsely used at the outer

diameter). A practice known as zoned recording is a popular compromise between these two extremes. In zoned recording, a group of tracks (a zone) is established in which every track in the zone holds the same amount of data. Thus each zone requires a different data transfer rate, but the number of data transfer rates which need be supported is reduced (more coarsely quantized). This still leaves a variation in the physical spacing of transitions between the inside and outside diameters of each zone resulting in a variation in pulse shape.

Partial-response signaling has just recently been incorporated into mass storage devices and then in a limited form. One prior-art magnetic disk drive using partial-response signaling only supports PR4 (pulses with the samples of ..., 0, 1, 1, 0, ...). PR4

signaling has only very limited inter-symbol

interference evidenced by only two non-zero samples in the pulse. To increase the capacity of the media, the user of a PR4 read channel must increase the

equalization of the pulses (slim the pulses) in order to limit the inter-symbol interference of adjacent pulses so that any pulse only affects two read signal samples. The increased equalization also enhances the noise accompanying the signal, making the detection task more difficult and errors more likely. U.S. Patent 4,945,538 by Patel covers a similar situation but with EPR4 signaling and an RLL (1,7) code. This improves the allowed amount of inter-symbol interference, increasing it to three non-zero samples of (..., 0, 1/2, 1, 1/2, 0, ...). Both of these techniques will allow an increase in capacity but are limited in the variety of pulse shapes which can be detected and therefore limited by how much equalization (pulse slimming) may be performed before the effect of equalizing the noise (noise

enhancement) becomes intolerable.

Thus, there is a need for a flexible read channel which can accommodate a wide variety of pulse shapes as will be seen in each zone. There is also a need to allow larger amounts of controlled inter-symbol

interference between pulses (pulses with more than two or three non-zero pulses) in order to continue

increasing the capacity of the recording media. SUMMARY OF THE INVENTION

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL (1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment

incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 shows a state transition on a medium such as a track of a disk drive and its associated pulse in an analog read signal. It also shows two digitized sample models of such read-signal pulses.

FIGURE 2 shows two adjacent medium transitions and their individual and combined read-signal pulses.

Figure 3 is an overall block diagram of the present invention.

Figure 4 is a block diagram illustrating the details of the gain control circuit 32 of Figure 3.

Figure 5 is a block diagram illustrating the details of the timing recovery circuit 34 of Figure 3.

Figure 6 is a block diagram illustrating the details of the spectrum smoothing filter 42 of Figure 3.

DETAILED DESCRIPTION OF THE INVENTION

The CL-SH4400 is a specific embodiment of the present invention designed to work with a companion analog integrated circuit and a disk controller to form a state of the art high density magnetic disk drive. In that regard, the uniqueness of the present invention, while used in a digital read-write channel, is primarily related to its read capability and versatility.

The companion integrated circuit with which the CL- SH4400 is specifically intended to operate implements a VGA (Variable Gain Amplifier), a tunable analog filter, an analog to digital converter, a timing VFO (Variable Frequency Oscillator), write pre-compensation and servo demodulation functions. Accordingly, in a read

operation, the CL-SH4400 does not receive an analog signal but instead receives already digitized read information in the form of digitized analog read channel samples. Further, while the timing Variable Frequency Oscillator and the Variable Gain Amplifier are on the companion integrated circuit and are not part of the present invention, the timing VFO and the Variable Gain Amplifier are each digitally controlled through digital control signals generated in the CL-SH4400.

Accordingly, in the specific embodiment to be described, digital control feedback signals for both the VFO and the VGA are generated in the CL-SH4400 even though the control loops for the timing recovery and the automatic gain control functions are actually closed within the companion analog integrated circuit. In that regard, it should be particularly noted that the automatic gain control signal may alternatively be generated on the analog companion integrated circuit, as the same may be readily generated in the analog domain rather than in the digital domain. Accordingly, particularly the generation of the digital gain control to be described as part of the CL-SH4400 is an optional design choice readily relegated to the companion integrated circuit if desired.

Figure 3 provides a block diagram illustrating the general organization of the CL-SH4400. As may be seen in Figure 3, the digitized read data for the CL-SH4400 is provided in an N-bit parallel form as digitized read data DRD0 and DRD1. Each of these two signals in the preferred embodiment disclosed is a 6-bit digitized read data signal. These two N-bit signals represent

digitized samples of a read signal directly from a read head of the storage device after analog amplification and analog filtering. Those skilled in the art will recognize that the purpose of the analog amplifier and the analog filter is to scale the signals to the input range of the digital to analog converter and to

attenuate frequencies above the Nyquist frequency (1/2 the sample frequency) to avoid signal distortion due to aliasing. In general, the analog filter will perform pulse shaping as well. The digitized read data signal DRD0 is a digitized read signal sample effectively taken near the center of a channel bit time (defined by the VFO frequency), subject however to a small amount of timing error or intentional timing set point offset in the VFO. The digitized read data signal DRD1 is the corresponding digitized read sample effectively taken near the center time of the previous logical channel bit, subject of course to similar timing errors and timing set point offsets. These two digitized read data signals are processed in the CL-SH4400 in a parallel or simultaneous manner so that ultimately in the CL-SH4400, two successive bits of digital read data will be derived from one set of DRD0 and DRD1 signals which together with successive bit pairs are decoded by a run-length limited (RLL) decoder and derandomized if applicable (e.g. if initially randomized) to provide the NRZ data output stream of the device. The processing of two digitized read data samples simultaneously doubles the throughput of the CL-SH4400 for a given clock rate without doubling the circuitry required, particularly in the sequence detector, though the present invention is not specifically limited to processing of two digitized read data sample at a time. One could process one digitized read data sample at a time, or alternatively process more than two digitized read data samples at a time, if desired. In that regard, the number of N-bit digitized read data sample connections to the chip normally will equal the number of samples processed at a time, though such signals could be multiplexed so that the number of N-bit digitized read data samples

connections to the chip is less than the number of samples processed together.

In one mode of operation, multiplexer 28 couples the DRD0 and DRD1 signals directly to a transition detector 22 which processes the successive samples to detect the presence of transitions in each of the two digitized read data signals. The output of the

transition detector is a low or high level during the respective bit times (delayed as described in the copending application) depending upon whether a transition (providing a high level output) or no transition

(providing a low level output) was detected. The output of the transition detector 22, the peak detected signal PKDET, in this mode would be coupled to multiplexer 24 and through a sync mark detector 26 to provide a sync byte detected output SBD if a sync byte was in fact detected, and to couple the two bits to the RLL decoder 28 which decodes the bit stream to provide the NRZ data out digital data. In the preferred embodiment run length constraint violations are detected and optionally multiplexed onto the NRZ data out lines. These may be used by an error correcting system within the disk controller. In the preferred embodiment, an error tolerant sync mark detector 26 is used. This detector is designed to achieve a level of error tolerance for the synchronization function equal to that achieved for the data field by the error-correction code implemented in the disk controller. This is achieved in part by employing an error-tolerant Synchronization Mark pattern for minimum cross-correlation with the preamble and for minimum auto-correlation, and by making the number of four-channel-bit groups which must be detected

programmable. The synchronization mark recovery procedure may be used to recover data when a severe defect has destroyed the entire synchronization mark. When using this mode, the CL-SH4400 first goes through a normal timing and gain acquisition procedure while counting channel bits. The synchronization mark is assumed to have been detected when the count matches the synchronization mark recovery count. By varying the synchronization mark recount, the microcontroller can vary the assumed starting point of a header or data area until the correct starting point is tried, whereupon the sector will be recovered if there is no other error beyond the capability of the error correction code in the disk controller.

In the CL-SH4400, the NRZ data output is user selectable as a serial bit stream, a 2-bit parallel stream or character wide (8-bit wide) digital data. If the data was randomized prior to storage, the data randomizer 30 may be enabled to de-randomize the data from the RLL decoder 28 before being provided as the NRZ data output.

The output of the transition detector 22 in this mode is also provided to the gain control circuit 32 and the timing recovery circuit 34. Also the N-bit

digitized samples DRD0 and DRD1 are coupled through multiplexer 20 to the gain control circuit 22 and the timing recovery circuit 34. The gain control circuit 32 is shown in more detail in Figure 4. The gain errors (the difference between the programmable desired signal level referred to as the Gain Set point, and each digitized data signal) are determined for each digitized read data sample by the gain error circuit 33. The outputs PKDET of the transition detector 22 provide references to control the multiplexer 35 of the gain control circuit 32, as the gain adjustments are

determined by the signal amplitudes of transitions and not the signal levels between transitions. The

automatic gain control signal VGAC (5-bits in the preferred embodiment) for coupling back to the companion integrated circuit for analog amplifier gain control is provided by the digital gain loop filter 37. The gain loop filter includes a loop filter coefficient which is independently programmable for tracking and acquisition. The individual gain errors are also coupled to a channel quality circuit 46 as the signals GERR so that gain control performance can be measured to determine the best choice of loop filter coefficients and other parameters of the channel with respect to the

performance of the automatic gain control loop.

The timing recovery circuit 34 in the CL-SH4400 is shown in greater detail in Figure 5. Timing recovery and maintenance of synchronization, of course, can only be done upon the detection of a transition, as the absence of transitions contains no timing information. The timing recovery circuit controls the read clocks which are synchronized to the read wave form. In the timing recovery circuit, a phase detector 39 digitally computes the phase error in the sampling instants of the analog to digital converter on the companion chip from the digitized sample values during transitions, as indicated by the signals PKDET. Providing timing error corrections only at transition times reduces the noise (jitter) in the timing loop. The sequence of measured phase errors is digitally filtered by filter 41 to produce a frequency control signal which is fed back to the companion chip, in the preferred embodiment as the 5-bit frequency control signal FCTL.

The timing recovery circuit has two modes of operation, acquisition and tracking. The appropriate range and resolution of the frequency control signal FCTL to the analog companion part is not the same for the two modes. In the acquisition mode, the necessary frequency control range is larger (wider range of possible frequency settings) than in tracking.

Conversely, in tracking the required resolution (minimum step of frequency) is finer. To meet these conflicting requirements without unduly increasing the number of bits in the FCTL interface, the resolution and range are made to depend on the mode of operation, and a signal ACQ is used to communicate to the analog companion part which mode of operation is being used. When the

operating mode is switched from acquisition to tracking, the last frequency setting during acquisition is stored in the companion analog part and the value on the FCTL bus during tracking is taken as an offset from the stored setting. In the preferred embodiment (CL-SH4400) the range and resolution are decreased by a factor of 8 between acquisition and tracking.

The timing recovery circuit 34 also includes a programmable timing set point. The timing set point permits a wider range of sampling strategies which enables the support of a wider range of pulse shapes. The timing set point is useful on retry in the event of the detection of an uncorrectable error. Also the digital filter includes two coefficients which are independently programmable for acquisition and tracking. These are also usable in a retry strategy to change the bandwidth and hence the response time of the timing loop. Like the individual gain errors GERR, the individual timing errors TERR are also coupled to the channel quality circuit for contribution to the

quantitative analysis of the channel quality with respect to timing recovery. One alternate embodiment of the timing recovery block includes a frequency error detector. The frequency error detector is used to decrease the time required for the timing loop to lock to the channel bit frequency and phase during the acquisition period before encountering data.

As variations on the mode of operation just described, the two N-bit digitized read data signals DRD0 and DRDl may be passed through a pulse shaping filter 38 prior to being coupled to multiplexing block 20. The pulse shaping filter provides digital filtering at the cost of a small amount of delay with two user selectable coefficients PC1 and PC2, independently programmable in the filter structure. This pulse shaping filter, of course, is in addition to any

filtering done in the analog domain, and is an example of the flexibility and adaptability of the present invention. In particular, the effect of the pulse shaping filter may be eliminated by multiplexing block 20, or alternatively, the pulse shaping filter may be used with coefficients user selected, and thus variable, to provide the best performance of the overall storage system read channel with the flexibility to accommodate changes in pulse shape when changing from one recording zone to another, and to allow coefficient variations as part of overall device parameter variations for

systematic retries upon the detection of uncorrectable errors in the subsequent error detection and correction (EDAC) operations. The pulse shaping filter of the preferred embodiment is a finite impulse response digital filter which means that the output is a function of the current and past inputs but not a function of its own past outputs. The delays necessary for the filter to remember the past inputs are shared by delay 36 to provide a separate delay path to multiplexing block 20. The delay path through delay 36 provides an amount of delay equivalent to the delay of pulse shaping filter 38. Multiplexing block 20 is provided to give a maximum of flexibility in modes of usage, by providing a separate source of input for the transition detector and the group of blocks comprising the sequence detector 40 (by way of spectrum smoothing filter 42), the gain control circuitry 32 and the timing recovery circuitry 34. The multiplexing block is designed so that all blocks may operate upon the raw input samples provided by DRD0 and DRD1 , or alternatively the pulse shaping filter may be placed in one of the multiplexing block's output paths with the delay placed in the other path. The delay is necessary in this case so that the

transition detector's outputs are synchronized with the sample values reaching the gain control circuitry and timing recovery circuitry. Finally, the pulse shaping filter may feed both of the multiplexing block's output paths. In general the multiplexing block could be designed so that by programming the multiplexing block each block at the multiplexing block's outputs

(transition detector 22, gain control 32, timing

recovery 34, and sequence detector 40 by way of spectrum smoothing filter 42) could receive raw input samples, delayed raw input samples, or filtered input samples independent of the data received by the other blocks. In the preferred embodiment of the present invention however, the gain control circuitry and the timing recovery circuitry have the capability of compensating for the pulse shape in an effort to increase the

accuracy of the gain and timing recovery loops, and to reduce the amount of circuitry, the gain control circuitry and timing recovery circuitry assume the same pulse shape for which sequence detector 40 is

programmed. This basic pulse shape received by the sequence detector is only marginally affected by the addition of the spectrum smoothing filter, which is designed to reduce only the head bumps at the tails. of the pulse and does not seriously affect the center of the pulse except to correct for head bumps due to neighboring pulses. In that regard, the present invention includes a channel quality circuit 46 for measuring the quality of the read channel as earlier described. This provides not only quantitative channel evaluation, but in addition allows selection of read channel parameters such as, but not limited to, the coefficients PC1 and PC2 in the pulse shaping filter to best adapt the read channel to the characteristics of the storage medium and the pulse form and

characteristics being read therefrom.

The present invention further includes a sequence detector 40 which receives as its input the two N-bit digital read data signals DRD0 and DRD1 as may be modified by the pulse shaping filter 38 and as may be additionally modified by the spectrum smoothing filter 42. In that regard, the spectrum smoothing filter 42, as shown in Figure 6, contains two delays FD1 and FD2 and four coefficients SC1, SC2 , SC3 and SC4 , all of which are independently programmable. The delays may be programmed from 0 to 23 channel bit intervals. The entire spectrum smoothing filter, or just its precursor correcting portion 43, can be disabled. The spectrum smoothing filter is designed to reduce the undershoots from the finite pole tips of a thin film head, or to reduce the bumps from the secondary gap of a single or double-sided MIG head. In the frequency domain, the filter acts to smooth out undulations caused by head bumps. If the precursor is disabled, the delay of the filter is disabled, whereas if a head which is not subject to head bumps is used, the post-cursor may be disabled.

The pulse shaping filter and the spectrum smoothing filter together form a digital equalizer which can modify the equalization done in the analog filter of the companion integrated circuit, and along with the

companion integrated circuit provides support for changing equalization needs from head to head and zone to zone of the magnetic storage device. The parameters for the pulse shaping filter and the spectrum smoothing filter are loaded and/or varied by microcontroller 44 on initialization and during head seeks.

The sequence detector 40 is a partial response sequence detector. This allows the analog response of the read channel to a storage medium transition to overlap with the response to adjacent transitions associated with subsequent information bits. In

comparison to most prior art read channels for magnetic storage media, the use of a partial response detector allows higher information storage densities in

comparison to the prior art alternative of requiring the medium transitions to be sufficiently spaced from each other so that the read signal responses do not overlap significantly, thereby allowing each transition to be individually detected irrespective of the nearest neighboring transitions.

The particular sequence detector used in the present invention is a uniquely modified form of Viterbi detector which substantially preserves the full

performance of the Viterbi algorithm in a substantially reduced complexity sequence detector. The basic Viterbi algorithm is described in the book "Fast Algorithms for Digital Signal Processing" by Richard E. Blahut, 1985, pages 387-399. In accordance with the Viterbi

algorithm, a Viterbi detector does not attempt to decide whether a medium transition has occurred immediately upon receipt of the read sample or samples that

correspond to that transition. Rather, as samples are taken from the read signal, the Viterbi detector keeps a running tally of the error between the actual sample sequence and the sample sequence that would be expected if the medium had been written with a particular sequence of transitions. Such an error tally is simultaneously kept for several possible transition sequences. As more samples are taken, less likely choices for transition sequences are pruned from

consideration. If a set of possible sequences of medium transitions is appropriately constrained, then the location of each medium transition becomes known with a high degree of likelihood within a reasonable time after taking the samples corresponding to that transition. Because of the time delay between a sample acquisition and the determination of whether that sample represented a transition or an absence of a transition, the gain control circuit 32 and the timing recovery circuit 34 are both still referenced to the output of the

transition detector 22, which has a more immediate response to the occurrence of a transition. Also, while in general the output of the sequence detector, when used, should be more accurate in ultimately determining whether a transition occurred at a particular bit time, an error in the output of the peak detector will have little effect on gain and timing. Specifically, failure to detect a transition will only slightly delay gain control and timing error corrections, and an isolated false detection of a transition will only slightly perturb the gain control and timing accuracy. This should be more than made up by the increased accuracy of the bit stream detection by the sequence detector's consideration of what comes before and after a

particular digitized read data sample. If the present invention is realized in an

embodiment wherein digitized read data is processed a single bit time's worth at a time, a Viterbi detector of a conventional design may be used, or if two or more bit time's worth of samples are to be processed

simultaneously, as in the preferred embodiment of the present invention, a conventional Viterbi detector could be modified for that purpose.

In a typical Viterbi detector implemented using the ADD, COMPARE, SELECT (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path metric. In the sequence detector used in the preferred embodiment, an ACS module may have two or more sequence model states dynamically associated with it such that at some times, one sequence model state is associated with it, and at other times, another sequence model is associated with it. This reduces the number of ACS modules required and also reduces the size and complexity of the detector path memories which must store one path for each ACS module. Groups of sequence model states may be chosen to share an ACS module without significant loss in performance as compared to the conventional Viterbi detector. These detectors support a wide range of sample models by making the expected sample sequence of an isolated medium

transition programmable through control 44. By way of specific example, the sequence detector used in the CL- SH4400 disclosed herein will support the PR4 , EPR4 and EEPR4 sample models, among others. In addition, the alternating polarity of pulses is enforced, as is a minimum run length constraint of d=1.

The d=1 constraint in the RLL(d,k) coding is an important constraint in the present invention, especially for applications where the storage system uses thin-film magnetic media. For thin-film magnetic media, there is an effect known as partial erasure which puts a practical limit on how close two magnetic transitions may be written. The effect is due to a ragged (or zig-zag) boundary between regions of opposite magnetization. As the transitions become too close, the zig-zags begin to overlap and the area of opposite magnetic polarity between two transitions starts to disappear. The result is that as the read head flies over the partially erased transitions, the amplitude of the corresponding read signal pulses is diminished.

This is a non-linear, data pattern dependent effect which is difficult to compensate for. The d=1

constraint remedies this situation by preventing magnetic transitions in two consecutive channel bit times. The drawback is that the d=0 constrained code may typically represent 8 NRZ bits with 9 RLL bits (rate 8/9) while the d=1 constrained code can only represent 6 NRZ bits with 9 RLL bits (rate 2/3). For example, to store 8 NRZ bits, the d=0 constrained code will store 9 channel bits while the d=1 constrained code will store 12 channel bits in the same amount of space, hence the d=1 channel bit interval is 3/4 the size of the d=0 channel bit interval. Fortunately, the magnetic

transitions have a minimum spacing of 2 channel bits and therefore the minimum distance between two transitions has increased by 3/2 with respect to the corresponding d=0 constrained code. This makes the d=1 constrained read channel a good solution for increasing storage capacity in applications where the minimum transition spacing is close enough for partial erasure effects to be noticeable.

The sequence detector utilized in the CL-SH4400 can be programmed to operate on any channel response which can be well represented by sequences in the form of a, b, 1, c wherein the selection of a, b and c allow the ability to accommodate pulse asymmetry which might otherwise require that the read signal pass through an analog or digital phase equalizer prior to entering the sequence detector. The levels a, b and c also give the ability to select between center and side sampling.

Center-sampled pulses are notably those for which the sample levels a, b, 1, and c are selected such that 1 is very near the peak of the pulse, b and c are roughly halfway down their respective sides of the pulse, and a is near zero, for example, the sample levels 0, 1/2, 1 and 1/2. Side-sampled pulses are notably those for which the sample levels are selected such that 1 and b (which is about 1) straddle the peak of the pulse, for example the sample levels 5/16, 1, 1 and 5/16. This choice of side versus center sampling also affects the manner in which gain error and phase error are

calculated in the gain control loop and timing recovery loop. The option to choose between side and center sampling allows the user a wider range of possible trade-offs between the amount of equalization

(filtering) used to shape the raw pulse shape into the target pulse shape of the sequence detector and the amount of noise enhancement which arises as a

consequence of shaping the raw pulse. Hence the read channel can be more suitably matched to the storage medium to provide better performance.

Referring again to Figure 3, for writing

information to the storage medium, the NRZ input data is provided to a run length limited encoder 48, in the CL- SH4400 through a user selectable serial line, a two bit parallel form or an eight bit byte parallel form. The run length limited encoder provides the desired run length limited coding, in the preferred embodiment an RLL (1,7) coding, randomized before encoding or not, depending upon the enabling of the data randomizer 30, with the encoded data being provided to multiplexer 52, in the preferred embodiment in a two-bit wide form. In the case of writing to the storage medium, the serial enable signal SER_ENA will be deasserted so that the multiplexer 50 and 52 will provide the encoded data bits 1 (the most significant of the two parallel data bits) and 0 (the least significant of the two parallel data bits) to the companion integrated circuit to write the same to the storage medium.

When not writing, the serial enable signal SER_ENA may be asserted, at which time multiplexers 50 and 52 are switched so that serial control address and data may be transferred on the SER_DAT line to the companion integrated circuit synchronous with the associated serial clock signal SER_CLK as the output signals of the two multiplexers 50 and 52. Multiplexing of these two chip pins of the single chip CL-SH4400 integrated circuit helps reduce the pin count without loss of performance or flexibility. This serial interface is provided to eliminate the need for the companion

integrated circuit to interface with the bus of the microprocessor and eliminates a potential coupling between the noisy microprocessor bus and in the

sensitive analog circuitry of the read channel in the companion integrated circuit. This also provides a benefit in pin count since the microprocessor bus interface would require numerous additional pins on the companion integrated circuit. Each of the control registers of the companion integrated circuit are mapped to corresponding register addresses in the integrated circuit of the present invention, when one of these registers is written to, the serial interface initiates a serial transfer write operation, sending the data to the appropriate register in the companion integrated circuit. The preferred embodiment of the present invention includes two modes, one in which a status bit which can be read to determine whether or not the serial transfer write operation is complete and another in which the integrated circuit of the preferred embodiment forces the microprocessor to pause while the serial transfer write operation is in progress. Similarly, a read of a register in the companion integrated circuit is performed by reading the corresponding register in the integrated circuit of the present invention. This initiates a serial transfer read operation. In the first of two serial interface read modes, the integrated circuit of the preferred embodiment will signal the microprocessor to pause until the serial transfer read operation is complete at which time the serially

transferred data will be accessible at the pins of the integrated circuit of the present invention. In a second mode, the integrated circuit of the preferred embodiment will return the data left over from the previous serial transfer read operation, and once the current read operation is completed, it will initiate a new serial interface read operation with the address just supplied. The preferred embodiment includes a status bit which can be read to determine whether or not the new serial transfer read operation is complete.

Once complete, the microprocessor may initiate a second read operation to retrieve the data originally desired and to initiate another serial transfer read operation at a new address for future use if desired. Summarizing the two modes, in one mode the microprocessor is made to wait, in the second mode the microprocessor must read the register twice, once to supply the register address and second time to retrieve the data and possibly supply the next register address.

Another embodiment of the present invention, namely part number CL-SH3300 integrated circuit, incorporates the essential functions of the CL-SH4400 and the companion integrated circuit in a single integrated circuit.

In the embodiments hereinbefore described, numerous parameters were described as being programmable, and as such, as being useful for varying on retries in the event of the detection or repeated detection of an uncorrectable error. Obviously additional programmable or fixed parameters may also be incorporated, such as by way of example, additional filter coefficients in the pulse shaping and other filters. It should be noted that particularly certain parameters, such as the parameters of the pulse shaping filter 38 and the spectrum smoothing filter 42, may be made adaptive, or a combination of adaptive and programmable. By way of example, coefficients may be made adaptive, while the time constants of the adaptive characteristics and perhaps offsets, wave shapes, asymmetries and

compensation for nonlinearities are made programmable. In that regard, it should be noted that given an

uncorrectable or repeated uncorrectable error, there is no harm in further attempts at a successful read with different parameters, side versus center sampling, filtering versus different, less or no filtering, etc. Further, normally one would use the sequence detector on read for its superior detection capabilities over a peak detector. However in the case of hard errors wherein the errors in the output of the sequence detector exceed the error correction capability of the EDAC code used, a further retry strategy may include switching to an output derived from the peak detector, as previously described, rather than the sequence detector. This will add noise errors characteristic of transition detection effectively within the single bit-time of the possible transition, but will eliminate whatever

additional propagation of the hard errors (for example media defects) may be caused by the sequence detector. The effect of the noise errors may be substantially eliminated by multiple reads, followed by a majority vote to cancel all or most of the effect of the noise errors, yielding an opportunity for a successful error correction when the same could not be achieved with the sequence detector in the path. Here again, pulse shaping filter characteristics may be varied and multiple retries of the peak detector multiple reads executed, as reasonable exhaustion of all opportunity for a successful read is better than a fatal error.

There have been disclosed and described herein preferred and alternate embodiments of a new and unique synchronous read channel which include a sequence detector with a flexible architecture capable of implementing a broad range of partial response

polynomials. While an embodiment of the present invention which supports only one or two partial response channels would be highly useful, the detector used in the preferred embodiment of the present

invention supports a broad class of partial response channels, including but not limited to PR4 (1,7), EPR4 (1,7) and EEPR (1,7). While the sequence detector is normally operative upon a read, the output of a digital peak detector may be enabled as the output of the read channel if desired. These and other inventive features of the invention will be apparent from the preceding description.

Thus while a preferred and alternate embodiments of the present invention has been disclosed and described in detail herein, it will be obvious to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope thereof.

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BACKGROUND OF THE INVENTION

In a computer data storage device, data is typically stored on magnetic media by reversing the magnetic flux at each "one" bit location, and maintaining the same flux direction at each "zero" bit location, called NRZI recording. When these flux reversals pass a read head they cause a voltage change in the read head. The voltage from the various flux reversals along a data track appears as a varying signal level on the output of the read head, with the voltage caused by each flux reversal appearing as a positive or negative voltage pulse. These pulses must be detected by the electronics connected to the read head, typically by detecting the peak of each pulse to determine the pulse location.

Similarly, the voltage from a data transmission line appears as a varying signal level on the input to a data communication device, such as a modem, with the voltage of each bit change often appearing as a positive or negative voltage pulse.

In order to separate the voltage pulses from noise in the signal, the voltage may be compared to a predetermined threshold, and only peaks whose magnitude exceeds the threshold are considered to be possible pulses. If the peaks are too small with respect to the threshold, the signal gain must be adjusted higher, and if the peaks are too high the gain must be adjusted lower. To properly determine the gain setting, pulses must be detected so that the gain adjustment can maintain the proper level for a pulse peak.

Because the rotational speed of a disk may vary, a phase locked loop is used to synchronize a detector to the times of the pulses. The peaks of the pulses Caused by bit transitions must be detected in order to correct for any timing deviations.

Several methods have been used to detect the pulses and thus the transitions within the data. In the prior art, peak detection circuitry has ordinarily been analog in nature, while digital detectors have ordinarily been sequence detectors such as those implementing the Viterbi method, disclosed in Application Serial Number 07/852,015, filed March 16, 1992, of Richard T. Behrens, Kent D. Anderson and Neal Glover, entitled "Method and Apparatus for Reduced-Complexity Viterbi-Type Sequence Detectors", which is incorporated herein by reference for all that is disclosed and taught therein. However, most digital pulse detectors analyze the context of the pulses, and do not detect a pulse until several samples have been taken beyond the peak of the pulse. This latency in detecting pulses is a disadvantage when the location of a pulse needs to be known in order to make timing and/or gain corrections.

It is thus apparent that there is a need in the art for an improved apparatus which digitally detects pulses at the earliest possible time after the peak of the pulse occurs. The present invention meets these and other needs.

SUMMARY OF THE INVENTION

It is an aspect of the present invention to detect signal pulses caused by bit transitions within data being read from a data storage device.

It is another aspect of the invention to detect signal pulses within signals received by a data communications device.

It is another aspect of the invention to detect the pulses using samples of the signal wherein one of the samples occurs at a peak of the pulse caused by a bit transition.

Another aspect of the invention is to detect such pulses using samples of the signal wherein samples occur on each side of a peak of the pulse and wherein no sample occurs at the peak.

A further aspect is to detect a pulse within one half to one and one half sample periods from the peak of the pulse.

A still further aspect is to use signal level moving averages of two samples for detection.

The above and other aspects of the invention are accomplished in a digital pulse detector that uses four samples of a read signal to detect a data transition as soon as one sample beyond the time of the peak of the signal level at the bit transition. The pulse detector detects peaks by sampling at the center of the peak or by sampling at each side of the peak. The pulse detector detects pulses while tracking, where the pattern of pulses is not known in advance, or while acquiring timing lock on the signal in a preamble, where the data pattern is fixed. Thus the pulse detector provides four combinations of detection to detect in tracking or acquisition mode, using either center or side sampling in either mode. The detection rules are summarized in Table 2.

In an alternative embodiment, the detector uses a moving average of two adjacent samples, as well as individual sample signal levels, to perform the detection. The alternative embodiment uses the sampled signal levels directly to determine peaks in side sampled acquisition mode, and in center sampled tracking mode. In the other two of the combinations, the alternative embodiment detector uses two-sample moving averages to determine peaks. The preamble pattern for acquisition in the alternative embodiment is restricted to be a repeating sequence of alternating polarity pulses with a period of four sample intervals. This is more restrictive than the pattern handling capability of the first embodiment, however, it permits the alternative embodiment to perform earlier detection of the pulses in the side sampled acquisition case and it uses simpler rules in acquisition. The detection rules for the alternative embodiment are summarized in Table 1.

Both embodiments avoid using a signal threshold to qualify the pulses during acquisition. This aspect prevents the gain at the beginning of the acquisition from affecting acquisition, since the gain may be incorrect at the beginning of acquisition. During tracking, where the pulses may be more widely separated, a threshold is used to qualify pulses. This qualification prevents the detection of small noise-induced pulses as data pulses. BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of the invention will be better understood by reading the following more particular description of the invention, presented in conjunction with the following drawings, wherein:

Fig. 1 shows a block diagram of the invention and the environment of the invention;

Fig. 2 shows a block diagram of the circuitry that provides data samples to the invention;

Fig. 3 shows a block diagram of the digital circuitry of the read channel containing the invention;

Fig. 4 shows a signal waveform and illustrates center sampling of the pulses;

Fig. 5 shows a signal waveform and illustrates side sampling of the pulses;

Figs. 6, 7, and 8 show a high-level logic diagram of the pulse detector of the present invention for the equations of

Table 1; and

Figs. 9, 10, and 11 show a high-level logic diagram of the pulse detector of the present invention for the equations of Table 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The following description is of the best presently contemplated mode of carrying out the present invention. This description is not to be taken in a limiting sense but is made merely for the purpose of describing the general principles of the invention. The scope of the invention should be determined by referencing the appended claims.

Fig. 1 shows a block diagram of the invention and a typical environment of the invention. Referring now to Fig. 1, a computer system 100 contains a processing element 102 which communicates to other elements of the computer system 100 over a system bus 104.

A keyboard 106 and a display 108 allow a user of the computer system 100 to communicate with the computer system 100. A memory

110 contains programs and data which cause the computer system 100 to perform operations desired by the user.

A disk data storage system 112 is connected to the system bus

104 for storing data and programs within the computer system 100.

A disk controller 114 within the disk device 112 communicates to the system bus 104 and controls the operations of a disk drive 118, possibly in conjunction with a local microprocessor (not shown) within the disk data storage system 112. The disk drive 118 performs the storage function, typically storing the data on magnetic media. A bus 116 connects the disk controller 114 to the disk drive 118, specifically connecting to a write channel 120 to write data onto the disk through write heads and amplifiers 128.

When data is being read from the disk through the read head and amplifiers 128 the data comes back through the read channel 122 which contains the pulse detector of the present invention. The read and write heads may be physically the same heads. The data first passes through the analog section 126 of the read channel 122 and then through the digital section 124 of the read channel 122 before being sent on the bus 116 to the disk controller 114. After being processed by the disk controller 114, the data is then sent over the system bus 104 to the memory 110 where it is processed.

The disk controller 114 also connects to other circuits, not shown, within the disk drive 118, such as a circuit which moves the read/write heads over the surface of the data storage media.

Although not shown in Fig. 1, the pulse detector of the present invention can be used to detect pulses within data received from a transmission line, such as a telephone line or local area network, in a data communications receiver. It may also be used in any other device that must detect pulses within a signal.

Fig. 2 shows a block diagram of the analog circuitry 126 of the read channel 122. Referring now to Fig. 2, when a read head is passing over a track of the data storage medium, it picks up a signal which is amplified by a preamplifier, not shown. After this preamplification, the signal 201 is passed to a variable gain amplifier 202. The signal is further amplified by the variable gain amplifier 202 and passed through an analog equalizer circuit 204, which filters the signal as desired, for example, so as to remove unwanted high frequencies and shape the remaining spectrum, to an Analog to Digital converter 206. The A to D converter 206 converts the analog signal into a digital value, providing six bits of digital information in the preferred embodiment, and then the data is passed to a register/de-multiplexer 207. In the preferred embodiment, the digital section 124 of the read channel 122 processes two samples in parallel. To create these two samples, the register/de-multiplexer 207 stores every other sample taken by the A to D converter 206. After the second sample is taken, the data from the two samples is passed to the data bus 230. The bus 230 is clocked by a single half-frequency clock signal.

The timing necessary for converting the data, also called taking a sample, in the A to D converter 206 is supplied by a variable frequency oscillator 222 which is controlled by the output of a digital to analog converter (DAC) 220. The input to the DAC 220 comes from the digital section of the read channel 124 as timing feedback signal 234.

The gain of the variable gain amplifier 202 is controlled through a gain feedback signal 232 which originates in the digital portion 124 of the read channel 122. The gain feedback signal 232 is input to a summing junction 210 which has a coarse gain control value as its other input. The coarse gain control can be set by the disk controller 114, or a local microprocessor within the disk drive (not shown), to provide a nominal gain level which is then adjusted up or down by the gain feedback signal 232. After being summed with the coarse gain control value, the feedback signal is sent to a digital to analog converter 212 and then to a filter 214. Because of the nature of digital to analog converters, the output of the DAC 212 may contain glitches when it iβ changing values.

Therefore, the filter 214 may be necessary to remove these glitches in the feedback signal. After being filtered, the signal is converted to an exponential value by the exponential converter block 216 and then connected to the variable gain amplifier 202.

This conversion makes the small-signal gain control dynamics independent of the input signal amplitude.

Fig. 3 shows a block diagram of the digital section 124 of the read channel 122 (Fig. 1). Referring now to Fig. 3, the digital data signal 230 from Fig. 2 is input to a delay circuit 304 and a digital filter circuit 302. The digital data signal 230 is also input to a multiplexer 306 whose output is connected to a second multiplexer 310 with an output that feeds the pulse detector 312 of the present invention. The output of the pulse detector 312 is connected to a gain control circuit 330 which provides the gain feedback signal 232 that connects to Fig. 2. The output of the pulse detector 312 is also connected to a timing recovery circuit 328 whose output 234 connects to the digital to analog converter 220 of Fig. 2. The output of the pulse detector 312 of the present invention may also be connected to a sync mark detector 322 and an RLL decoder 320, as shown in Fig. 3, or a more sophisticated data detector (not shown) may be connected to the sync mark detector 322 and the RLL decoder 320. The output of the RLL decoder 320 and the sync mark detector 322 are connected to the disk controller 114 (Fig. 1) through the bus 116.

The pulse detector 312 of the present invention is designed to detect pulses using one of two types of sampling methods, selected by the user. The first detection method is called center sampling wherein one of the samples taken will arrive at or very near the center, or peak, of a pulse. The location of the sampling is controlled by the timing recovery block 328 of Fig. 3. In the other method of sampling, called side sampling, the timing recovery block 328 will adjust the timing of the VFO 222 (Fig. 2) such that two samples are taken wherein one of the two samples appears on one side of the peak of the pulse and the other of the two samples appears on the other side of the peak. The user of the system determines whether center sampling or side sampling is used by setting a bit in a control register through the interface 116 (Fig.

1).

For either center or side sampling, sampling can occur at two different times within a data record being read from the disk media. The first time sampling occurs is called acquisition, because it occurs when the gain control and timing control are acquiring the gain and timing relationships of the pulses. This occurs when the read head is passing a preamble portion of the data record which always has a known data pattern to facilitate acquisition of the timing and gain. When data is being transferred, a different mode is used for the pulse detector, called tracking, since data has an irregular and a priori unknown pattern of pulses.

Therefore, the pulse detector of the present invention is designed to detect pulses under four separate conditions. The first condition is acquisition mode using side sampling, the second is acquisition mode using center sampling, third is tracking mode using side sampling, and fourth is tracking mode using center sampling.

The pulse detector analyzes the current sample of the amplitude of the signal as well as the previous three samples of the signal amplitude. Using these four samples, Table 1 shows equations for one embodiment of the pulse detector, and Table 2 shows equations for another embodiment.

In Table 1, y_n is the current sample, y_n-1 is the first previous sample, and y_n-2 is the second previous sample. The third previous sample is used only through the moving averages, (1+D)/2 (described below). The equations of Table 1 will be further described below with respect to Figs. 5 and 6. Also, the equations of Table 1 show pulse detection of a pulse whose peak occurs at time y_n-1 for center sampling, or between y_n-1 and y_n-2 for side sampling tracking mode, or between y_n and y_n-1 for side sampling acquisition mode. The circuits of Figs. 6-8 processes two signal samples simultaneously. The equations for the second sample are the same as the equations of Table 1, with one time delay. Thus, for example, y_n in Table 1 would be replaced by y_n-1, y_n-1 would be replaced by y_n-2, and y_n-2 would be replaced by y_n-3.

Fig. 4 shows a signal waveform of an isolated pulse and illustrates center sampling of the pulse. Referring now to Fig. 4, a signal waveform 402 is shown having a positive level above a baseline 404. Four samples of this waveform have been taken with the sample identified by reference 412, y_n, being the most recent sample. Sample 410, y_n-1, is the sample just prior to the most recent sample, sample 408 is the next previous sample and sample

406 is the oldest of the four samples shown. A threshold value 414 is also shown and the signal value of sample 410 must be greater than the threshold 414 for the pulse to be detected in tracking mode. Negative pulses would appear as a mirror image of Fig. 4.

Fig. 5 shows a signal waveform of an isolated pulse and illustrates side sampling of the pulse. Referring now to Fig. 5, a signal waveform 502 is shown as a positive level above a baseline 503. Four samples are shown, with the most recent sample being sample 510. Sample 508 is the sample previous to the most recent, 506 is the next previous sample and sample 504 is the oldest of the four samples shown. These samples are also identified by the reference y_n through y_n-3. Also, a threshold 512 is illustrated, and sample (y_n-1 + y_n-2) / 2 must be greater than the threshold 512 to be considered a pulse during tracking.

Figs. 6, 7, and 8 show a high-level logic diagram of the pulse detector 312 of the present invention. Referring now to Figs. 6, 7, and 8, signals 610 and 632 are received from the register/demultiplexer 207 of Fig. 2 through digital data signal 230. As discussed above with respect to Fig. 2, the analog section 126 sends two samples at a time to the digital section. Signal 610, also designated y_n, is the digitized value for the signal level of the most recent sample. Signal 632, also designated y_n-1, is the digitized value for the signal level of the next prior to the most recent sample. In the preferred embodiment, these two signals are each six bit digital values stored in two's compleinent number representation, with one of the bits being the sign bit. Signal 610 is fed to a multiplexer 608 and signal 632 is fed to a second multiplexer 640. These multiplexers are controlled by an exclusive-OR gate 606 which has two signals 602 and 604 as its inputs. Signal 602 determines whether the pulse detector is in acquisition or tracking mode, as described above, and signal 604 determines whether the pulse detector is in center or side sampling mode, as discussed above. When the pulse detector is in acquisition and side sampling mode, or the pulse detector is in tracking and center sampling mode, signals 610 and 632 will be selected by the multiplexers 608 and 640 respectively. When the pulse detector is in acquisition mode center sampling or in tracking mode side sampling, the multiplexers 608 and 640 will select signals 631 and 639 respectively.

Signal 631 is called a (1+D)/2 signal and is formed by adding signal 610 to signal 632 in summing junction 628 and then dividing this sum by two with a divide by two circuit 630 to produce signal 631. The summing junction 628 is a six bit add circuit and the divide by two circuit 630 is a shift. The signal 631 represents the sum of the y_n signal and y_n-1 divided by two, therefore, it is the average of y_n and y_n-1.

Circuits 634, 636, and 638 produce a (1+D)/2 signal for the previous samples. That is, delay circuit 634, which is a set of D flip flops, is used to delay the y_n signal 610 by one clock cycle (two sample times), so it becomes signal y_n-2, which is sent to the summing junction 636. Summing junction 636 sums y_n-2 with y_n-1 and divides the result by two to produce the average at signal 639. As disclosed in Table 1, these (1+D)/2 signals are used in two of the four cases that the pulse detector can decode.

After passing through multiplexer 608, y_n signal 610 is sent to Figs. 7 and 8 over y_n signal 613. This signal is also delayed by delay circuit 617 to become y_n-2 signal 614. In addition, y_n signal 613 is connected to a sign-bit circuit 616 which extracts only the sign-bit from the six-bit digital value. This sign-bit is connected to an exclusive-OR circuit 618 along with the other bits of the digital value 613. Also, the sign-bit 616 is connected to another summing junction 620 along with the output of the exclusive-OR circuit 618 and a threshold value 656. The circuits 616, 618, and 620 convert the value of y_n to an absolute value, that is, y_n is negated if it was originally a negative value to produce a positive value and is unchanged if it was originally a positive value. The threshold signal 656 is then subtracted from the absolute value to produce a non-negative value if the absolute value of y_n is greater than or equal to the threshold. The summing junction 620 produces a negative value if the absolute value of y_n is less than the threshold 656.

The output of the summing junction 622 is passed to another sign-bit circuit 624 which extracts the sign bit from the result and inverts it. This will indicate whether the absolute value of y_n is greater than or equal to the threshold value 656. The inverted sign-bit is then sent through a delay circuit 626. The output signal 627 of the delay circuit 626 has a value of one if the absolute value of y_n delayed by one clock cycle, that is, |y_n-2|, is greater than or equal to the threshold value, and is zero if it is less than the threshold.

In a similar manner, y_n-2 signal 642 is sent to a sign-bit circuit 644, an exclusive-OR circuit 646, and a summing junction

648. The output of the summing junction 648 indicates whether the absolute value of the y_n-1 signal is greater than or equal to the threshold value 656. This result is passed through a sign-bit circuit 650 and then inverted to indicate whether the absolute value of y_n-1 is greater than or equal to the threshold value 656.

Fig. 7 shows a high-level logic diagram of the section of the pulse detector 312 that detects pulses during data tracking. Referring now to Fig. 7, comparator circuits 702 and 704 compare the results of the last three samples taken of the signal. Y_n signal 613 is the most recent sample, y_n-1 signal 642 is the previous sample, and y_n-2 signal 614 is the sample prior to signal 642. The outputs of the comparator 702 and 704 are connected to a number of AND gates and delay circuits to implement the tracking equations shown in Table 1.

AND gate 706 determines whether a positive pulse is detected at time n (with the peak at time n-1). Output 736 of comparator 702 is a logical one if y_n-2 is less than y_n-1, and output 740 of comparator 704 is a logical one if y_n is less than y_n-1. These signals are ANDed together with the inverted sign of the signal level of y_n-1 to produce a logical one from AND gate 706 if a positive pulse has been detected at time n.

AND gate 708 determines whether there is a negative pulse at time n (with the peak at time n-1). Output 738 of comparator 702 is a logical one if y_n-1 is less than y_n-2, and output 742 of comparator 704 is a logical one if y_n-1 is less than y_n. These signals are ANDed together with the sign of y_n-1 to produce a logical one from AND gate 708 if a negative pulse is detected at time n.

AND gates 716 and 718 determine whether a pulse is detected at time n-1 (with the peak at time n-2). Output 736 of comparator 702 indicates that y_n-2 is less than y_n-1. Output 740 of comparator 704, after being delayed by delay circuit 710, indicates that y_n-2 is less than y_n-3. Signal 744 indicates that y_n-2 is negative, therefore, the ANDing of signals 736, 748, and 744 indicate there is a negative pulse detected at time n-1.

Signal 738 indicates that y_n-2 is greater than y_n-1. Signal 746, the output of delay circuit 712, indicates that y_n-2 is greater than y_n-3. By ANDing signals 738, 746, and the inverted signal 744, AND gate 718 indicates that a positive pulse is detected at time n- 1.

The output of OR gate 714 indicates that a pulse, either positive or negative, is detected at time n, and the output of OR gate 724 indicates that a positive or negative pulse is detected at time n-1. AND gate 720 determines whether the magnitude of the pulse at time n was greater than the threshold value and it also determines whether the pulse detector is in tracking mode. AND gate 726 determines whether the pulse at time n-1 was greater than the threshold and whether the detector is in tracking mode.

Because of the recording code used in writing data to the storage media in this application, a pulse can never occur at time n and also at time n-1. Therefore, the outputs of and gates 720 and 726 are cross-coupled to AND gates 728 and 730 to prevent detection of pulses in both locations at once. Thus, the output of gates 728 and 730 will indicate that a pulse occurred either at time n or at time n-1 but not both. These outputs are connected to the circuit of Fig. 8.

Fig. 8 shows a high level logic diagram of the portion of the pulse detector that implements the acquisition equations shown in Table 1 for acquisition mode. Referring now to Fig. 8, signal 602 indicates whether or not the detector is in acquisition mode. Sign-bit extractor circuit 802 and sign-bit extractor circuit 804 extract the sign bits from the values y_n and y_n-1 respectively. These two sign bits are exclusive NORed in XNOR circuit 808, whose output indicates whether the sign of y_n is equal to the sign of y_n-1. Circuit 810 indicates whether the sign of y_n-1 is not equal to the sign of y_n-2. If both these conditions are true, the output of AND gate 816 will indicate that a pulse is detected at time n (with the peak between time n and time n-1) in acquisition mode. This output is ORed with output 732 from Fig. 7 which indicates whether a pulse is detected at time n in tracking mode, therefore, signal 824 indicates whether a pulse is detected in one of the modes at time n.

The sign-bit output of circuit 804 is delayed one clock cycle to indicate the sign of signal y_n-3. This signal is exclusive ORed with the sign bit of y_n-2 by circuit 814, whose output indicates whether the sign of y_n-2 is not equal to the sign of y_n-3. The output of exclusive-OR circuit 810, after being inverted at the input of AND gate 818, indicates whether the sign of y_n-1 is equal to the sign of y_n-2. Therefore, the output of AND gate 818 indicates whether a pulse is detected in acquisition mode at time n-1 (with the peak between time n-1 and time n-2). This output is ORed with the output 734 of Fig. 7, which indicates whether a pulse is detected in tracking mode at time n-1. Therefore, output 826 indicates whether a pulse is detected at time n-1, either in acquisition or tracking mode.

Figs. 9 through 11 show a circuit that implements the equations of Table 2. This circuit, and the equations of Table 2, provide an implementation of the pulse detector that allows the preamble section of the data to contain different types of patterns. For example, the circuit of Figs. 6-8 works well for a preamble having a 2T pattern, which is an alternating 1-0 pattern (10101010...), where a 1 indicates presence of a pulse, a zero indicates absence of a pulse, and pulses alternate in polarity. The circuit of Figs 9-11 allows a 2T pattern, a 3T pattern (100100...), and an 4T pattern (10001000...). Thus, the circuit of Figs. 9-11 and equations of Table 2 are the preferred embodiment and the best mode. In all cases except side sampling acquisition mode, the equations of both Tables 1 and 2 detect pulses with the same latency. For side sampling acquisition, the equations of Table 1 detect peaks one sample sooner that the equations of Table 2. However, the equations of Table 2 are consistent in the amount of latency in both acquisition and tracking modes, while with the equations of Table 1 for side sampling, the latency in acquisition mode is one sample shorter than the latency in tracking mode.

The equations of Table 2 show detection of a pulse at time y_n. As with the circuits of Figs. 6-8, the circuit of Figs. 9-11 processes two signal samples simultaneously. The equations for the second sample are the same as the equations of the first sample shown in Table 2, with one time delay. Thus, for example, y_n in Table 2 is replaced by y_n-1, y_n-1 is replaced by y_n-2, etc., for the second sample.

Referring now to Figs 9-11, Fig. 9 shows a series of comparators, 912-922, that compare the values of y_n, y_n-1, y_n-2, and y_n-3, and compares y_n and y_n-1 to the threshold value. Most of the comparators have a delay circuit, 924-938, on their output to also provide a comparison of y_n-2, y_n-3, y_n-4, and y_n-5. These circuits thus provide all the inputs necessary for the equations of Table 2, and the equivalent equations for the second sample as discussed above.

Fig. 10 implements the equations of Table 2 for the current sample, and Fig. 11 implements the equations of Table 2 for the first previous sample. Therefore, in the following description. Figs. 10 and 11 will be described together.

In Figs. 10 and 11, NOR circuits 1002 and 1102 determine if the absolute value of the signal is greater than the threshold. As shown in Table 2, this comparison is done in tracking mode, but not in acquisition mode. Multiplexers 1020 and 1120 select side or center sampling mode. Multiplexers 1008 and 1108 select positive or negative pulses in center sampling mode, and multiplexers 1018 and 1118 select positive or negative pulses in side sampling mode. NAND circuits 1004, and 1104 implement the equations for center sampling positive pulses, and NAND circuits 1010 and 1110 implement the equations for center sampling negative pulses. Multiplexers 1006, 1106, 1012, and 1112 allow a user to select one of two equations during center sampling. These equations are shown in Table 2, equation 3, for positive and negative pulses of center sampling. This provides flexibility to the user of the circuit. NAND circuits 1016 and 1116 implement the equations for side sampling, positive pulses, and NAND circuits 1022 and 1122 implement the equations for side sampling, negative pulses. Condition 3 of Table 2 may be omitted during tracking mode when condition 4 is used.

Because data recorded on a magnetic storage medium is recorded using small magnets having alternating north-south poles, the signal detected by the read head will always have alternating positive and negative pulses. Therefore, for detecting signals read from a magnetic recording medium, the equations of Tables 1 and 2 could be easily modified to detect a pulse only if the pulse is opposite in polarity to the previous pulse detected. This could provide additional noise immunity.

Having thus described a presently preferred embodiment of the present invention, it will now be appreciated that the aspects of the invention have been fully achieved, and it will be understood by those skilled in the art that many changes in construction and circuitry and widely differing embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the present invention. The disclosures and the description herein are intended to be illustrative and are not in any sense limiting of the invention, more preferably defined in scope by the following claims.

Claims

What is claimed is:

1. An integrated circuit synchronous read channel for receiving digitized read signals representing samples of a read signal of a magnetic storage device and recovering digital data represented thereby

comprising:

a transition detector for detecting amplitude pulses of the digitized read signals indicative of storage media transitions and for generating an output signal representative of the amplitude pulses, said output signal being a sequence of binary digital

signals;

timing recovery circuitry responsive to the

digitized read signal and the output signal of the transition detector to provide a timing control signal for controlling the timing of digitized samples of the read signal;

a sequence detector responsive to the digitized read signals for receiving as stream of the digitized read signals and determining a corresponding sequence of binary digital signals likely to be represented thereby, said sequence detector including a path memory means for constructing sequences of binary digital signals, a comparison means for comparing the received read signal to a set of predetermined ideal read signals, and a selection means for selecting one of said set of ideal read signals which resembles the received read signal and for selecting a sequence of binary digital signals from the path memory means which corresponds to the selected ideal read signal;

an RLL (d,k) decoder for providing a run length limited decoded output by decoding the selected sequence of binary digital signals from the sequence detector or for providing a run length limited decoded output by decoding the sequence of binary digital signals from the transition detector;

control means for directing either the sequence of binary digital signals from the sequence detector or the sequence of binary digital signals from the transition detector to the RLL (d,k) decoder.

2. The integrated circuit synchronous read channel of claim 1 further comprised of digital pulse shaping filter circuitry for modifying the digitized read signals prior to receipt thereof by at least one of (i) the sequence detector, (ii) the transition detector and (iii) the timing recovery circuitry.

3. The integrated circuit synchronous read channel of claim 2 further comprised of delay means for delaying coupling of the digitized read signals to the transition detector or to the timing reciver circuitry to match a delay in coupling the digitized read signals to the timing recovery circuitry or the transition detector, respectively, imposed by the digital pulses shaping filter circuitry.

4. The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter circuitry includes variable filter parameters.

5. The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter circuitry modifies the digitized read signals using programmable filter parameters.

6. The integrated circuit synchronous read channel of claim 1 further comprising the spectrum smoothing filter circuitry for filtering the digitized read signals prior to processing by the sequence detector.

7. The integrated circuit synchronous read channel of claim 1 wherein the sequence detector processes two digitized read signals at a time, the two digitized read signals respectively representing digitized samples of a read signal of a magnetic storage device during two successive channel bit times.

8. An integrated circuit synchronous read channel for receiving read signals responsive to transitions in magnetic polarity stored in a magnetic storage device and recovering digital data represented thereby

comprising:

timing recovery circuitry responsive to the read signals to provide a timing control signal for recovery of the binary digital signal timing in the read signal; and,

a sequence detector responsive to the read signals for receiving a read signal and determining the

corresponding sequence of binary digital signals likely to be represented thereby said binary digital signals having a minimum run length constraint of d>0 and said sequence detector comprising a path memory means in which sequences of binary digital signals are

constructed, a comparison means to compare the received read signal to a set of ideal read signals, and a selection means which selects an ideal read signal which resembles the received read signal and thereby also selects the sequence of binary digital signals in the path memory which corresponds to the selected ideal read signal .

9. The integrated circuit synchronous read channel of claim 8 wherein d=l.

10. The integrated circuit synchronous read channel of claim 8 wherein said timing recovery

circuitry comprises:

timing error measurement circuitry for providing a timing error measurement signal responsive to the present quantity of bit timing error;

timing correction circuitry for correcting the present timing in response to the timing error

measurement signal received from the timing error measurement circuitry; and,

sensing circuitry for determining when the timing correction circuitry responds to the timing error measurement signal .

11. The integrated circuit synchronous read channel of claim 10 wherein the sensing circuitry is a transition detector for detecting pulses in the

amplitude of the received read signal indicative of magnetic transitions on the storage media.

12. The integrated circuit synchronous read channel of claim 10 further comprised of control circuitry for selecting either the sequence of binary digital signals from the sequence detector or an output from the sensing circuitry.

13. The integrated circuit synchronous read channel of claim 8 further comprised of an RLL (d,k) decoder for providing a run length limited decoded output by decoding the sequence of binary digital signals from the sequence detector.

14. The integrated circuit synchronous read channel of claim 13 wherein the RLL (d,k) decoder is an RLL (1,7) decoder.

15. The integrated circuit synchronous read channel of claim 8 wherein the timing recovery circuitry includes a digital phase detector and a digital timing loop filter.

16. The integrated circuit synchronous read channel of claim 10 wherein the timing error measurement circuitry comprises a digital phase detector and the timing correction circuitry comprises a digital timing loop filter.

17. The integrated circuit synchronous read channel of either of claims 15 and 16 wherein the timing correction circuitry provides a digital frequency control signal responsive to bit timing phase errors for direct control of the frequency of a clock determining bit timing.

18. The integrated circuit synchronous read channel of either of claims 15 and 16 wherein the coefficients of the digital timing loop filter are programmable .

19. The integrated circuit synchronous read channel of claim 8 further comprised of automatic gain control circuitry coupled to the read signals to provide a gain control signal responsive thereto.

20. The integrated circuit synchronous read channel of claim 19 wherein the read signals are

digitized read signals representing digitized samples of the read signal of the magnetic storage device and wherein the automatic gain control circuitry includes a digital gain error detector responsive to the digitized read signal samples and a digital gain loop filter.

21. The integrated circuit synchronous read channel of claim 20 wherein the digital gain loop filter provides a digital gain control signal for directly controlling the gain of a variable gain amplifier.

22. The integrated circuit synchronous read channel of claim 20 wherein the coefficients of the digital gain loop filter are programmable.

23. The integrated circuit synchronous read channel of claim 20 wherein the digital gain error detector provides a digital gain error measurement signal responsive to the difference between a

programmable desired signal level and the digitized read signal .

24. The integrated circuit synchronous read channel of claim 8 further comprised of digital pulse shaping filter circuitry for modification of the

digitized read signals prior to receipt thereof by at least one of (i) the sequence detector and (ii) the timing recovery circuitry.

25. The integrated circuit synchronous read channel of claim 11 further comprised of digital pulse shaping filter circuitry for modification of the

digitized read signals prior to receipt thereof by at least one of (i) the sequence detector, (ii) the timing recovery circuitry, and (iii) the transition detector.

26. The integrated circuit synchronous read channel of claim 25 further comprised of delay circuitry for delaying the coupling of the digitized read signals to the transition detector or the timing recovery circuitry to match the delay of the coupling of the digitized read signals to the timing recovery circuitry or the transition detector, respectively, imposed by the digital pulse shaping filter.

27. The integrated circuit synchronous read channel of either of claims 24 and 25 wherein the digital pulse shaping filter circuitry includes

programmable filter parameters.

28. The integrated circuit synchronous read channel of claim 8 further comprised of spectrum smoothing filter circuitry for filtering the digitized read signals to reduce the effect of head bumps prior to processing by the sequence detector.

29. The integrated circuit synchronous read channel of claim 28 wherein the spectrum smoothing filter includes programmable coefficients.

30. The integrated circuit synchronous read channel of claim 28 wherein the spectrum smoothing filter includes programmable delays.

31. The integrated circuit synchronous read channel of claim 8 wherein the read signals are

digitized read signals representing digitized samples of the read signal of the magnetic storage device and wherein the sequence detector processes two digitized read signals at a time, the two digitized read signals representing digitized samples of a read signal of a magnetic storage device during two successive channel bit times.

32. The integrated circuit synchronous read channel of claim 8 wherein the read signals are

digitized read signals representing digitized samples of the read signal of the magnetic storage device and wherein the timing recovery circuitry processes two digitized read signals at a time, the two digitized read signals representing digitized samples of a read signal of a magnetic storage device during two successive channel bit times.

33. The integrated circuit synchronous read channel of claim 8 wherein the read signals are analog signals and the read channel includes sampling circuitry to periodically sample the analog signals.

34. The integrated circuit synchronous read channel of claim 33 wherein the sampling circuitry includes digitizing circuitry to produce digitized read signals representing digitized samples of the read signal of the magnetic storage device.

35. The integrated circuit synchronous read channel of claim 8 further comprised of a microprocessor interface and a plurality of control registers.

36. A digital integrated circuit for receiving digitized read signals representing digitized samples of a read signal of a magnetic storage device and

recovering digital data represented thereby comprising: timing recovery circuitry responsive to the digitized read signals to provide a timing control signal for controlling the timing of digitized samples of the read signal; and,

a sequence detector responsive to the digitized read signals for receiving a read signal and determining a corresponding sequence of binary digital signals likely to be represented thereby said binary digital signals having a minimum run length constraint of d>0 and said sequence detector comprising a path memory means in which sequences of binary digital signals are constructed, a comparison means to compare the received read signal to a set of ideal read signals, and a selection means which selects an ideal read signal which resembles the received read signal and thereby also selects the sequence of binary digital signals in the path memory which corresponds to the selected ideal read signal .

37. The digital integrated circuit of claim 36 wherein the timing recovery circuitry is programmable to control the phase of the digitized read signal such that the pulses in the digitized read signal may be

selectively side sampled or center sampled.

38. The digital integrated circuit of claim 37 wherein the sequence detector is programmable to determine a sequence of binary digital signals from a digitized read signal in which the pulses are

selectively side sampled or center sampled.

39. The digital integrated circuit of claim 36 wherein d=l .

40. The digital integrated circuit of claim 36 wherein said timing recovery circuitry comprises:

timing error measurement circuitry for providing a timing error measurement signal responsive to the present quantity of bit timing error;

timing correction circuitry for correcting the present timing in response to the timing error

measurement signal received from the timing error measurement circuitry; and,

sensing circuitry for determining when the timing correction circuitry responds to the timing error measurement signal.

41. The digital integrated circuit of claim 40 wherein the sensing circuitry is a transition detector for detecting pulses in the amplitude of the digitized read signal indicative of magnetic transitions on the storage media.

42. The digital integrated circuit of claim 36 wherein said timing recovery circuitry comprises:

timing error measurement circuitry for providing a timing error measurement signal responsive to the present quantity of bit timing error;

timing correction circuitry for correcting the present timing in response to the timing error

measurement signal received from the timing error measurement circuitry; and,

control circuitry responsive to an external transition detector for determining when the timing correction circuitry responds to the timing error measurement signal.

43. The digital integrated circuit of claim 40 further comprised of controllable means for selecting either the sequence of binary digital signals from the sequence detector or the output from the transition detector.

44. The digital integrated circuit of claim 36 further comprised of an RLL (d,k) decoder for providing a run length limited decoded output by decoding the sequence of binary digital signals from the sequence detector.

45. The digital integrated circuit of claim 44 wherein the RLL (d,k) decoder is an RLL (1,7) decoder.

46. The digital integrated circuit ^'of claim 36 wherein the timing recovery circuitry includes a digital phase detector and a digital timing loop filter.

47. The digital integrated circuit of claim 40 wherein the timing error measurement circuitry comprises a digital phase detector and the timing correction circuitry comprises a digital timing loop filter.

48. The digital integrated circuit of either of claims 46 and 47 wherein the timing recovery circuitry provides a digital frequency control signal responsive to bit timing phase errors for direct control of the frequency of a clock determining bit timing.

49. The digital integrated circuit of either of claims 46 and 47 wherein the coefficients of the digital timing loop filter are programmable.

50. The digital integrated circuit of claim 36 further comprised of automatic gain control circuitry coupled to the read signals to provide a gain control signal responsive thereto.

51. The digital integrated circuit of claim 50 wherein the read signals are digitized read signals representing digitized samples of the read signal of the magnetic storage device and wherein the automatic gain control circuitry includes a digital gain error detector responsive to the digitized read signal samples and a digital gain loop filter.

52. The digital integrated circuit of claim 51 wherein the digital gain loop filter provides a digital gain control signal for directly controlling the gain of a variable gain amplifier.

53. The digital integrated circuit of claim 51 wherein the coefficients of the digital gain loop filter are programmable.

54. The digital integrated circuit of claim 36 further comprised of digital pulse shaping filter circuitry for modification of the digitized read signals prior to receipt thereof by at least one of (i) the sequence detector and (ii) the timing recovery

circuitry.

55. The digital integrated circuit of claim 41 further comprised of digital pulse shaping filter circuitry for modification of the digitized read signals prior to receipt thereof by at least one of (i) the sequence detector, (ii) the timing recovery circuitry, and (iii) the transition detector.

56. The digital integrated circuit of claim 55 further comprised of delay circuitry for delaying the coupling of the digitized read signals to the transition detector or the timing recovery circuitry to match the delay of the coupling of the digitized read signals to the timing recovery circuitry or the transition

detector, respectively, imposed by the digital pulse shaping filter.

57. The digital integrated circuit of either of claims 54 and 55 wherein the digital pulse shaping filter circuitry includes programmable filter

parameters .

58. The digital integrated circuit of claim 36 further comprised of spectrum smoothing filter circuitry for filtering the digitized read signals to reduce the effect of head bumps prior to processing by the sequence detector.

59. The digital integrated circuit of claim 58 wherein the spectrum smoothing filter includes

programmable coefficients.

60. The digital integrated circuit of claim 58 wherein the spectrum smoothing filter includes

programmable delays .

61. The digital integrated circuit of claim 36 wherein the read signals are digitized read signals representing digitized samples of the read signal of the magnetic storage device and wherein the sequence

detector processes two digitized read signals at a time, the two digitized read signals representing digitized samples of a read signal of a magnetic storage device during two successive channel bit times.

62. The digital integrated circuit of claim 36 wherein the read signals are digitized read signals representing digitized samples of the read signal of the magnetic storage device and wherein the timing recovery circuitry processes two digitized read signals at a time, the two digitized read signals representing digitized samples of a read signal of a magnetic storage device during two successive channel bit times.

63. The digital integrated circuit of claim 36 further comprised of an RLL encoder for RLL encoding digital data to be written to a magnetic storage device.

64. The digital integrated circuit of claim 36 further comprised of: a processor interface and a plurality of control registers from which a processor may read information and to which a processor may write information; and, a serial interface having a serial data line and a serial clock line.

65. The digital integrated circuit of claim 64 further comprised of:

multiplexing circuitry for providing as the output of the integrated circuit;

i) the digital data to be written to a magnetic storage device in 2 bit wide form during writing to the storage medium; and,

ii) selectively providing the output of the serial data line and the serial clock line when not writing to the storage medium.

66. The digital integrated circuit of claim 64 wherein the serial interface includes circuitry for reading in serial form on the serial data line the contents of mapped external registers.

67. The digital integrated circuit of claim 66 wherein the serial interface includes circuitry

responsive to requests presented at the processor interface to selectively:

a) read in serial form on the serial data line the contents of one of the mapped external registers and then provide the contents of said mapped external register at the processor interface; or

b) provide at the processor interface the contents of a mapped external register specified in a previous request and then read in serial form on the serial data line the contents of a second mapped external register specified in the present request.

68. The digital integrated circuit of claim 66 wherein a processor may write control information to a specified mapped external register by writing to the mapped external register's address in the digital integrated circuit, and wherein the serial interface includes circuitry for presenting in serial form on the serial data line to the specified mapped external register the data written to the mapped external register's address in the digital integrated circuit each time the processor writes to the mapped external register's address.

69. A digital integrated circuit comprising:

an RLL encoder for RLL encoding digital data to be written to a magnetic storage device;

a processor interface and a plurality of control registers from which a processor may read information and to which a processor may write information; and, a serial interface having a serial data line and a serial clock line;

multiplexing circuitry for providing as the output of the integrated circuit

i) the output of the RLL encoder in 2 bit wide form during writing to the storage medium; and,

ii) selectively providing the output of the serial data line and the serial clock line when not writing to the storage medium.

70. The digital integrated circuit of claim 69 wherein the serial interface includes circuitry for reading in serial form on the serial data line the contents of mapped external registers.

71. The digital integrated circuit of claim 70 wherein the serial interface includes circuitry responsive to requests presented at the processor interface to selectively:

a) read in serial form on the serial data line the contents of one of the mapped external registers and then provide the contents of said mapped external register at the processor interface; or

b) provide at the processor interface the contents of a mapped external register specified in a previous request and then read in serial form on the serial data line the contents of a second mapped external register specified in the present request.

72. The digital integrated circuit of claim 69 wherein a processor may write control information to a specified mapped external register by writing to the mapped external register's address in the digital integrated circuit, and wherein the serial interface includes circuitry for presenting in serial form on the serial data line to the specified mapped external register the data written to the mapped external register's address in the digital integrated circuit each time the processor writes to the mapped external register's address.