US3705359A

US3705359A - Pcm decoder with expansion characteristic

Info

Publication number: US3705359A
Application number: US121940A
Authority: US
Inventors: Werner Kappes
Original assignee: Krone GmbH
Current assignee: ADC GmbH
Priority date: 1970-03-09
Filing date: 1971-03-08
Publication date: 1972-12-05
Anticipated expiration: 1989-12-05
Also published as: GB1315749A; BE763859A; FR2083956A5; DE2011056B2; DE2011056A1; NL7102345A

Abstract

Incoming binary code words of n+m+1 bits, the highest-ranking of them being a polarity indicator, are fed to a first decoding stage which converts the lower-ranking n-bit group into a corresponding analog voltage of up to 2n incremental steps and, in the presence of at least one bit of logical value '''' 1'''' in the higher-ranking m-bit group, superimposes upon this analog voltage a fixed voltage of 2n incremental steps. A second decoding stage simultaneously receives the m-bit group and derives from it a stepdown factor, ranging from 0 to 2m, by which a switching circuit controlled by that stage divides the output of the first stage.

Description

United States Patent v 1151 3,705,359 Kappes 1 Dec. 5, 1972 1 541 PCM DECODER WITH EXPANSION 4/1970 Gorog ..l78/66 R CHARACTERISTIC [72] Inventor: Werner Kappes, Berlin, Germany Primary Examiner-Alfred L. Brody [73] Assignee: Krone Gmbl-l, Berlin-Zehlendorf, Attorney-Karl ROSS Germany 22 Filed: March a, 1971 [57] ABSTRACT [21] APPL 121,940 Incoming binary code words of n-l-m+l bits, the a highest-ranking of them being a polarity indicator, are

fed to a first decoding stage which converts the lower- [301' s" Apphcmlm Pl'lomy Data ranking n-bit group into a corresponding analog volt- March 9, 1970 Germany ..P 20 11 056.9 age of p to incremental Steps and, in the Presence ofat least one bit of logical value 1 in the higher- [52] US. Cl.....' ..329/l04, 178/66 R,'325/38 R, Tanking m-bi! group, supel'imposes P this analog 325/32l,325/324, 340/347 AD voltage a fixed voltage of 2" incremental steps. A [51] Int. Cl. ....H03k 9/00 eC0nd decoding stage simultaneously receives the m- [58] Field of Search.....329/l04; 325/38 R, 321, 322, bit group and derives from it a stepdown factor, rang- 325/324; 340/347 AD; 178/66 R a ing from 0 to 2'", by which a switching circuit controlled by that stage divides the output of the first [56] References Cited stage.

UNITED STATES PATENTS 10 Claims, 13 Drawing Figures 3,404,231 10/1968 Aaron etal ..'...325/38 R i ml I n-bils E P Ric/5m? m5- mm 6 L0 0 4 OUTPUT 1 I s g m-MIJv DEtooL-E RD: a S2 76 10/ '1-g% I02 R91 I s,

PATENTEU 5 3, 705. 359

'

sum

1 or 6 8-,6-I'C code words EXPANSION CHAEflCTEE/ST/C Inventor U Werner Kappes 71 mime PAIENTl-innm 5m 3.705.359

SHEET 5 BF 6 SQQ QQQx w QkQQQQQQ z m m coo: wens CODE WORDS QQQQ QQQx I I I I I I l I I I I I I I J ENCCDEE (.3109 (HA Attorney PATENTEDuEc "s uerz SHEET 6 OF 6 VOLTAGE SWITCH bits STEP- oowu CLOSED My present invention relates to a demodulator for binary code words, e.g., as arriving at a receiving station in a telecommunication system of the pulse-codemodulation, time-division-multiplex type.

In digitizing an analog signal, such as the instantaneous amplitude of an audio-frequency wave, it is possible to improve the signal-to-noise ratio bymagnifying the lower signal voltages with reference to the higher amplitudes in accordance with apredetermined compression characteristic and restoring the original relationship upon subsequent digital/analog analog reconversion by operating along a complementary expansion characteristic, as is well known per se. In such a compander system, the characteristics are generally kneetype' curves each consisting of 2'" linear segments dividing a range of signal amplitudes, between limits of iU into as many bands (half of them positive, half of them negative) whose width increases from the origin outward by a factor of 2, except for the two innermost bands on either side of the abscissa which are of the same width. Each amplitude band, in turn, is subdivided into 2" incrementalsteps represented by the n lowest-ranking bits of a code word of n+m+l hits, the highest-ranking bit being a sign indicator which, of course, is needed only if the signal to be digitized can be of either polarity. Y

In the specific PCM system discussed hereinafter by way of example, each code word consists of eight bits with n 4 and m 3. Thus, the characteristic is divided into 16 segments, eight on each side of the origin; if the four innermost segments of identical slope are considered a single segment, the number of segments reduces to thirteen. Reference may be made in this connection to a CClTT report entitled COM XV, question No; 33, Temp. Doc. No. 34 of 25 September to 6 October 1967.

The general object of my present invention is to provide an improved pulse-code demodulatorifor re-expanding the analog equivalents of binary code words generated in the aforedescribed manner according to a compression characteristic divided into 2" -(or possibly 2'") linear segments.

-A more specific object is to provide means in such a demodulator for reversing the'polarity of the reconstituted analog voltage under the control of the sign bit, if necessary, at a stage preceding the restoration of the original amplitude relationship in order that possible minor switching dissymmetries may be stepped down in the same proportionas the corresponding signal amplitudes to minimize their effect upon low-amplitude signals.

A further object is to obviate the need in such a demodulator for so-called floating analog switches (which do not respond to a fixed reference potential) as well as constant-current generators, both of which require complex circuitry in order to be realized with the necessary degree of precision.

Still another object is to provide a demodulator which, while satisfying the aforestated desiderata, operates at a decoding speed compatible with the reception of 3-bit code words in a PCM system of the 30/32-channel type in which signal amplitudes are sampled during intervals on the order of lusec.

In accordance with this invention, the demodulator includes a first decoding stage connected to receive both thelower-ranking n-bit group and the higherranking m-bit group from a storage circuit in which the incoming code words are temporarily registered, this first stage including an impedance network with individually switchable branches which are controlled by the n-bit group to generate a corresponding analog voltage composed of up to 2" incremental steps: a further switchable branch in this network, controlled by the m-bit group, superimposes upon this analog voltage a first voltage of 2" incremental steps in the output of the'first stage if this latter group includes at least one finite bit, i.e., if one or more m-bits thereof have the logical value 1. This m-bit group is also fed to a second decoding stage to control the operation of a weighting circuit for multiplying the output of the first stage by a factor proportional to the analog equivalent of the m-bit group. In practice, this proportional factor is usually of fractional value so that the multiplication becomes a division performed in an impedance work of the step-down type.

' The network of the first stage, as more fully described hereinafter, may comprise n+2 parallel resistances joined to an inverting input of an operational amplifier, these resistances having staggered magnitudes 2R wherein i is an integer ranging from 0 through n+1, the smallest resistances thus having the value R while the largest one has the value 32R in the specific example (n 4) here considered. The smallest resistance R, which in view of the parallel connection is the electrically most significant one, is switchable into circuit in response to a finite m-bit, the register stage carrying the several (here three) m-bits working advantageously into a common OR gate to generate a control signal for the switching of this particular resistance. The largest and therefore electrically least significant resistance is connected to a source of fixed reference potential whose polarity may be reversed in response to the sign bit; it is also possible for this purpose to insert an inverter ahead ofthe operational amplifier delivering the output of that decoder stage, this inverter being selectively short-circuited according to the logical value of the sign bit.

Instead of staggered resistances connected in parallel branches of the impedance network, the latter may be a resistive ladder circuit of the R/2R type as described, for example, by David F. Hoeschele in Analog-to- Digital/Digital-to-Analog Conversion Techniques, published 1968 by John Wiley & Sons, Inc., New York, pages 108 ff. This latter network comprises n+2 arms of magnitude 2R (interconnected by sections of mag nitude R) of which one is connected to a source of fixed reference potential whereas the others are selectively connectable to the same source in response to respective n-bits and, in the case of the arm farthest from the source, to a finite m-bit as transmitted through the aforementioned OR gate. Again, the reversal of polarity under the control of the sign bit may be carried out at the source or by an inverter cascaded with the zero-voltage terminal (ground) and a high-voltage ter-.

net-

minal energized by the. first decoder stage, these re- 'sistors having progressively decreasing magnitudes ranging from a value 2 '"-"R for the resistor nearest the high-voltage terminalto a value R between the two taps farthest from that terminal, the adjoining resistor at the grounded end having the same magnitude R. The highvoltage terminal and the 2"'2 taps between the several weighting resistors are selectively connectable, under the control of the m-bit group, to an impedance transformer such as an operational amplifier whose high input resistance minimizes the shunting effect of the output circuit upon the potentiometer.

The duplication of the lowest resistance value at the grounded potentiometer end is designed to preserve the correct binary relationship 'of the several potentiometer output, at the expense of introducing an ambiguity with regard to the first two segments (of identi-- cal slope) of the characteristic curve.

This ambiguity, however, is resolved by the aforedescribed superposition of a fixed voltage upon the analog equivalent of the n-bit group in response to the presence of at least one true m-bit; thus the switch connecting the lowest tap of the potentiometer to the output amplifier is closed regardless of the logical value of the least-significant m-bit if all the other m-bits have the logical value 0, Le, if (for m 3) this group is of either the form 000 or the form 001.

dent of the mechanism by which the binary code words were derived from the original analog signal, provided the compression and expansion characteristics are mutually complementary. Reference may be made, however, to commonly owned application Ser. No. 120,171 filed Mar. 2, 1972 by Waldemar Fruhauf which discloses and claims a corresponding modulator operating on a somewhat analogous two-stage coding principle.

The above and other features of my invention will be described in detail hereinafter with reference to the accompanying drawing in which:

FIG. 1 is a graph of an expansion characteristic of the type used in a pulse-code demodulator embodying my invention;

FIG. la is a similar graph showing a complementary compression characteristic;

FIG. lb is a graph showing part of the characteristic of FIG. 1a on a larger scale;

FIG. 2 is a diagram of an eight-bit code word to be demodulated;

- FIG. 3 is an overall circuit diagram of a demodulator according to the invention;

FIG. 4a is a more detailed diagram of a first decoder stage forming part of the demodulator of FIG. 3;

nos. 4b and 4c SllOW respective modifications of the decoder stage of FIG. 4a;

FIG. S'shows one branch of the expansion curve of FIG. 1 on an enlarged scale, together with the output of the first decoder stage drawn to the same scale;

FIGS. 5a and 5b are graphs illustrating the relationship between analog voltage 'and code combinations in coding and decoding, respectively;

FIG; 6 is a table relating to the operation of a weighting circuit included in the system of FIG. 3; and

FIG. 7 is a circuit diagram of a second decoder stage forming part of the demodulator of FIG. 3.

Reference will first be made to FIGS. la and 1b which show a compression characteristic (similar to that illustrated in correspondingly numbered Figures of the above-identified Fruhauf application) as used in an encoder at a transmitting station of a PCM/TDM telecommunication system. The demodulator according to my invention, described in detail hereinafter, forms part of a receiving station linked with that transmission station in any conventional manner.

The compression characteristic shown in FIG. la represents the variation of the output voltage U of an amplitude converter in response to different input voltages U, ranging between a negative limit -U,,,,,, and a positive limit +U of the same absolute magnitude. The positive branch of the curve, lying in the first quadrant, and its negative branch, lying in the third quadrant, are mutually symmetrical about the origin 0 and are each subdivided at points +0 to +0 and Q, to --Q into 2'" linear segments, there being eight such segments per branch (m 3) in the example given. The first six segments of the positive branch have been shown more clearly in FIG. 1b; because of the symmetry, the subsequent discussion will be limited to this positive branch.

The seven knee points Q, Q1 of the curve are progressively spaced along the abscissa according to a binary law, with the exception of the first two points 0 Q defining bands of like width (equal to U,,,,,,/ I 28) for the amplitude of input voltage U Thus, the width of the third hand (between points 0; and O3) is UNI/64, that of the fourth band is U /32, and so forth to a maximum value of U /2 for the eighth band. The slopes of the several linear segments defined by these knee points decrease in the same binary ratio (being identical for the first two segments) so that the output voltage U rises from one point to the next by a constant differential AU. With the spread AU quantized in 2" steps, as indicated along the ordinate in FIG. lb for n 4, the magnitude of +U may be coded in m+n 7 bits. An additional bit, ranking above the others, may be used to discriminate between positive and negative polarity so that the entire range between U,,.,,, and +U can be covered by m+n+1= 8 bits.

The expansion characteristic shown in FIG. 1 is subdivided, like the aforedescribed compression characteristic, into 16 segments defined by points H, to H, and P to P,; on opposite sides of the origin 0. The slopes of these segments progressively increase in a binary ratio, again with the exception of the four innermost segments (between P and +P which are of the same slope; the relative length of the several segments is so chosen that their projections upon the abscissa are of uniform length, defining sixteen (2"*) sets of eightbit code words which have been designated I VIII for the positive half of the curve. Each set I VIII encompasses 16 (2") different code words headed by a single combination of m-bits (000 through 111). Thus, the corresponding analog voltage iU is divided into 16 bands whose relative width is the same as that of the corresponding bands of the original analog voltage U shown in FIGS. la and 1b.

FIG. 2 shows the structure of an eight-bit code word together with the digital weight of its constituent bits. The highest-ranking (sign) bit of the weight 2, indicates the polarity of the transmitted signal. The next 106009 OIIO three bits, of

weights

2, 2 and 2 represent the m-bit group which defines one'of the sets I VIII in FIG. 1 and thus identifies one of the segments of the expansion characteristics whose slope determines the relative magnification or reduction to which the analog equivalent of the code word must be subjected. The four lowest-ranking bits, of weights.2", 2 2 and 2, represent then-bit group which selects one of the sixteen subdivisions forming part of the designated amplitude band.

The incoming bits of any code word are temporarily stored in respective bistable units of a register 100 'which, at a predetermined point in a cycle and under the control of a timer not shown, discharges them in parallel to two decoding stages D, and D Stage D, v

receivesthe four n-bits, the 3 m-bits, and the signbit;

only the m-bits are fed to stage D, which has seven outconsists of seven serially interconnected resistors RD,

RD, connected between ground and an output lead 109 of decoder stage D, carrying an analog voltage U, switch S, isinsertedbetween this lead 109 and the input of amplifier IW beyond the junction of that lead with potentiometer RD, whereas switches S, S,,are connected to respective taps of the potentiometer formed bysuccessive junctions of resistors RD, RD The relative magnitudes of these resistors are as follows:

From the foregoing values it will be noted that selective operation of switches S, S, (only one of which can be closed at a time), in response to respective combinations of m-bits, applies the following potentials to the additive input of amplifier IW:

[1,4764 (00]) U 'I3Z (010) U 'll6 (011) 47 (1 0) U,4'/4 (101) UA /Z (I10) U Thus,'the output voltage of the first decoder stage D,

is multiplied, under the control of the second decoder stage D,,, by a factor which ranges from 1/64 to 1 and is proportional to the analog equivalent of the m-bit code group operating the associated switch. These switches, though shown diagrammatically as pairs of contacts, are in practice designed as solid'state electronic devices such as field-effect transistors.

The'input resistance of the operational amplifier IW may be on the order of I GO so that this amplifier should have no significant influence upon the potentiometer RD.

One form of decoder D, has been illustrated in FIG. 4a which shows the register working into a resistance network RB comprising six resistors RB, RB the first five resistors being in series with respective switches BS, BS terminating at a bus bar which is directly connected to resistor RB A further switch BS, is reversible under the control of the sign bit in register 100 to apply either a positive reference voltage +U or a negative reference voltage U,,; to the bus bar 110 and through it to the inverting input of an operational amplifier V to which all the other resistors are also connected in parallel. Amplifier V has a feedback resistor R connected between its output, delivering the intermediate analog voltage U,,', and its inverting input; the non-inverting input of this .differential amplifier is grounded.

An OR gate 111 receives the 3 m-bits 2 2 2 from register 100 to close the switch Bs whene ver at least one of these bits has the logical value l thereby connecting the resistor RB, to bus bar 110. Resistors RB, RB, are similarly connected in circuit by switches BS, BS responding to respective n-

bits

2, 2, 2 and 2 The relative magnitudes of resistors RB RB, R8,,

4 based upon the resistance R of arm RB are as follows:

If RB is the effective overall resistance of network RB in a particular switch position (regardless of the polarity of the reference voltage applied to bus bar 110), and if Up is the input voltage at the subtractive feedback terminal of amplifier V, we can establish the relationship F 4 re!) rel- Since U,,' aU (a being the gain of amplifier V), we obtain It follows that the output voltage U,,' isnegatively proportional to the reference voltage U; multiplied by the quotient of the resistance R and R5; the bus bar 110 may be energized with a positive or negative reference voltage U so that U may be of either sign.

106009 OI ll The amplification factor of commonly available operational amplifiers is very large (l a 10);

hence the voltage U, U,/a is very low. Thus, the subtractive input of an operational amplifier connected as an inverter is called virtual ground or summing point. It follows that, in the circuit here considered, the voltage U is developed only across the resistor R, which may be considered the input impedance of the inverting operational amplifier V.

It can be readily calculated that the magnitude of the network resistance R may assume any one of 32 different values ranging from 32R (with all switches BS, 88,-, open) to 32R/63 (with all the switches closed), corresponding to 32 discrete amplitudes for output voltage U, ranging from iU /64 to :63 U,,,/64. This has been illustrated inFIG. 5. Which shows that the first set I of code words, ranging from 0000000 to 0001 111 (with omission of the polarity bit), gives rise to 16 discrete steps below the median line U, )U the highest of these steps, (simultaneous closure of switches BS, B8,) representing 3lU, ,/64. If, with switches BS, BS., open, switch BS closes in response to an output of OR gate 111 to connect the electrically most significant resistor RB, to bus bar 110, the output voltage U, reaches the first step 33 U, ,/64 in the upper half of the diagram. Thus, in the presence of one or more m-bits of logical value 1, the 16 amplitude steps represented by the various combinations of n-bits are transposed from positions below the median line (set I) to corresponding positions above that line (sets 11 VIII).

The threshold U, ,/64 of the lowermost step represents a slight and practically insignificant deviation from the original analog voltage as modified by the amplitude converter at the encoder (see FIGS. 1a and lb). This has been illustrated in FIGS. 5a and 5b, FIG. 5a showing the relationship between the voltage steps in the region of the origin and the associated code combinations at the encoder whereas FIG. 5b gives the corresponding relationship at the decoder D,. At the encoder, words 10000000 and 00000000 represent 0 volt,

words

10000001 and 00000001 indicate a first step equal to 1/32 of the positive or negative voltage U,

U,,,,,,/64, words 10000010 and 00000010 relate to the next step of twice that amplitude, and so forth. At the decoder, on the other hand, words 10000000 and 00000000 respectively correspond to +U 64 and U' #64,

words

10000001 and 00000001 denote amplitudes of i3 U /64, words 10000010 and 00000010 designate the next unit step of i5 U y/64, and so forth.

A similar result is obtained if, as shown in FIG. 4b, the bus bar 110 is permanently connected to its source of reference voltage U (here positive), the single operational amplifier V of FIG. 4a, being replaced by a pair of cascaded amplifiers V,, IW, (the latter being of the type shown at IW in FIG. 3) between which a further inverting amplifier V can be inserted with the aid of a pair of ganged switches SW1, SW under the control of the sign bit of register 100. Amplifier V,, generating a negative output voltage U,', and amplifier V generating a positive voltage +U, of the same absolute magnitude, are identical with amplifier V of FIG. 4a; in amplifier V however, the resistors R and R associated with amplifier V, have been replaced by a pair of identical resistors R and Ry connected in series between the outputs of amplifiers V and V with their junction tied to the subtractive input of amplifier V It can be shown that, owing to the equality of resistors R and R inverter V, has an amplification factor of -l (for a gain a 1) so that its insertion in or exclusion from the output circuit of the decoder does not affect the absolute magnitude of voltage U, delivered by impedance transformer IW,. In the illustrated switch position, inverter V is short-circuited by switch SW, so that output voltage U, is negative; upon reversal of switches SW, and SW, in the presence of a polarity bit, this output voltage becomes positive.

FIG. 40 shows'another possible configuration for the impedance network of decoder D, which in this case has a ladder-type structure consisting of five series resistors of magnitude R, five shunt resistors RB, RB of magnitude 2R in series with respective switches BS, BS a further resistor RB, of the same magnitude 2R permanently connected to bus bar 1 10 at the end of the ladder remote from resistor R3 and an additional resistor RB, connected between that end and ground. The opposite end of the ladder network R is terminated by a resistor R, which is virtually grounded by being joined to the subtractive input of the operational amplifier V connected as an inverter. It is thus possible to consider resistor R,,' the load resistance of the ladder network across which the voltage U, is developed. At the output of the amplifier V the voltage U,' appears when the feedback resistors R equals the load resistors 11,, as has already been explained for the amplifier V in FIG. 4b. The voltage U, can be calculated in the following manner (see the above-identified publication by DA. Hoeschele):

where D,* D represent the value of the respective bits controlling the switches BS, BS Again, a pair of reversing switches SV, and SV,, responsive to the polarity bit in register 100, serve to feed the output of the impedance network to an amplifier [W of very high input resistance (identical with impedance transformer IW, of FIG. 4b) either directly or, in the illustrated switch position, by way of inverting stage V The operation of the R/2R-type ladder network RB is well known per se. With the switches BS, BS all in their illustrated position, resistors RB,'-' R3 are grounded and the output voltage of the network, taken off at the junctions of resistors R8 and R,,', has its minimum value. In this case, and with R, 2R, output voltage U, equals U,,,/96 which corresponds to the aforementioned threshold of ral/64 if U,,,;' is selected to equal 3U /2. With this assumption the diagram of FIG. 5 applies also the circuit of FIG. 40.

It will be understood that the various switches illustrated in FIGS. 4a rc are also devices of the electronic type, such as bipolar transistors.

FIG. 6 is a table which summarizes the output voltages of weighting circuit RD, FIG. 3, in different positions of switches S, 8,, together with the associated combinations of m-bits and the sets of code groups I VIII represented thereby. A logic circuit for decoder stage D operating in accordance with that table, has been illustrated in FIG. 7 which shows seven NAND gates N, N, with three inputs each except for gate N,

having onlytwo inputs. The outputs of gates N N respectively control the switches S S of FIG. 3.

Gate N receives the true bits 2 2 2, gates N N receiving the same bits partly in negated form. Gate N receives only the negated bits and? since the logical value of the lowest-ranking m-bit (2 is immaterial for the operation of switch S as already explained.

Thus, depending on the numerical value of the partial code combination represented by three m-bits, the weighting circuit including potentiometer RD and switches S S attenuates the output voltage U of decoding stage D under the control of decoding stage D to reduce the analog voltages of FIG. 5 by a corresponding step-down factor, except within the am.- plitude band represented by set VIII which coincides (apart from its stepped character as illustrated for sets I and II in FIG. 5) with the eighth segment of the expansion characteristic. Aside from the discontinuities inherent in digital coding and decoding, the final output voltage U A is therefore exactly proportional to th original input voltage U (FIGS. la and 1b) fed int the remote encoder.

I claim:

1. A pulse-code demodulatorin a receiver for binary code words of a predetermined number of bits forming a lower-ranking n-bit group and a higher-ranking m-bit group, comprising: T

storage means for temporarily registering the bits of an incoming code word;

a first decoding stage connected to said stage means for receiving both said groups therefrom, said first stage including an impedance network with individually switchable branches controlled by said lower-ranking group to generate a corresponding analog voltage composed of up to 2" incremental steps, said network being provided with a further switchable branch controlled by said higher-ranking group for superimposing upon said analog voltage of 2" incremental steps in the output of said first stage in the presence of any finite bit in the said higher-ranking group;

a second decoding stage connected to said storage means for receiving said higher-ranking group therefrom;

and weighting means controlled by said second stage from multiplying the output of said first stage by a factor proportional to the analog equivalent of said 2"R where i is an integer ranging from Q through n+1, the largest resistance of magnl ude 2" R being connected to a source of fixed referencepotential, the

smallest resistance of magnitude R being switchable into circuit in response to a finite bit in said higherranking group, the remaining resistances being switchable into circuit in response to respective bits in said lower-ranking group.

' 6. A demodulator as defined in claim 5, further comprising switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code work,'for reversing the polarity of said source.

7. A demodulator as defined in claim 5 wherein said operational amplifier has a feedback path with a series resistance of magnitude R/2.

8. A demodulator as defined in claim 4 wherein said network comprises a resistive ladder circuit of R/2R type with an arm of magnitude 2R connected to a source of fixed reference potential and with n+l other arms of like magnitude 2R selectively connectable to said source in response to respective bits in said lowerranking group and to a finite bit in said higher-ranking group.

9. A demodulator as defined in claim 4, further comprising an inverter ahead of said operational amplifier and switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code word, for selectively short-circuiting said inverter.

10. A demodulator as defined in claim 1 wherein said weighting means comprises an impedance transfonner of high input resistance and further comprises a potentiometer with 2"-l series resistors, a high-voltage terminal connected to said first stage for energization thereby, and an opposite grounded terminal, said resistors forming 2"-2 taps between said terminals and having progressively decreasing magnitudes ranging from a value 2 'r for the resistor nearest said highvoltage terminal to a value r between the two taps farthest from said high-voltage terminal, the resistor lying between said grounded terminal and the tap nearest thereto having the same magnitude r, said taps and said high-voltage terminal being selectively connectable to said impedance transformer under the control of said m hits, the tap nearest said grounded terminal being so connectable regardless of the logic value of the least significant bitof said higher-ranking group upon all the other bits of the latter group having the logical value 0.

Claims

1. A pulse-code demodulator in a receiver for binary code words of a predetermined number of bits forming a lower-ranking n-bit group and a higher-ranking m-bit group, comprising: storage means for temporarily registering the bits of an incoming code word; a first decoding stage connected to said stage means for receiving both said groups therefrom, said first stage including an impedance network with individually switchable branches controlled by said lower-ranking group to generate a corresponding analog voltage composed of up to 2n incremental steps, said network being provided with a further switchable branch controlled by said higher-ranking group for superimposing upon said analog voltage of 2n incremental steps in the output of said first stage in the presence of any finite bit in the said higher-ranking group; a second decoding stage connected to said storage means for receiving said higher-ranking group therefrom; and weighting means controlled by said second stage from multiplying the output of said first stage by a factor proportional to the analog equivalent of said higher-ranking group.

2. A demodulator as defined in claim 1 wherein said first stage further comprises switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code work, for reversing the polarity of said output.

3. A demodulator as defined in claim 1 wherein said network includes an OR gate with input connections to respective parts of said storage means registering said m bits, said further branch being responsive to a control signal generated by said OR gate.

4. A demodulator as defined in claim 1 wherein said first stage comprises an operational amplifier with an inverting input connected to said network.

5. A demodulator as defined in claim 4 wherein said network comprises n+2 parallel resistances joined to said inverting input and having staggered magnitudes 2iR where i is an integer ranging from 0 through n+1, the largest resistance of magnitude 2n 1R being connected to a source of fixed reference potential, the smallest resistance of magnitude R being switchable into circuit in response to a finite bit in said higher-ranking group, the remaining resistances being switchable into circuit in response to respective bits in said lower-ranking group.

6. A demodulator as defined in claim 5, further comprising switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code work, for reversing the polarity of said source.

8. A demodulator as defined in claim 4 wherein said network comprises a resistive ladder circuit of R/2R type with an arm of magnitude 2R connected to a source of fixed reference potential and with n+1 other arms of like magnitude 2R selectively connectable to said source in response to respective bits in said lower-ranking group and to a finite bit in said higher-ranking group.

10. A demodulator as defined in claim 1 wherein said weighting means comprises an impedance transformer of high input resistance and further comprises a potentiometer with 2m-1 series resistors, a high-voltage terminal connected to said first stage for energization thereby, aNd an opposite grounded terminal, said resistors forming 2m-2 taps between said terminals and having progressively decreasing magnitudes ranging from a value 2(2 3)r for the resistor nearest said high-voltage terminal to a value r between the two taps farthest from said high-voltage terminal, the resistor lying between said grounded terminal and the tap nearest thereto having the same magnitude r, said taps and said high-voltage terminal being selectively connectable to said impedance transformer under the control of said m bits, the tap nearest said grounded terminal being so connectable regardless of the logic value of the least significant bit of said higher-ranking group upon all the other bits of the latter group having the logical value 0.