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Publication numberCN1138271 C
Publication typeGrant
Application numberCN 99806368
PCT numberPCT/US1999/009312
Publication date11 Feb 2004
Filing date29 Apr 1999
Priority date21 May 1998
Also published asCN1301386A, DE19983241T0, DE19983241T1, US6195220, US6469849, WO1999060571A1
Publication number99806368.1, CN 1138271 C, CN 1138271C, CN 99806368, CN-C-1138271, CN1138271 C, CN1138271C, CN99806368, CN99806368.1, PCT/1999/9312, PCT/US/1999/009312, PCT/US/1999/09312, PCT/US/99/009312, PCT/US/99/09312, PCT/US1999/009312, PCT/US1999/09312, PCT/US1999009312, PCT/US199909312, PCT/US99/009312, PCT/US99/09312, PCT/US99009312, PCT/US9909312
InventorsTF埃利斯, T・F・埃利斯, AH萨克斯, 萨克斯
Applicant西加特技术有限责任公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Method and device utilizing field ratioing demodulation techniques for null-type servo pattern
CN 1138271 C
Abstract  translated from Chinese
产生位置误差估算的方法产生相位区域信号(470)与位置误差区域信号(472、474)。 The method of generating a position error estimate generates a phase field signal (470) and the position error field signal (472, 474). 对该相位区域信号(470)执行一组操作(524、542、546、712、716)并对位置误差区域信号(472、474)执行同一组操作。 (524,542,546,712,716) and position error signal area to perform a set of actions for the phase field signal (470) (472, 474) to perform the same set of operations. 用对相位区域信号执行的一组操作所得结果除对位置误差区域信号执行的一组操作所得结果。 With the results obtained for a set of operations performed by the phase field signal except a set of operations on the resultant position error field signal execution results. 相除结果是位置误差估值。 Result of the division is the position error estimate. 此外,还提供用于区域比的解调电路。 In addition, also provided for demodulating circuit area ratio.
Claims(10)  translated from Chinese
1.一种根据读取头经过存储媒体上的相位区域与位置误差区域时由该读取头产生的伺服信号,确定所述读取头在存储装置中的存储媒体上的位置的方法,其特征在于,该方法包括下述步骤:(a)对与所述相位区域关联的部分伺服信号执行一组解调操作以产生相位区域值;(b)对与所述位置误差区域关联的部分伺服信号执行一组解调操作以产生位置误差区域值;(c)用所述相位区域值除所述位置误差区域值,产生表示读取头在所述存储媒体上位置的位置误差估值。 A method based on the servo signal read head passes over phase field and position error field on the storage medium produced by the read head, the method of determining the position of the head in the storage means on the storage medium to read, which characterized in that the method comprises the steps of: (a) performing a demodulating set of operations on the portion of the servo signal associated with the phase field to produce a phase field value; (b) on the part of the servo position error field associated with the signal demodulation operations performed to generate a set of position error field value; (c) the phase region of the position error field value other value, generated by the reading head indicates the position of the storage medium position error estimate.
2.如权利要求1所述的方法,其特征在于,所述读取头经过第2位置误差区域,该方法还包括下述步骤:(d)对与所述第2位置误差区域关联的部分伺服信号执行一组解调操作,产生第2位置误差区域值;(e)用所述相位区域值除所述第2位置误差区域值,产生表示所述读取头在所述存储媒体上位置的第2位置误差估值。 2. The method according to claim 1, characterized in that the read head passes over a second position error field, the method further comprising the steps of: (d) of the position error associated with the second area of the portion a set of servo signals for performing a demodulation operation, generating a second position error field value; (e) by the phase field value other than the second value of the position error field, generating showing the reading head position on the storage medium The second position error estimate.
3.如权利要求1所述的方法,其特征在于,所述对部分伺服信号执行一组解调操作的步骤包括下述步骤:(a)(1)采样该部分伺服信号产生信号采样序列;(a)(2)把所述信号采样序列与校正值序列相乘,产生经校正值的序列;(a)(3)累加经校正值序列中的经校正值。 3. The method according to claim 1, characterized in that the execution of the portion of the servo signal demodulation operation of a set of steps comprising the steps of: (a) (1) sampling the portion of the servo signal to generate a signal sample sequence; (a) (2) of the sample sequence with the signal sequence is multiplied by the correction value, resulting in a positive sequence through school; (a) (3) accumulated by the correction sequence after correction.
4.如权利要求3所述的方法,其特征在于,所述校正值序列至少包含一个零。 4. The method of claim 3, wherein said sequence comprises at least one correction value zero.
5.如权利要求4所述的方法,其特征在于,所述相乘步骤(a)(2)包含把小幅值的信号采样值与零校正值相乘的步骤。 5. The method according to claim 4, characterized in that said multiplying step (a) (2) comprises the step of signal samples and a zero correction value slightly positive multiplied.
6.如权利要求4所述的方法,其特征在于,所述相乘步骤(a)(2)包含如果信号采样值取自所述伺服信号的低于峰值的肩部则把信号采样值乘零校正值的步骤。 6. The method according to claim 4, characterized in that said multiplying step (a) (2) If the signal sample is taken from containing the servo signal is lower than the peak value of the signal sample values multiplied by the shoulder put positive steps to zero school.
7.如权利要求1所述的方法,其特征在于,所述步骤(a)包含下述步骤:(a)(1)把所述伺服信号部分与校正信号相乘,产生经校正的信号;(a)(2)对所述经校正的信号进行积分。 7. The method of claim 1, wherein said step (a) comprises the steps of: (a) (1) The portion of the servo signal is multiplied with the correction signal to produce a corrected signal; (a) (2) of the corrected signal is integrated.
8.如权利要求7所述的方法,其特征在于,所述位置误差区域值与相位区域值是模拟值,所述用相位区域值除位置误差区域值是模拟操作。 8. The method according to claim 7, characterized in that the position error field value and the phase field value is an analog value, with the phase field value other than the position error field value is an analog operation.
9.一种用于解调数据存储装置中的伺服信号以产生误差信号值的解调电路,该伺服信号包含相位区域信号和位置误差区域信号,其特征在于,该解调电路包括:校正电路,可接收并校正相位区域信号与位置误差区域信号,产生经校正的相位区域信号与经校正的位置误差区域信号;加法电路,耦联至所述校正电路,可随时间累加所述经校正的相位区域信号以产生归一化因子并可随时间累加所述位置误差区域信号以产生未换算的位置误差区域值;除法电路,可接收所述归一化因子与未换算的位置误差区域值并可用归一化因子除未换算的位置误差区域值,产生位置误差信号值。 A demodulated data storage means to produce a servo signal demodulation circuit for error signal value, the servo signal comprising a phase field signal and a position error field signal, characterized in that the demodulating circuit includes: a correction circuit , may receive and correct the phase field signal and the position error field signal to produce a corrected position error field signal phase field signal and corrected; adder circuit coupled to the correction circuit, can be accumulated over time of the corrected phase field signal to produce a normalization factor and accumulating the position error field signal over time to produce an unscaled position error field value; the division circuit capable of receiving the normalization factor and the unscaled position error field value and The normalization factor can be used in addition to the unscaled position error field value, and generates a position error signal value.
10.如权利要求9所述的解调电路,其特征在于,所述加法电路包含模拟积分器。 10. The demodulation circuit according to claim 9, characterized in that said summing circuit comprises an analog integrator.
Description  translated from Chinese
对零类型伺服模式使用区域比解调技术的方法和装置 Zero-type servo pattern area than demodulation technique using method and apparatus

发明领域本发明涉及存储装置,具体而言,本发明涉及存储装置中的伺服系统。 Field of the Invention The present invention relates to a storage device, specifically, the present invention relates to a storage device servo systems.

该精细位置信息通常用几个伺服区域组合的伺服区域模式加以存储。 The precise location information is typically used to store several servo area servo area pattern combinations. 有若干类型的伺服区域模式,包括“零类型”(null-type)伺服模式、“分猝发脉冲幅度”(split-burst amplitude)伺服模式和“相位型”伺服模式。 There are several types of servo area modes, including "zero-type" (null-type) servo mode, "minute burst pulse amplitude" (split-burst amplitude) servo mode and the "phase type" Servo mode.

零类型伺服模式包含至少两个以已知相互相位关系写入的区域。 Null-type servo pattern includes at least two regions to each other in a known phase relationship written. 第1个区域是“相位”或“同步”区域,用于把读通道的相位和频率锁定于读信号的相位与频率。 The first area is a "phase" or "sync" area for the phase and frequency locked to the read channel read signal phase and frequency. 第2个区域是位置误差区域,用于识别读写头至记录道中心线的距离。 The second region is a position error field, for identifying the head to the track center line distance.

对于零类型位置误差区域,其磁化模式是,当读写头正好跨越记录道中心线时,读信号的幅度理论上为零。 For a null-type position error field, the magnetization pattern is that when the head is just across the track centerline, the amplitude of the read signal is zero theoretically. 当读写头从期望的记录道中心线移开时,读信号幅度增大。 When the head from a desired track centerline away, read signal amplitude increases. 当读写头处于期望道中心线与相邻记录道中心线中间时,读信号具有最大值。 When the head is in the desired track centerline and the centerline of the adjacent tracks in the middle, read signal has a maximum value.

在零类型位置误差区域中,记录道中心线一侧的磁化模式写入相位与记录道中心线另一侧磁化模式相位差180度。 In the null-type position error field, the track side of the centreline of the magnetization pattern written into phase with the track centerline on the other side 180 out of phase magnetization pattern. 从而,位置误差区域中读信号相对于同步区读信号的相位表示读写头从记录道中心线移动的方向。 Thus, the position error field read signal relative to the phase of the sync field indicates the direction of the read signal from the head track centerline movement.

为了控制这种伺服系统,对各伺服扇区确定一个位置误差值。 In order to control such a servo system, for each servo sector to determine a position error value. 通常通过解调与该位置误差区域相关的读信号来产生该位置误差值。 Typically generating the position error value by demodulating the position error field read signal associated. 位置误差值的幅值通常表示读写头离记录道中心线的距离,而其符号表示读写头移动的方向。 Magnitude of the position error value usually indicates a track center line distance from the head, and its sign indicates the direction of movement of the head.

以往,零类型模式读信号解调始终是同步处理。 In the past, zero-type pattern read signal demodulation is always synchronized. 在同步处理中,位置误差区域的读信号对于相位区域读信号的精确相位是已知的,因为以已知且固定的对位置误差区域的相位关系写相位区域。 In the synchronization process, the position error field read signal with respect to the phase of the phase field read signal precision is known, as in a known and fixed phase relation to the phase position error field of the write area. 通常用锁相环(PLL)获得相位区域的相位且用该相位信息解调位置误差区域信号。 Usually obtain phase information demodulation phase region and the position error signal with the phase of the regional phase-locked loop (PLL). 因而,相位区域必须足够长,以便使PLL可锁定在读信号的相位和频率上。 Thus, the phase region must be long enough so that the PLL can be locked in phase and frequency of the read signal. 例如,相位区域可为位置误差区域的3至4倍长。 For example, the phase field may be 3 to 4 times the length of the position error field.

确保盘片各伺服扇区中相位区域与位置误差区域之间相位关系一致是精确定位读写头的关键。 To ensure that the phase relationship between each servo sector in the disk phase region consistent with the position error field is the key head of precise positioning. 如果该两个区域之间的相位在各伺服区域中不一致,则即使读写头保持在记录道中同样径向位置,在两个不同的伺服区域将获得不同的位置误差值。 If the phase mismatch between the two regions in each servo region, even if the head is maintained at the track in the same radial position, in two different servo area will get a different position error value. 为确保该一致性,作出巨大努力并花费高昂费用以建立在各伺服区域中工作均相同的一致锁相环。 To ensure the consistency, and make great efforts to build costly expenses in each area of work are the same servo consistent phase-locked loop.

当读写头径向跨记录道移动时,伺服系统产生的位置误差值理论上以线性变化。 When the read-write head to move radially across the track, position error value theory, linear servo system to produce change. 这种线性变化简化了确定读写头移动至期望位置的移动量所需的计算。 This linear variation for the determination to move the head to calculate the required amount of movement of the desired position. 通常,读写头径向跨记录道移动时,伺服系统不产生线性变化的位置误差值。 Typically, the head moves radially across a track, the servo system does not produce a linear change of position error value. 具体而言,当读写头跨记录道径向移动时,读取头产生的读信号因该头的几何形状会有波动。 Specifically, when the head is moved radially across the track, the read head read signal generated due to the geometry of the head is subject to fluctuations. 为减小这种波动的影响,已有技术采用自动增益控制系统来自动调节伺服环增益,使其在读写头的所有记录道位置均保持常数。 To reduce the effects of such fluctuations, the prior art automatic gain control system to automatically adjust the servo loop gain, so that in all positions the head of the track are kept constant. 自动增益控制必须引入的增益量由控制电路设置,该电路在盘毁坏时或在盘驱动器寿命期间周期性加以初始化。 AGC gain amount to be introduced by the control circuit is provided, the circuit destruction of the disc during initialization or periodically to the disk drive life.

在已有技术中,作了大量努力使位置误差值标准化,从而在跨越不同伺服区时保持一致。 In the prior art, has made considerable efforts to make the position error value standardized to consistent across different servo areas while. 这产生了复杂且昂贵的结构从而提高了盘驱动器的成本。 This results in a complex and costly structure thereby increasing the cost of the disk drive.

产生位置误差估值的方法产生相位区域信号和位置误差区域信号。 The method of generating the position error estimate generates a phase field signal and a position error field signal. 对相位区域信号执行一系列操作并对位置误差区域信号执行同样操作。 A series of operations and position error field signal is the same operation on the phase field signal. 执行对位置误差区域信号的一系列操作的结果除以对相位区域信号执行的一系列操作获得的结果。 Results of the series of operations of position error field signal is divided by the phase field signal to perform the operation to obtain a series of results. 相除结果即是该位置误差估值。 That is the result of the division of the position error estimate. 本发明还提供实现该方法的电路和系统。 The present invention also provides a circuit implementation of the method and system.

本发明的一种根据读取头经过存储媒体上的相位区域与位置误差区域时由该读取头产生的伺服信号,确定所述读取头在存储装置中的存储媒体上的位置的方法,该方法包括下述步骤:(a)对与所述相位区域关联的部分伺服信号执行一组解调操作以产生相位区域值;(b)对与所述位置误差区域关联的部分伺服信号执行一组解调操作以产生位置误差区域值;(c)用所述相位区域值除所述位置误差区域值,产生表示读取头在所述存储媒体上位置的位置误差估值。 A servo signal in accordance with the present invention when the read head passes over phase field and position error field on the storage medium produced by the read head, the method of determining the position of the head in the storage means on said storage medium read, The method comprises the steps of: (a) performing a demodulating set of operations on the portion of the servo signal associated with the phase field to produce a phase field value; (b) the portion of the servo signal of the position error field associated with the implementation of a group demodulation operation to generate position error field value; (c) the phase region of the position error field value other value, indicates readhead generating the storage medium used in the position location error estimate.

本发明的一种用于解调数据存储装置中的伺服信号以产生误差信号值的解调电路,该伺服信号包含相位区域信号和位置误差区域信号,该解调电路包括:校正电路,可接收并校正相位区域信号与位置误差区域信号,产生经校正的相位区域信号与经校正的位置误差区域信号;加法电路,耦联至所述校正电路,可随时间累加所述经校正的相位区域信号以产生归一化因子并可随时间累加所述位置误差区域信号以产生未换算的位置误差区域值;除法电路,可接收所述归一化因子与未换算的位置误差区域值并可用归一化因子除未换算的位置误差区域值,产生位置误差信号值。 The present invention provides a demodulated data storage means to produce a servo signal demodulation circuit for error signal value, the servo signal comprising a phase field signal and a position error field signal, the demodulation circuit comprising: a correction circuit capable of receiving and correcting the phase field signal and the position error field signal to produce a corrected position error field signal phase field signal and corrected; adder circuit coupled to the correction circuit, can be accumulated over time of the phase-corrected signal region to produce a normalization factor and accumulating the position error field signal over time to produce an unscaled position error field value; the division circuit capable of receiving the normalization factor and the unscaled position error field value and can be normalized factor in addition to the unscaled position error field value, and generates a position error signal value.

本发明降低了对精确锁相环和自动增益控制的要求。 The present invention reduces the accurate phase locked loop and automatic gain control.

附图概述图1是本发明盘驱动器的透视图。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view of a disk drive of the present invention.

图2是盘驱动器中伺服环的框图。 Figure 2 is a block diagram of a disk drive servo loop.

图3是已有技术伺服模式的模式配置。 Figure 3 is a prior art servo pattern mode configuration.

图4是读取头经过图3的伺服模式时该读取头产生的读信号。 Figure 4 is a read head passes over the servo pattern of FIG. 3 when the read head generates a read signal.

图5是读取头经过图3的伺服模式时该读取头产生的读信号。 Figure 5 is a read head passes over the servo pattern of FIG. 3 when the read head generates a read signal.

图6是读取头经过图3的伺服模式时该读取头产生的读信号。 Figure 6 is a read head passes over the servo pattern of FIG. 3 when the read head generates a read signal.

图7是已有技术模拟解调的框图。 Figure 7 is a block diagram of a prior art analog demodulation.

图8是已有技术数字解调的框图。 Figure 8 is a block diagram of a prior art digital demodulation.

图9是本发明伺服模式的模式配置。 Figure 9 is a servo pattern of the present invention, mode configuration.

图10是读取头经过图9伺服模式时该读取头产生的读信号。 FIG 10 is a read head passes over the servo pattern of FIG. 9 when the read head of the read signal is generated.

图11是读取头经过图9伺服模式时该读取头产生的读信号。 FIG 11 is a read head passes over the servo pattern of Figure 9 reads the read head signal generated.

图12是读取头经过图9伺服模式时该读取头产生的读信号。 FIG 12 is a read head passes over the servo pattern of Figure 9 generates a read signal read head.

图13-1至图13-5是与本发明的数字解调器相关的信号的信号波形。 Figure 13-1 to Figure 13-5 is a signal waveform with a digital demodulator of the present invention is related to a signal.

图14是本发明的数字解调器的框图。 Figure 14 is a block diagram of a digital demodulator according to the present invention.

图15-1至图15-2是表示本发明第1实施例的校正值与读信号间关系的定时图。 Figure 15-1 through Figure 15-2 illustrates the present invention is a first embodiment of the school's positive relationship between the read signal and timing diagram.

图16-1至图16-2是表示本发明第2实施例的校正值与读信号间关系的定时图。 Figure 16-1 to Figure 16-2 is a correction of the second embodiment of the present invention is a positive relationship between the read signal and a timing chart.

图17是本发明模拟解调器的框图。 Figure 17 is a block diagram of an analog demodulator of the present invention.

图18-1至图18-11是表示与图17框图相关信号的定时图。 Figure 18-1 to Figure 18-11 shows a block diagram of Fig. 17 associated with the signal timing chart.

图19是图17中使用的模拟除法电路的框图。 Figure 19 is a block diagram 17 used in an analog dividing circuit.

较佳实施例的详细描述图1是本发明有用的盘驱动器100的透视图。 Examples of the preferred embodiment described in detail in FIG. 1 is a perspective view useful for the present invention is a disc drive 100 of FIG. 盘驱动器100包括具有底座102和顶盖(未图示)的壳体。 Disc drive 100 includes a housing having a base 102 and a top cover (not shown). 盘驱动器100还包括通过盘夹具108安装在主轴电机(未图示)上的盘组合。 Disc drive 100 further includes a disc mounted on the spindle motor combination 108 through the disc clamp (not shown) on. 盘组合包含多个可转动地安装在中心轴109周围的单一盘片。 Compositions comprising a plurality of single disc disc mounted around the central shaft 109 rotatably. 各盘表面具有相关的盘片头滑块110,安装在盘驱动器100上用于与盘表面联系。 Each disc surface has an associated disc head slider 110, is mounted on the disk drive 100 for contact with the disc surface. 在图1所示例子中,滑块110由悬臂112支持,后者又固定在致动器116的道存取臂114上。 In the example shown in FIG. 1, a slider 110 supported by the cantilever 112, which in turn is fixed to the actuator arm 116 of the access channel 114. 图1中的致动器属于熟知的转动线圈致动器类型,它包括以118统示的音圈电机(VCM)。 Figure 1 rotating coil actuator are known actuator type, which includes 118 voice coil motor system shown (VCM). 音圈电机118使带有读写头110的致动器116在支轴120周围转动,以沿盘片内径124和外径126间的弧形路径122把读写头定位在期望的数据记录道上。 The voice coil motor 118 of the actuator 116 with a head 110 is rotated around the support shaft 120 to the inner diameter of the disc along the arcuate path 124 and the outer diameter 126 of the head 122 positioned in the desired data recording track . 伺服电子装置130根据读写头110和主计算机(未图示)产生的信号驱动音圈电机118。 Voice coil drive signal servo electronics 110 and read-write head 130 according to a host computer (not shown) generated by the motor 118.

图2是诸如图1的磁盘驱动器100之类的信息存储装置的框图。 Figure 2 is a block diagram of an information storage device such as a diagram 100 of the disk drive 1 and the like. 存储装置228包括3个主要部件:设备230、伺服逻辑单元232和微处理器233。 Storage device 228 includes three main components: device 230, servo logic 232 and microprocessor 233. 微处理器233经主计算机接口234与主计算机(未图示)通信。 The microprocessor 233 (not shown) via the host computer interface 234 to communicate with the host computer. 微处理器233根据从主计算机接收的指令控制信息读、写。 The microprocessor 233 according to the received control instruction information from the host computer to read, write. 具体而言,微处理器233经控制线235向设备230提供控制信号控制设备230的各种功能,包括读写头、写电流强度、读灵敏度及工作模式(读、写或寻找记录道)的选择。 Specifically, the microprocessor 233 via the control lines 230 provide control signals to control various functions of the device 230 to the device 235, including the head, write current intensity, read sensitivity and mode of operation (read, write or find track) of selection. 此外,微处理器233经数据总线237提供写数据并接收读数据。 In addition, the microprocessor 233 via data bus 237 provides the write data and receives read data. 经主机接口234向主计算机提供恢复数据。 234 provided by the host interface to restore data to the host computer. 微处理器233经通过地址总线241和双向数据总线243与其连接的伺服逻辑单元232,控制读写头112在盘片上移动。 The microprocessor 233 via address bus 241 and servo logic 243 bi-directional data bus 232 connected thereto, controlling the head 112 moves onto the disc. 利用地址总线241和数据总线243,微处理器233可在伺服逻辑单元232中的存储位置为读写头存储期望位置。 The use of the address bus 241 and data bus 243, microprocessor 233 may be stored in a location in the servo logic 232 to store a desired location for the head. 伺服逻辑单元232访问该存储位置,以根据存储值与读写头目前位置发出电流指令236至设备230。 Servo logic 232 to access the memory location to store the value based on the current issue and the current head position commands to the device 230 236. 微处理器233也可利用地址总线241和数据总线243检索伺服逻辑单元232的存储位置中所存储的读写头位置信息。 The microprocessor 233 can also use the location information of the head address bus 241 and data bus 243 to retrieve the storage position servo logic 232 is stored in.

在设备230中,功率放大器238接收电流指令236并把电流指令236的电压转换成电流信号240。 In device 230, the power amplifier 238 receives a current command 236 and the current command voltage 236 is converted into a current signal 240. 该电流信号240提供并控制致动器242,后者包含由电流信号的电流驱动并以该电流确定的速率加速的音圈电机134(图1)。 The current signal 240 provides and controls the actuator 242, which contains the driving current of the current signal and to the current acceleration rate determined by a voice coil motor 134 (FIG. 1). 致动器242把电流信号240的电流转化为机械运动244,以相对于媒体移动读写头112。 242 current signal of the actuator current 240 into mechanical movement 244, to move the head relative to the medium 112.

当读写头112相对于媒体移动时,它检测存储在媒体内的数据与伺服模式。 When the head 112 to move relative to the media, it detects the servo pattern data stored in the media. 该伺服模式包含读写头相对于介质的位置信息并使读写头产生含编码位置信息的低电平信号248。 The servo patterns contain information of the head relative to the medium and the head produces a low signal 248 containing the encoded position information. 读写头放大器250放大该低电平信号248,产生放大信号252,该信号对噪声不太敏感且易于解码。 A head amplifier 250 amplifies the low level signal 248 to generate an amplified signal 252, the signal is less sensitive to noise and easy to decode. 放大信号252输入至解调器254,后者解释编码的读写头信号,向伺服逻辑单元232提供解调器位置信息测量值256,并经数据总线239向微处理器233提供数据。 Amplified signal 252 is input to the demodulator 254, which interprets the encoded head signal, a demodulator 232 to provide location information of the measured value to the servo logic unit 256, and 239 provide data to the microprocessor 233 via the data bus.

伺服逻辑单元232把解调器位置测量值256应用于该测量值与读写头实际位置相关的线性表。 Servo logic 232 demodulator position measurement values are applied to the measurement of 256 linear meter values associated with the actual position of the head. 从而,伺服逻辑单元232可确定读写头112的位置并根据该位置与微处理器233设定的期望位置发出新的电流指令236。 Thus, servo logic 232 can determine the position of head 112 and issue a new current command 236 based on the position and the desired position set by microprocessor 233.

对存储装置228有两类基本操作模式。 Storage device 228 has two basic modes of operation. 在第1模式,即熟知的记录道搜索模式中,微处理器233指令伺服逻辑单元232把读写头在媒体上移至新的记录道。 In the first mode, the well-known track search mode, the microprocessor 233 instruction servo logic 232 head to a new track in the media. 在第2种模式即熟知的记录道跟随模式中,微处理器233指令伺服逻辑单元232保持读写头位于记录道中的某一位置上。 In the second mode is known as track following mode, the microprocessor 233 commands the servo logic 232 to maintain the head in a track located in a certain position. 记录道跟随不是完全的被动模式,因为伺服逻辑单元232必须移动读写头以相对于媒体上的记录道保持稳定。 Track follower is not completely passive mode since servo logic 232 must move the head relative to the track on the medium is stable. 记录道包含不规则处,因而伺服逻辑单元232必须移动读写头112以跟随这些不规则处,所以运动是必须的。 Track contains irregularities, and thus servo logic 232 must move head 112 to follow these irregularities, so the movement is necessary. 在跟随记录道期间,利用设备230和伺服逻辑单元232间形成的伺服环在适当位置保持读写头。 In the period following the track, the use of device 230 and the servo loop servo logic unit 232 is formed between the holding head in place. 具体说,当读写头112移开该位置时,读写头读取媒体上存储的伺服模式的不同部分,因而低电平信号248开始改变。 Specifically, when the position of the head 112 is removed, the head read different portions of the storage medium servo pattern, and thus a low level signal 248 begins to change. 该低电平信号248的变化使放大信号252及位置测量值256中产生类似变化。 The low-level signal amplification signal 248 changes make a similar change in position 252 and 256 of the measured values. 根据位置测量值256的变化,伺服逻辑单元232改变电流指令236,从而读写头112移向其记录道上的原始位置。 Based on the position change of the measured value 256, servo logic 232 changes current command 236 so that head 112 is moved to the original position of the recording track.

上述伺服环对记录道上的不规则处具有频度相关响应,即,其对不规则处的响应能力随该不规则处频度增加而降低。 Said servo loop on the recording track of irregularities associated with the frequency response, i.e., their ability to respond to irregularities with the irregularities frequency increases. 在这种意义上,记录道上的不规则处可当作向伺服环的输入信号,而伺服环对这些不规则处的响应可当作伺服环的增益。 In this sense, irregularities track record can be used as an input signal to the servo loop, servo loop responds to these irregularities can be used as the servo loop gain. 对某些读写头,例如磁阻读写头,伺服环的频度响应随记录道中读写头112的位置改变而改变。 For some head, such as the frequency of the magnetoresistive head, the servo loop response vary with the position of the track in the read-write head 112 change. 这样,读写头可对记录道中不同部分的不规则处作出更快的响应。 Thus, the read-write head can track irregularities made in different parts of the faster response.

图3表示已有技术中使用的伺服部分180的零类型伺服磁化模式的主要部分。 Figure 3 shows a prior art servo used in the main part of a null-type servo magnetization pattern portion 180. 盘片122的径向元垂直显示,其角度元水平显示。 Radial disc 122 yuan vertical display, the angle element horizontally. 箭头182指示盘片122的记录道下行方向或角度元。 Arrow 182 indicates the disc 122 track down direction or angle yuan. 箭头184指示盘片122的跨记录道方向或径向元。 Arrow 184 indicates the disc 122 cross track direction or radial yuan. 图3显示四个记录道中心190、191、192和193,分别标以“1”、“2”、“3”、“4”。 Figure 3 shows four track centers 190,191,192 and 193, respectively labeled "1", "2", "3", "4." 读写头134沿跨记录道方向184对准中心“2”。 Head 134 along the cross track direction 184 centering "2."

图3中阴影区域相当于相对于非阴影区为反磁化的区域。 Non-shaded area is the region with respect to the magnetization reversal in the shaded area in Figure 3 corresponds. 例如,在纵向记录系统中,如果非阴影区的纵向磁化是图中从右至左,则阴影区的纵向磁化方向是从左至右。 For example, in a longitudinal recording system, if the longitudinal magnetization in the non-shaded area is the figure from right to left, then the longitudinal magnetization direction of the shaded area is from left to right. 如在数字磁记录系统的标准实践所示,在这些区域中,磁媒体在纵向均是饱和的。 As shown in the standard practice in digital magnetic recording systems, in these regions, the magnetic medium in the longitudinal direction are saturated.

伺服扇区180包括引导区域200、“同步”或“相位”区域202、中间区域204、标准位置误差区域205、正交位置误差区域206和尾区域208。 Servo sector 180 includes a guide area 200, "sync" or "phase" area 202, the intermediate region 204, normal position error field 205, quadrature position error field 206 and end region 208. 引导区域200、中间区域204和尾区域208如图3所示可为“空”,或包含附加伺服数据。 Guide region 200, middle region 204 and end region 208 shown in Figure 3 may be "empty", or include additional servo data. 例如,中间区域204可包含记录道号或扇区号。 For example, the intermediate region 204 may include a track number or sector number. 相位区域202包含径向相干磁变换。 Phase region 202 includes a radially coherent magnetic transitions. 当读写头134经相位区域202时,相位区域202中的磁化模式在读写头134的输出中感应振荡信号。 When the head 134 by phase field 202, phase field 202, the magnetization patterns in the output of the sensor head 134 of the oscillation signal. 标准位置误差区域205和正交位置误差区域206包含零类型磁图。 Normal position error field 205 and quadrature position error field 206 contains a null-type magnetic map. 正交位置位置误差区域206的正交磁图相对于标准位置误差区域205的标准磁图偏移半个记录道。 Quadrature position error field position orthogonal magnetic map 206 relative to the standard position error standard magnetic map area offset 205 half tracks. 在某些零类型伺服模式中,正交磁图分成两半,其一半置于标准磁图前,另一半置于后。 In some types of zero-servo mode, an orthogonal magnetic map divided into two halves, one half placed in front of a standard magnetic map, after another half placed.

图4表示读写头134正好跨越记录道中心线191经相位区域202、中间区域204、标准位置误差区域205和正交位置误差区域206时已有技术的读信号210的波形。 Figure 4 shows head 134 just across the centerline of the track 191 by the phase field 202, middle region 204, normal position error field read signal 205 and quadrature position error field 206 of the prior art waveform 210. 读信号210可按时间分为:读写头经过相位区域时产生的相位区域信号207、读写头经标准位置误差区域205时产生的标准位置误差区域信号212、读写头经正交位置误差区域206时产生的正交位置误差区域214。 Read signal 210 can be divided into time: phase field signal when the head passes over phase field 207 generated, normal position error field signal by the read-write head normal position error field 205 is generated 212, the head position error quadrature quadrature position error field generated in area 206 214. 注意,因为读写头134为产生读信号210而跨越记录道中心线时,准标位置误差区域信号212实际上为零。 Note that, because the head 134 for generating a read signal 210 and across track centerline, the fiducial mark position error field signal 212 is effectively zero.

图5分别是读写头134位于记录道1和2的中心线190和191中途时的读信号216的波形。 5 are located in the read signal head 134 and the center line of the track 1 and 191 2 190 216 midway waveform. 读信号216可分为相位区域信号218、标准位置误差区域信号220和正交位置误差区域信号222,它们分别是读写头134经相位区域202、标准位置误差区域205和正交位置误差区域206时产生的。 Read signal 216 can be divided into phase field signal 218, normal position error field signal 220 and quadrature position error field signal 222, which are read-write head 134 by phase field 202, normal position error field 205 and quadrature position error field 206 when generated. 图6是读写头134处于记录道2和3的中心线191和192中途时的读信号224的波形图。 Figure 6 is a head 134 at the center line of the track 2 and 3 192 191 and the read signal waveform diagram when the middle 224. 读信号224可分为相位区域信号226、标准位置误差区域信号228和正交误差区域信号230。 Read signal 224 can be divided into phase field signal 226, normal position error field signal 228 and quadrature error field signal 230. 注意,图5中的标准位置误差区域信号220与图6的标准位置误差区域信号228相位差180度。 Note that normal position error field signal in Figure 5 normal position error field signal 220 and 228 of FIG. 6 phase difference of 180 degrees.

图7是图2已有技术解调器254一个实施例的解调器300的框图。 Figure 7 is a block diagram of two prior art demodulator 254 of an embodiment of demodulator 300. 解调器300在连至自动增益控制电路302的输入端接收放大信号252。 The demodulator 300 is connected to the automatic gain control circuit 302 receives the amplified signal input terminal 252. 自动增益控制302是包含加法电路304的反馈环路的一部分,该加法电路连至自动增益控制电路302的输出端。 Automatic gain control 302 is part of the adding circuit 304 comprising a feedback loop, the adding circuit is connected to the automatic gain control circuit 302 output. 加法电路304也接收图2的伺服逻辑单元232产生的基准值306。 A reference summing circuit 304 also receives FIG servo logic 232 generates a value of 2 306. 伺服逻辑单元232计算基准值306以确保伺服环的增益在所有记录道位置保持恒定。 The servo logic 232 calculates the reference value 306 in order to ensure a gain of the servo loop remains constant at all track positions. 加法电路304从自动增益控制电路302输出的幅值减去基准值306产生反馈值308,反馈至自动增益控制电路302。 The adder circuit 304 from the output of the automatic gain control circuit 302 subtracts the reference value 306 of the amplitude of a feedback value 308, is fed back to automatic gain control circuit 302. 根据该反馈值308,自动增益控制电路302对放大信号252进行放大,直到自动增益控制电路302的增益控制输出310的幅值大致等于基准值306的幅度。 Based on the feedback value 308, automatic gain control circuit 302 amplifies amplified signal 252 until the automatic gain control circuit 302 controls the gain of the amplitude of the output 310 is substantially equal to the reference value 306 of the amplitude.

向锁相环312和定时电路314提供增益控制输出310,锁相环312利用相位区域信号产生通常是与相位区域信号的相位与频率同步的方波的时钟输出316。 The phase locked loop 312 and a timing circuit 314 provides a gain control output 310, using the phase locked loop 312 is usually generated with the field signal phase and frequency of the phase field signal synchronized square wave output of clock 316. 即使在相位区域信号结束及标准位置误差区域信号开始后,锁相环312仍根据相位区域信号持续产生时钟信号316。 Even after the phase field signal ends and the normal position error field signal begins, the phase locked loop 312 generates a clock signal 316 continued based on the phase field signal. 在增益控制输出310上,标准位置误差信号跟随相位区域信号,与时钟信号316一起提供给乘法器318。 The gain control output 310, normal position error signal follows the phase field signal, with the clock signal 316 to the multiplier 318 together.

乘法器318把标准位置误差信号与时钟信号316相乘产生乘积信号320。 The multiplier 318 normal position error signal 316 is multiplied with the clock signal 320 to generate product signal. 乘积信号320提供至从定时电路314接收定时控制信号的积分器322。 320 to provide a product signal from the timing circuit 314 receives the timing control signal of the integrator 322. 定时控制信号使积分器322在与标准位置误差信号相关的周期的某一部分中对乘积信号320进行积分。 Timing control signal causes the integrator 322 in a certain part of the normal position error signal associated cycle of product signal 320 is integrated. 积分器322的输出是标准位置误差值,该值由多路转换器323转送至保持电路324保持以供以后使用。 Output of the integrator 322 is the normal position error value by the multiplexer 323 transferred to the holding circuit 324 for holding later use.

乘积信号320代表修正型的标准位置误差信号。 320 product signal representative of the normal position error correction type signal. 为获得正确的修正,已有技术要求时钟信号316对标准位置误差信号具有已知和精确的相位关系。 To obtain the correct amendment requires the prior art clock signal 316 to the standard position error signal having a known and precise phase relationship. 任何相位关系的误差使乘积信号320不精确,从而使积分器322产生的标准位置误差值不精确。 Any phase relationship of the error signal 320 so that the product of inaccurate, so that the integrator 322 produces the normal position error value is inaccurate.

在标准位置误差信号后,增益控制输出端上的下一个信号是正交位置误差信号。 After the normal position error signal, the gain control signal at the output of the next is the quadrature position error signal. 该信号也向乘法器318提供,与时钟信号316相乘产生乘积信号320。 This signal is also provided to the multipliers 318, 316 with the clock signal generated by multiplying the product signal 320. 乘积信号320由积分器积分,在积分器322的输出端产生正交位置误差值。 Product signal by the integrator 320 integrating the output of the integrator 322 produces the quadrature position error value. 该正交位置误差值然后由多路转换器323转送至输出端328。 The quadrature position error value from the multiplexer is then transferred to the output terminal 323 328. 输出端328上的正交位置误差值与输出端326的标准位置误差值用于计算读写头在记录道中的位置。 Quadrature position error value and an output terminal 328 on the output terminal 326 of the normal position error value is used to calculate the position of the head in the track. 这种计算在已有技术中是公知的。 This calculation in the prior art are known.

图8是图2的解调器的已有技术一个实施例的数字解调器350的框图。 Figure 8 is a block diagram of a digital demodulator of FIG demodulator 2 an embodiment of the prior art 350. 向自动增益控制电路352提供图2的放大信号252,该电路工作方式类似于图7的自动增益控制电路302。 The automatic gain control circuit 352 provides an amplified signal 252 in FIG. 2, the circuit operates in a manner similar view of an automatic gain control circuit 302 7. 自动增益控制电路352的增益控制输出354提供至加法器356,后者从增益控制输出的幅值中减去基准值358以提供反馈值360。 Automatic gain control circuit 352 provides a gain control output 354 to the adder 356, which subtracts the reference value from the magnitude of gain control output 358 to provide a feedback value 360. 根据反馈值360,自动增益控制电路352向放大信号352施加适当增益。 Based on feedback value 360, automatic gain control circuit 352 amplifies the signal 352 is applied to the appropriate gain. 增益控制输出354也提供给锁相环362,该锁相环根据读信号的相位区域部分产生时钟信号364。 Gain control output 354 is also provided to phase locked loop 362, the phase locked loop 364 generates the clock signal based on the phase field portion of the read signal. 时钟信号的符号由提供表示时钟信号364符号的数字值的正负号函数电路366确定。 Symbol clock signal indicated by the sign function circuit to provide the digital value of the symbol clock signal 364 366 determination.

即使在增益控制输出354的相位区域结束且标准位置误差信号和正交位置误差信号部分开始后,锁相环362产生的时钟信号仍继续产生。 Even if the gain control output 354 ends and the phase field normal position error signal and quadrature position error signal portions begin, the clock signal generated by the phase locked loop 362 continues to produce. 模—数转换器368对标准位置误差区域信号进行取样并转换成一系列数字值。 Analog - digital converter 368 pairs of normal position error field signal is sampled and converted into a series of digital values. 乘法器370把正负号函数输出值与一系列数字信号值相乘,从而通过该乘法器用正负号函数电路366产生的值修正该一系列数字值。 The multiplier 370 sign function output value with a range of digital signal values are multiplied by the multiplier and thus the value of the function with the sign of the correction circuit 366 generates a series of digital values. 乘法器370产生的一系列乘积值输入至加法器372,在定时电路374设定的时间周期中该值相加。 The product of the multiplier 370 to generate a series of input values to the adder 372, the timing circuit 374 to set the period of time values are added. 在多数已有技术系统中,乘积值在与标准位置误差区域信号的中央部分相关的时间周期中累加。 In most prior art systems, the multiplied value is accumulated in the central portion of the normal position error field signal associated time period.

加法器372产生的和由多路转换器376导向保持电路378加以保持供以后使用。 Adder 372 and produced by multiplexer 376 guide the holding circuit 378 to be maintained for later use. 保持电路378的输出是标准位置误差值。 The output holding circuit 378 is the normal position error value.

正交位置误差信号也由模一数转换器368转换成一系列数字值。 Quadrature position error signal also by an analog-digital converter 368 into a series of digital values. 乘法器370把这一系列数字值与时钟信号364的符号相乘。 The multiplier 370 these series of digital values with a clock signal 364 is multiplied symbol. 乘法器370产生的一系列乘积值由加法电路372在定时电路374控制下相加。 A series of product values produced by multiplier 370 are added by an adder circuit 372 at the timing control circuit 374. 相加结果是正交位置误差值,由多路转换器376导向输出端380。 The addition result is the quadrature position error value, the multiplexer 376 the output of the guide 380. 正交位置误差值与标准位置误差值用于计算读写头在记录道中的位置。 Quadrature position error value and the normal position error value is used to calculate the position of the head in the track.

在图7和图8所示系统中,自动增益控制和锁相环必须是没有过度漂移的精密电路。 In the system of Figure 7 and Figure 8, the automatic gain control and phase locked loop must be precise circuits without excessive drift. 由此,在已有技术中,必然化费高昂费用以改进这些电路的性能。 Thus, in the prior art, high costs inevitably expended to improve the performance of these circuits.

图9是本发明使用的伺服区400的磁化模式配置。 Figure 9 is a servo area in the present invention magnetization pattern 400 configuration. 在图9中,读写头134从左至右跨越该图,跨越记录道方向垂直显示,记录道下行方向水平表示。 In Figure 9, head 134 from left to right across the figure, the vertical display direction across the track, the track level indicates the downstream direction. 伺服区400包括引导区域402、相位区域404、中间区域406、标准位置误差区域408、正交位置误差区域410和尾区域412。 The servo region 400 includes a guide area 402, phase field 404, middle region 406, normal position error field 408, quadrature position error field 410 and trailing region 412. 引导区域402、中间区域406和尾区域412与图3所示已有技术伺服区同名区域相同。 Guide region 402, middle region 406 and end regions 412 of the prior art servo region shown in Figure 3 the same region of the same name. 除了相位区域404比已有技术相位区域202较少转换外,图9的相位区域404与图3相位区域202相似。 In addition to phase field 404 than the prior art phase field 202 less conversion, the phase field 404 of FIG. 9 is similar to phase field 202 in FIG. 3. 相位区域404比相位区域202短,因为本发明不需要已有技术中的精确锁相环,从而不需要已有技术相位区域中那样多的转换。 Phase field 404 is shorter than phase field 202 because the present invention does not require accurate prior art phase-locked loop, and thus do not need as much of the prior art phase field conversion. 除了标准位置误差区域408与正交位置误差区域410两者在接近各自区域起始处有一系列径向相干变换414和416外,标准位置误差区域408与正交位置误差区域410分别类似于已有技术的标准与正交位置误差区域205与206。 In addition to normal position error field 408 and quadrature position error field 410 both close to the beginning of the respective regions have a series of radially coherent conversion 414 and 416, the normal position error field 408 and quadrature position error field 410 are similar to the existing Standards and Technology quadrature position error field 205 and 206. 径向相干转换414与416类似于相位区域404中的转换。 Radially coherent transitions 414 and 416 is similar to phase field 404 in the conversion. 这些转换的使用下文作进一步讨论。 These converters use below for further discussion.

图10、11和12分别是读写头在不同记录道位置经图9伺服区400时所产生读信号450、452和454一个例子的定时图。 10, 11 and 12 respectively in the head by a different track position servo region 400 in FIG. 9 when the read signal 450, 452 and 454 produced an example of a timing chart. 具体而言,图11的伺服读信号452是读写头134经图9记录道418中心线时产生的。 Specifically, the servo read signal 11 is generated when 452 418 centerline head 134 by 9 tracks. 读信号452可分成3个部分,由相位区域信号456、标准位置误差信号458和正交位置误差信号460组成。 Read signal 452 can be divided into three portions, the phase field signal 456, normal position error signal 458 and the quadrature position error signal 460 components. 相位区域信号456类似于已有技术图4、5和6中的相位区域信号。 4, 5 and 6 in the phase field signal 456 is similar to the phase field signal prior art FIG. 标准位置误差信号458包括触发振荡部分462与零磁化模式部分464。 The normal position error signal 458 includes a trigger oscillation portion 462 and the zero magnetization pattern portion 464. 读写头134径向经过图9的相干转换414时产生触发振荡部分462。 134 radial head after conversion to produce coherent 9 414 462 trigger the oscillations. 读写头134经过标准位置误差区域408其余部分时产生零图案部分464。 Generated when the head 134 passes over normal position error field 408 the rest of the null pattern portion 464. 产生读信号452时读写头134对准记录道中心线418,因而零图案部分实质上等于零。 Generating a read signal 452 134 head alignment track centerline 418, which is essentially zero zero pattern portions. 正交位置误差信号460可分为触发振荡部分466和零图案部分468,振荡触发部分466由正交位置误差区域410的径向相干转换416产生,零图案部分468由正交位置误差区域410的其余部分产生。 Quadrature position error signal 460 can be divided into a trigger oscillation portion 466 and a null pattern portion 468, the oscillation trigger portion 466 by radially coherent transitions 410 of quadrature position error field 416 generated by the null pattern portion 468 of quadrature position error field 410 the rest of the production.

当读写头134位于图9的记录道中心线418与420之间时产生图10的读信号450。 FIG 10 is a read signal generated between 418 and 420 when the recording head 134 is located in the track centerline 450 of FIG. 9. 读信号450可分为3部分,包括相位区域信号470、标准位置误差区域信号472与正交位置误差区域信号474。 Read signal 450 can be divided into three parts, comprising a phase field signal 470, normal position error field signal 472 and quadrature position error field signal 474. 标准位置误差区域信号472又可细分成触发振荡部分476和零图案部分478。 Standard position error signal 472 area can be subdivided into the trigger oscillation pattern section 476 and section 478 of zero. 正交位置误差区域信号474可分成触发振荡部分480与零图案部分482。 Quadrature position error field signal 474 can be divided into a trigger oscillation portion 480 and null pattern portion 482. 注意,当因读取头位于两记录道中心线间中途,正交位置误差区域信号474的零图案部分482大致为零时,标准位置误差区域信号472的零图案部分478有最大幅值。 Note that, when the result of the read head is located between the two recording track centerline midway, quadrature position error field signal null pattern portion 474 is substantially zero 482, normal position error field signal null pattern portion 472 has a maximum amplitude 478.

当读写头134位于图9记录道中心线418和422中途时,产生图12的读信号454。 When the head 134 is located 9 track centerline 418 and 422 midway generated when the read signal 12 454. 读信号454可分成3个分隔的部分,即相位区域信号490、标准位置误差信号492和正交位置误差信号494。 Read signal 454 can be separated into three parts, namely a phase field signal 490, normal position error signal 492 and the quadrature position error signal 494. 标准位置误差信号492可进一步分成触发振荡部分496和零图案部分498。 The normal position error signal 492 may be further divided into a trigger oscillation portion 496 and a null pattern portion 498. 类似地,正交位置误差信号494可分成触发振荡部分500和零图案部分502。 Similarly, quadrature position error signal 494 may be divided into a trigger oscillation portion 500 and a null pattern portion 502.

当读写头134位于各自记录道中心线中途时产生读信号454与450,因而它们具有共同特征。 Is generated when the head 134 is located in the middle of each track centerline read signals 454 and 450, and thus they have a common characteristic. 例如,读信号450与454的零图案部分482与502两者均大致为零。 For example, a read signal 454, null pattern portions 450 and 482 and 502 are both substantially zero. 此外,读信号450与454的零图案部分478与498分别有最大幅度。 In addition, the read signal null pattern portions 450 and 454 respectively 478 and 498 have a maximum amplitude. 读信号450与454不等同,因零图案部分478与498相位差180度。 Read signals 450 and 454 are not identical, because the zero-phase pattern portions 478 and 498 to 180 degrees. 这类似于已有技术零类型模式中的相移。 This is similar to the prior art type of mode zero phase shift. 读信号450与454不同于已有技术处在于,即使零图案部分彼此移相180度,标准位置误差信号472与492中的触发振荡部分476与496也相同。 Read signal 450 and 454 differs from the prior art is that, even if the null pattern portions shifted from each other by 180 degrees, the normal position error signal 472 and the oscillation portion 492 of the trigger 476 and 496 are also the same. 实际上,由图9伺服区400产生的任何标准位置误差区域信号的触发振荡部分均相同。 In fact, any trigger oscillation portion normal position error field signal is generated by the servo field of FIG. 9 400 are the same. 类似地,在伺服区400的所有读写头位置,本发明正交位置误差信号的触发振荡部分均相同。 Similarly, in all the head position servo region 400, trigger oscillation portion quadrature position error signal of the present invention are the same. 触发振荡部分的一致性。 Consistency trigger oscillation portion. 如下所述可简化电路设计。 Follows simplify circuit design.

图14是本发明解调器520一个实施例的框图。 Figure 14 is a block diagram of a demodulator 520 of the present invention is an embodiment. 该解调器是数字解调器,把图2的放大信号252转换成两个位置误差信号。 The demodulator is a digital demodulator, the amplified signal 252 in FIG. 2 into two position error signals. 通过使用本发明的区域比技术,解调器520降低了对自动增益控制电路及锁相环的要求。 By using the area ratio of the present invention technique, the demodulator 520 reduces the need for automatic gain control circuit and phase locked loop requirements. 参照图14和图13-1至13-5的定时图,下文说明解调器520的配置和工作。 Referring to FIG. 14 and FIG. 13-1 to 13-5 of the timing diagram, described below to configure the demodulator 520 and the work.

图13-1表示读信号522,它是图14的放大信号252的一部分。 Figure 13-1 shows a read signal 522, which is part of the amplified signal 252 of FIG. 14. 读信号522提供给模—数转换器524,它根据触发振荡器526产生的取样时钟在选定的采样点采样读信号。 Read signal 522 to an analog - digital converter 524, which samples the read signal at selected sampling points based on the trigger oscillator 526 generates the sampling clock. 图13-2显示触发振荡器526产生的采样时钟信号528的定时图。 Figure 13-2 shows the sampling clock signal triggered oscillator 526 generates a timing diagram 528. 采样时钟信号528的每个正转换沿使模—数转换器524在该时刻采样读信号522,并把采样值转换成数字值。 Each of the sampling clock signal 528 is converted along the mold - digital converter 524 samples the read signal 522 at that time, and converts the sampled value to a digital value. 在图13-1中,采样点表示为读信号522中的点。 In Figure 13-1, the sampling point is represented as a read signal 522 points. 在图13-1、13-2和14的实施例中,采样时钟信号的频率是读信号基频的4倍。 In the embodiment of FIG. 13-1, 13-2 and 14, the frequency of the sampling clock signal is read four times the fundamental frequency signal. 但,采样时钟信号528的频率不需是读信号522频率的整数倍。 However, the frequency of the sampling clock signal 528 need not read signal 522 is an integer multiple of the frequency. 实际上,可使用提供读信号522的足够采样率的任何频率。 In fact, any frequency of the read signal 522 to provide a sufficient sampling rate may be used.

触发振荡器526根据来自序列发生器534的控制信号产生采样时钟信号528。 Triggered oscillator 526 according to a control signal from the sequence generator 534 generates the sampling clock signal 528. 序列发生器534包含公知的零相位再启动电路,它利用部分读信号522,产生图13-3的压控振荡器(VCO)使能信号536和图13-4的压控振荡器(VCO)启动信号538。 Sequencer 534 contains a known zero phase restart circuit, which uses part of the read signal 522, FIG. 13-3 generates a voltage controlled oscillator (VCO) 536 and the enable signal 13-4 of FIG VCO (VCO) start signal 538. 为产生VCO使能信号536与VCO启动信号538,序列发生器534利用分别位于伺服区的相位区域、标准位置误差区域和正交位置误差区域起始处的转换。 VCO to generate the enable signal 536 and start VCO 538, sequencer 534 are located in the use of the phase servo zone area, converting normal position error field and quadrature position error field at the start. 参照图9,序列发生器534分别利用与相位区域404关联的前四个转换及标准位置误差区域408与正交位置误差区域410的径向相干转换414与416。 Referring to Figure 9, the first four conversion and normal position error field 534, respectively, the use of the sequencer 404 is associated with the phase field 408 and quadrature position error field radially coherent transitions 414 and 410 416. 序列发生器534确保触发振荡器526在伺服区400的各区域以一致的相位关系启动。 Sequencer 534 ensure that triggered oscillator 526 in the regions of the servo region 400 in a consistent phase relationship start. 为确保该相位关系,序列发生器534在各区域末尾禁止触发振荡器526并在各区域始端再使能触发振荡器526。 To ensure that the phase relationship, sequencer 534 at the end of the regional ban triggered oscillator 526 and ends at the beginning of each region and then enable the trigger oscillator 526.

采样时钟信号528也提供至图14的校正值发生器540,在采样时钟信号528的每个正阶跃产生校正值。 The sampling clock signal 528 is also provided to the correction value generator 540 in FIG. 14, 528 in each of the sampling clock signal generating step is a correction value. 校正值发生器540产生的校正值提供至乘法器542,该乘法器还接收模—数转换器524产生的数字值。 Correction correction generator 540 generates positive value provided to the multiplier 542, which also receives the analog multiplier - digital converter 524 digital values generated. 乘法器542把校正值与采样数据值相乘产生一系列乘积值,输入至加法电路546。 Correction multiplier 542 multiplies the value of the sampled data to produce a series of product value, the input to the adder circuit 546. 校正值发生器540与乘法器542一起校正模—数变换器524产生的值。 Correction generator 540 and 542 along with multiplier calibration mode - value generated digital converter 524. 该校正可包含下述简单校正:模—数变换器524产生的所有负值均乘-1校正值,而模—数变换器524产生的所有正值均乘+1的校正值。 Correction may contain the following simple correction: mold - all negative values are multiplied by -1 524 school-digital converter to generate positive value, and mold - all positive-digital converter 524 are generated by multiplying the correction +1. 在另外实施例中,校正值发生器540产生的校正值可更复杂,以抑制噪声采样值或位于读信号不希望部分的采样值。 In a further embodiment, the correction of the correction value generator 540 generates a positive value can be more complex, in order to suppress noise in a read signal sample values or undesirable sampled value portion.

图15-1和图15-2是与本发明一个实施例有关的定时图,其中,选择校正值以抑制取自读信号的噪声采样。 Figure 15-1 and Figure 15-2 is a timing diagram of an embodiment of the invention relating, wherein selecting the correction value in order to suppress noisy samples taken from the read signal. 具体而言,图15-1显示具有黑点所表示采样点的读信号600。 Specifically, Figure 15-1 shows with a black dot represents a read signal 600 sampling points. 图15-2显示校正值发生器540产生的校正值,其值垂直对准各采样点,两者相乘产生图14的乘积值540。 Figure 15-2 shows calibration correction generator 540 generates positive value, the value of the vertical alignment of each sampling point, the two values are multiplied to produce 14 540 product. 从图15-1与图15-2可见,读信号峰值的采样点依据其符号乘1或-1。 As seen in Figure 15-1 and Figure 15-2, the read signal peak sampling points according to their sign by 1 or -1. 例如,因采样值602是负,因而采样值602乘-1校正值604,而采样值606为正,故该值乘+1校正值608。 For example, due to the value of 602 samples are negative, and thus the value of 602 multiplied by -1 sample correction 604, while 606 samples are positive, so the value is multiplied by 608 +1 correction. 在图15-1与15-2中,幅值接近于零的采样值乘校正值零。 In Figure 15-1 and 15-2, the amplitude of the sampled value is close to zero, zero multiplied by the correction value. 例如,采样值610在读信号600中接近于零,该值乘零校正值612。 For example, 610 sample values close to zero in read signal 600, the value is multiplied by the correction value 612 of zero. 通过把这种低幅值的采样值乘零,本发明抑制了这些值并防止它们影响位置误差值计算。 By such low magnitude sample values multiplied by zero, the present invention suppresses these values and prevents them from impact position error value calculation. 这些低幅值的值常被噪声污染,因而这种校正提供了本发明的一个优点。 These values are often low amplitude noise pollution, and thus this correction provides an advantage of the present invention. 通过抑制这些低幅值的值,也抑制了与之相关的噪声。 By suppressing these low magnitude values is also suppressed associated noise.

图16-1与图16-2示出本发明的第2实施例,其中利用校正值抑制取自读信号620的不希望采样点。 Figure 16-1 and Figure 16-2 shows a second embodiment of the present invention, wherein using the correction values read inhibition signal 620 from unwanted samples. 读信号具有峰值622与624等峰值及肩部626与628。 Read signal having a peak like a peak 622 and 624 and shoulder 626 and 628. 肩部626与628表示读信号620不理想的部分。 Shoulder 626 and 628 indicates a read undesirable part of the signal 620. 取自肩部626与628的采样点不能正确表示媒体中存储的转换。 From the shoulder 626 and 628 sampling points are not correctly represent the stored media conversion. 在图16-1与图16-2所示的本发明实施例的情况下,用零校正值抑制取自肩部的采样点。 In the present invention, FIG. 16-1 and 16-2 shown in FIG case of the embodiment, the correction value with zero suppression sample points from the shoulder. 与肩部626和628相关的采样点乘校正值零。 626 and 628 associated with the shoulder sampling dot correction to zero. 选择其余校正值以校正取自峰值的采样点。 Select the remaining correction to correct sampling points from the peak. 负值的采样值乘-1,正值采样值乘+1。 Negative samples multiplied by -1, +1 positive samples multiplied.

本领域技术人员理解示于图15-1、15-2、16-1与16-2的实施例仅是校正值实施例的可能例子。 Those skilled in the art understand the embodiment shown in FIG 15-1,15-2,16-1 and 16-2 are only examples of possible embodiments of the correction value. 在本发明范围中可采用及考虑其它校正值序列。 And the correction value may be used to consider other sequences within the scope of the present invention.

回到图14,加法电路546对伺服区中的各区域累加乘积值544序列。 Returning to Figure 14, the addition circuit 546 pairs of the servo area of each region 544 accumulated value of the product sequence. 具体而言,加法电路546对相位区域404、标准位置误差区域408与正交位置误差区域410累加乘积值。 Specifically, the adder circuit 546 pairs of phase field 404, normal position error field 408 quadrature position error field 410 and the accumulated value of the product. 在多数实施例中,进行加法的时间段各区域相同,在各区域中的同样相对瞬时位置相加。 In most embodiments, each region were the same time period of addition, also in each region relative instantaneous position of the sum. 该进行加法的时间段受序列发生器534产生的使能和信号控制并提供至加法电路546。 The time period of addition sequence generator 534 generates an enable signal to control and provide to the adder circuit 546 by.

图13-5示出使能和信号548的定时图。 Figure 13-5 shows the case where the signal 548 can be a timing chart. 使能和信号548具有各自在相位区域信号、标准位置误差区域信号及正交位置误差区域信号期间产生的3个高电平区550、552与554。 Enable signal 548 and 3 have respective high areas produced during the phase field signal, the normal position error field signal and the quadrature position error field signal 550, 552 and 554. 高电平部分550、552与554其持续时间相同,且在相位区域信号、标准位置误差区域信号及正交位置误差区域信号的相同相对时间段产生。 The high portion 550, 552 and 554 the same duration, and at the same relative time period to generate a phase field signal, the normal position error field signal and the quadrature position error field signal. 在多数实施例中,使能和信号548使加法电路546能不在其相加的和中包含各区域信号的前后转换。 In most embodiments, enable sum signal 548 enables summing circuit 546 can be added and is not included in its front and rear regions converted signal. 这有助于避免来自因脉冲拥挤可能被污染的和的转换。 This helps to avoid pulse crowding may be contaminated and the conversion from.

加法电路546产生包含相位区域和、标准位置误差区域和及正交位置误差区域和的一系列和值。 Adding circuit 546 includes a phase region and generating, and the normal position error field and the quadrature position error field and the range and value. 这些和值提供至来自序列发生器534的多路转换器控制信号558控制的多路转换器556。 And provide these values to the multiplexer 534 from the sequencer 558 of the control signal controlling multiplexer 556. 多路转换器556把来自加法电路546的3个和分别传输至寄存器560、562与564。 Multiplexer 556 from the adding circuit 546 and are transmitted to the three registers 560, 562 and 564. 寄存器560、562与564分别存储与相位区域信号、标准位置误差区域信号与正交位置误差区域信号相关的和信号。 Registers 560, 562 and 564 are respectively stored with the phase field signal, the normal position error field signal and the quadrature position error field signal and the signal related.

在本发明中,通过使用区域比技术,即与标准位置误差区域相关的和及与正交位置误差区域相关的和除以与相位区域相关的和,可去除锁相环与自动增益控制。 In the present invention, by using the area ratio techniques, i.e., associated with the normal position error field and the quadrature position error field and the associated phase and divided by the area-related and can be removed by phase-locked loop and automatic gain control. 通过用相位区域和除每个位置误差区域的和,本发明对这些和进行归一化且消除了对所有3个区域公共的增益因子。 By addition to each of the phase field and position error field and, of these, and the present invention were normalized and eliminates common to all three regions of the gain factor. 除法电路566执行相位区域和除标准位置误差区域和的除操作,产生第1位置误差信号估值。 Dividing circuit 566 in addition to the implementation of the phase field and position error field and the standard addition operation, generates a first position error signal estimate. 除法电路568执行相位区域和除正交位置误差区域和的除法操作,产生第2位置误差信号估值。 Divider circuit 568 to perform phase region and in addition to the quadrature position error field and divide operation, generates a second position error signal estimate. 第1与第2位置误差信号估值用公知技术组合以确定读写头在记录道中的位置。 The first and the second position error signal estimate with known techniques are combined to determine the position of the head in the track.

由本发明示于图14的解调器进行的归一化消除因解调硬件可能产生的位置误差采样中的某些误差。 Expressed by the present invention in FIG demodulator 14 is normalized to eliminate errors due to sampling position demodulation hardware may produce some errors. 为说明这点,模—数转换器524产生的采样读数据可如下确定:y*(t)=Y(t)δ(t-nT1) 式(1)式中,y*(t)是采样的读数据,Y(t)是模—数转换器524接收的放大信号,t是时间,δ是脉冲函数,n是采样数,(TS)是采样时钟周期。 To illustrate this point, analog - digital converter 524 samples the read data can be determined as follows: y * (t) = Y (t) δ (t-nT1) of formula (1) wherein, y * (t) is sampled read data, Y (t) is the analog - digital converter 524 amplifies the signal received, t is the time, δ is an impulse function, n is the number of samples, (TS) is the sample clock period.

采样值与校正值相乘并对乘积求和的步骤可如下式所示:Sx=Σn=1NY(t)·δ(t-nTS)·Rn]]>式(2)式中,Sx是图14加法电路546产生的和,Rn是与第n个采样值相关的校正值,N是整个区的采样数。 Step sampled values multiplied with the correction value and the sum of products of formula as follows: Sx = & Sigma; n = 1NY (t) & CenterDot; & delta; (t-nTS) & CenterDot; Rn]]> formula (2) in, Sx is an adder circuit 546 in FIG. 14 and generated, Rn is the n th sample values associated correction value, N is the number of samples of the entire area. 在图14中,式(2)的和是在3个分隔区中取得的。 In Figure 14, the formula (2) and is made in three separated areas. 从而,读信号可如下分成3部分:YnPEF(t)=AnPEFf(t) 式(3)YqPEF(t)=AqPEFf(t) 式(4)YPF(t)=APFf(t) 式(5)其中:YnPEF(t)是来自标准位置误差区域的读信号,AnPEF(t)是标准位置误差区域中读信号的幅值,f(t)是表示所有3个区域中读信号的通用函数,YqPEF(t)是来自正交位置误差区域的读信号部分,AqPEF(t)是正交位置误差区域中读信号的幅值,YPF(t)是相位区域读信号,APF是相位区域读信号的幅值。 Thus, the read signal may be divided into the following three parts: YnPEF (t) = AnPEFf (t) of formula (3) YqPEF (t) = AqPEFf (t) of formula (4) YPF (t) = APFf (t) of formula (5) wherein : YnPEF (t) is the read signal from the normal position error region, AnPEF (t) is the amplitude of the normal position error field read signal, f (t) is represented in all three regions of the read signal generic function, YqPEF ( t) is the read signal portion from the quadrature position error field, AqPEF (t) is the amplitude of the quadrature position error field read signal, YPF (t) is the phase field read signal, APF is the amplitude of the phase field read signal .

对式(2)、(3)和(5)进行组合,图14除法电路566进行的除法可表示如下:PES1=Σn=1NAnPEFf(t)·δ(t-nTS)·RnΣn=1NAPFf(t)·δ(t-nTS)·Rn]]>式6式中,PES1是除法电路556产生的第1位置误差信号估值。 Of formula (2), (3) and (5) are combined, the divider 14 dividing circuit 566 can be expressed as follows: PES1 = & Sigma; n = 1NAnPEFf (t) & CenterDot; & delta; (t-nTS) & CenterDot; Rn & Sigma ; n = 1NAPFf (t) & CenterDot; & delta; (t-nTS) & CenterDot; Rn]]> Formula 6 wherein, PES1 is the first position error signal estimate produced by division circuit 556.

假定f(t)在标准位置误差区域与相位区域是相同的且在该两区域中采样时钟相位相同,要求标准位置误差区域中所用的校正值与相位区域中所用的校正值匹配,则式(6)可简化为:PES1=AnPEFAPF]]>式7类似地,除法电路568执行的除法可表示为:PES2=Σn=1NAqPEFf(t)·δ(t-nTS)·RnΣn=1NAPFf(t)·δ(t-nTS)·Rn]]>式8式中,PES2表示除法电路568产生的第2位置误差信号。 Assume that f (t) in the normal position error field and the phase field is the same and the sampling in the two regions in the clock phase the same, require the correction value and the phase field normal position error field used in the used correction value match, then the formula ( 6) can be simplified to: PES1 = AnPEFAPF]]> Formula 7 Similarly, a divider dividing circuit 568 execute can be expressed as: PES2 = & Sigma; n = 1NAqPEFf (t) & CenterDot; & delta; (t-nTS) & CenterDot; Rn & Sigma; n = 1NAPFf (t) & CenterDot; & delta; (t-nTS) & CenterDot; Rn]]> Formula 8 wherein, PES2 represents the second position error signal produced by the dividing circuit 568. 利用上述假设,式(8)可简化为:PES2=AqPEFAPF]]>式9式(7)与式(9)表示,通过除法电路566与568进行的除法运算,可去除f(t)中始终出现的任何误差。 With the above assumptions, equation (8) can be simplified to: PES2 = AqPEFAPF]]> Formula 9 of formula (7) and (9), by division of the dividing circuit 566 and 568 carried out, can be removed f (t) is always Any errors occur. 此外,若一个伺服区中的各区域采样周期相同,则在式(7)及(9)中可消去采样周期Ts,因而可知,只要在单个伺服区中各区域采样周期一致,并不要求各伺服区的采样周期均相同。 In addition, if a servo area of each sampling period the same region, in the formula (7) and (9) can be eliminated by the sampling period Ts, and therefore found that, consistent with the regional sampling period as long as a single servo region, not requiring sampling period are the same servo region. 这样,就不需要各伺服区采样时钟相同,因而不需要高精度的锁相环。 Thus, it does not require the same sampling clock for each servo region, and thus does not require highly accurate phase locked loop. 代之以,如图14所示,可使用一致的触发振荡器。 Instead, as shown in FIG. 14, a consistent triggered oscillator can be used. 应注意,只要Rn在伺服区的各区域中是一致的,Rn可取任何值。 It should be noted, as long as Rn in the servo area of each region are consistent, Rn take on any value. 这样,Rn可选择成排除噪声采样值,而不影响位置误差信号估值。 Thus, Rn can be selected to exclude the sampling value of the noise, without affecting the position error signal estimate. 此外,可在不同伺服区使用不同Rn值,使解调器性能最佳。 In addition, different Rn values can be used at different servo areas, so that the best performance of the demodulator.

即使本发明,某些误差也可对位置误差信号估值产生负面影响。 Even if the present invention, some errors can also have a negative impact on the estimate position error signal. 详细说,若触发振荡器的频率在相位区域的差异甚于在位置误差区域,或各触发振荡器在区域不同的相对时间启动,则位置误差信号估值中可产生误差。 In detail, the phase difference in the frequency region even if the triggered oscillator is in the position error field, the or each flip-flop in different relative start time zone, then the position error signal estimate error may be generated. 这些影响可由下式得出:PES1=AnPEFΣn=1Nf(t)·δ(tn(TS+TE)-SE)·RnAPFΣn=1NAPFf(t)·δ(t-nTS)·Rn]]>式10式中,累加值相除表示误差系数,它与标准位置误差区域信号幅值与相位区域信号幅值的比值相乘。 These effects is given by: PES1 = AnPEF & Sigma; n = 1Nf (t) & CenterDot; & delta; (tn (TS + TE) -SE) & CenterDot; RnAPF & Sigma; n = 1NAPFf (t) & CenterDot; & delta; (t-nTS ) & CenterDot; Rn]]> 10 wherein the formula, represents the accumulated value divided by the error coefficient, the ratio of which with the normal position error field signal amplitude and phase field signal amplitude is multiplied. 在式(10)中,TE表示标准位置误差区域的采样周期与相位区域采样同期的差,SE表示触发振荡器在标准位置误差区域启动与在相位区域启动时的启动误差。 In the formula (10), TE represents the sampling period and phase position error regional standards poor sampling area earlier, SE shows the trigger oscillator startup error in the standard error of the area started with the start position in the phase region. 可对PES2写出类似等式,描述触发振荡器526引入第2位置误差信号估值的误差。 PES2 can write similar equations describing introduce errors triggered oscillator 526 second position error signal valuations. 根据上述式子,本发明发现为使解调误差小于记录道宽度的1%,启始时间差应小于数据周期的约0.7%。 According to the above formula, the present invention is found to be demodulated error is less than 1% of the track width, starting time difference should be less than about 0.7% of the data cycle.

本发明也可实施为模拟解调器700,其框图示于图17。 The present invention may also be implemented as an analog demodulator 700, which block is shown in Figure 17. 在解调器700中,序列发生器702接收图2的放大信号252,该序列发生器为解调器700的其余部分提供不同定时信号。 In the demodulator 700, the sequencer 702 receives amplified signal 252 of FIG. 2, the sequence generator to provide timing signals for the remainder of a different demodulator 700. 序列发生器702基于放大信号252产生这些定时信号。 Sequence generator 702 based on the amplified signal 252 to generate these timing signals. 其一个例子示于图18-1的定时图。 An example of which is shown in the timing chart of FIG. 18-1. 序列发生器702产生的两个信号是示于图18-3定时图的压控振荡器(VCO)使能信号704与示于定时图18-4的压控振荡器(VC0)启动信号706。 Two signals generated by sequence generator 702 is shown in the timing chart of FIG. 18-3 voltage-controlled oscillator (VCO) 704 and an enable signal shown in the timing chart of the voltage controlled oscillator (VC0) 18-4 start signal 706. VCO使能信号704提供给触发振荡器708产生示于图18-2的乘法时钟信号710。 VCO 704 is supplied to the enable signal generation triggered oscillator 708 shown in FIG. 18-2 multiplication clock signal 710. 触发振荡器708也从序列发生器702接收VCO启动信号706。 Triggered oscillator 708 also receives from the sequencer 702 VCO enable signal 706. VCO使能信号704为高电平,触发振荡器708在VCO启动信号706变高后开始产生乘法时钟信号710。 VCO enable signal 704 is high, the trigger oscillator VCO 708 starts at the beginning of the clock signal to generate a multiplication signal goes high after 706 710. 触发振荡器708继续产生乘法时钟信号710直到VCO使能信号704返回低电平。 Trigger oscillator 708 continues to generate a clock signal 710 until the VCO multiplication enable signal 704 returns low. 在本发明多数实施例中,乘法时钟信号710是在负与正电平间振荡的方波时钟信号。 In most embodiments of the present invention, the multiplication clock signal 710 is in the oscillation between a positive level and a negative square wave clock signal.

通过VCO使能信号704与VCO启动信号706,序列发生器702在伺服区域的各区中再启动时钟信号710。 By VCO enable signal 704 and start VCO 706, sequencer 702 districts in the servo area and then start the clock signal 710. 具体而言,在读写头每次进入相位区域、标准位置误差区域和正交位置误差区域时再启动时钟信号710。 Specifically, in the head every time you enter a phase region, when normal position error field and quadrature position error field and then start the clock signal 710. 序列发生器702根据各区的第1组转换产生VCO使能信号704与VCO启动信号706。 VCO 702 sequencer generates an enable signal 704 and start VCO 706 according to the district's Group 1 conversion. 序列发生器702使用相位区域的第1组转换及与标准位置误差区域与正交位置误差区域的振荡触发部分(例如图9的振荡触发部分414与416)关联的各组转换。 Sequencer 702 uses the phase field group and the first conversion normal position error field and the quadrature position error field of the oscillation trigger portion (e.g., a trigger oscillation portion 414 in FIG. 9 and 416) associated with each set of conversion. 因序列发生器702利用径向相干转换以启动触发振荡器708,触发振荡器708产生的时钟信号,在各区域中对放大信号252具有相同起始相位关系,而不管读写头的径向位置。 Due to the use of the sequencer 702 radially coherent transitions to start triggered oscillator 708, triggered oscillator 708 generates a clock signal, in the respective regions of the amplified signal 252 has the same starting phase relationship, regardless of the radial position of the head .

在本发明中,乘法时钟信号710的频率不必与放大信号252的基频相同。 In the present invention, the multiplication clock signal frequency amplified signal 710 need not be the same as the frequency of the base 252. 此外,也不必是放大信号252基频的整数倍。 In addition, the amplified signal 252 need not be an integer multiple of the fundamental frequency.

乘法时钟信号710与放大读信号252均提供至乘法器712,后者把该两信号相乘以提供模拟乘积信号714。 Multiplication clock signal 710 and amplified read signal 252 are provided to the multiplier 712, which converts the two signals are multiplied to provide an analog product signal 714. 模拟乘积信号714可分成表示与伺服区的相位区域、标准位置误差区域、正交位置误差区域相应的放大信号252的3部分。 Analog product signal 714 can be divided into phase field represents the servo area, normal position error field, the quadrature position error field signal 3 corresponding amplification portion 252.

在示于图18-5的定时图的VCO启动信号706与积分器使能信号718的控制下,积分器716把乘积信号714的各部分进行积分。 In start VCO shown in a timing chart of FIG. 18-5 706 enable signal 718 and the integral control, the integrator 716 of each portion of product signal 714 is integrated. 在乘积信号714的各部分起始部分,VCO启动信号706使积分器716复位。 At the beginning of each portion of product signal 714, VCO 706 start signal 716 to reset the integrator. 积分器使能信号718在乘积信号714的各部分短时间使积分器716能工作。 Integration enable signal 718 in various parts of the product of the signal integrator 714 716 short-term work. 在一个实施例中,使积分器716能工作的期间排除相位区域的起始和末尾转换、标准位置误差区域的零图案部分及正交位置误差区域的零图案部分。 In one embodiment, so that the integrator 716 to work during the start and end of the phase field exclusion conversion, null pattern portion null pattern portion of normal position error field and the quadrature position error field. 在该实施例中,积分期间在乘积信号714的各部分中均相同。 In this embodiment, during the integration period are the same in each portion of product signal 714 in. 从而,与相位区域关联的各部分乘积信号714的积分期间与标准位置误差区域与正交位置误差区域的积分期间相同。 Accordingly, each partial product signal associated with the phase field and during the integration period the integral normal position error field and the quadrature position error field 714 of the same.

每次积分后,积分器716在其输出端产生被积函数720序列产生的模拟值。 After each integration, integrator 716 produces the sequence generator 720 integrand analog value at its output. 被积函数720序列中的第1被积函数是相位区域被积函数,由多路转换器722导至模拟相位区域采样和保持电路724。 Integrand 720 in the sequence of the first phase of the integrand is integrand area, guided by the multiplexer 722 to simulate the phase field sample and hold circuit 724. 多路转换器722根据图18-6所示的多路转换器控制信号726把该被积函数导至相位区域采样和保持电路724。 The multiplexer 722 according to FIG. 18-6 multiplexer control signal 726 shown in the integrand to phase field guided sample and hold circuit 724. 在积分器716对相位区域产生被积函数期间多路转换器控制信号726为高电平,在积分器716为标准位置误差区域与正交位置误差区域产生被积函数期间,多路转换器控制信号726为低电平。 In the integrator 716 produces the phase integrand region is during the multiplexer control signal 726 is high, the integrator 716 for the normal position error field and the quadrature position error field is generated during the integrand, multiplexer control signal 726 is low.

相位区域采样和保持电路724从序列发生器702接收相位载入信号728与相位复位信号730。 Phase field sample and hold circuit 724 from the sequencer 702 receives a phase load signal 728 and phase reset signal 730. 相位载入信号728与相位复位信号730分别示于图18-9与图18-10。 Phase load signal 728 and phase reset signal 730 are shown in Figure 18-9 and Figure 18-10. 相位复位信号730在积分器716刚要产生相位被积函数前使相位区域采样和保持电路724复位。 Phase reset signal 730 in the integrator 716 to produce just before the phase is a function of the phase plot area sample and hold circuit 724 is reset. 相位载入信号728在积分器716刚产生相位被积函数后,把相位区域采样和保持电路724置于从多路转换器722接收相位被积函数的状态。 Phase load signal 728 just after the integrator 716 generates integrand phase, the phase of the regional sample and hold circuit 724 is placed from the multiplexer 722 receives the phase state of the integrand. 上述情况示于图18-9与图18-5,其中,就在积分器使能信号718对相位区域变低电平时,相位载入信号728变高电平。 The above-mentioned situation is shown in Figure 18-9 and Figure 18-5, wherein, in the integration enable signal when 718 pairs of the phase field goes low, the phase load signal 728 goes high. 一旦相位区域被积函数载入相位区域采样和保持电路724,相位区域采样和保持电路724在其输出端732产生相位被积函数直到其复位。 Once the phase field integrand phase region loaded sample and hold circuit 724, a phase field sample and hold circuit 724 generates phase integrand until it is reset at its output 732.

在相位区被积函数后,积分器716产生标准位置误差区域被积函数。 After phase zone integrand integrator 716 produces normal position error field integrand. 该被积函数由多路转换器722转送至位置误差信号采样和保持电路734。 The integrand from multiplexer 722 transferred to the position error signal sample and hold circuit 734. 由分别示于图18-7与18-8的PES载入信号736与PES复位信号738控制位置误差信号采样与保持电路734。 By loading are shown in Figure 18-7 and 18-8 of the PES PES signal 736 and the reset signal 738 to maintain the control position error signal and the sampling circuit 734. PES复位信号在标准位置误差区域被积函数刚产生前使PES采样与保持电路734复位。 PES before the reset signal in the standard position error field integrand produce just make PES sample and hold circuit 734 is reset. 从而使可能保持任何先前值的PES采样和保持电路734清零。 Thereby possible to maintain the value of any previous PES sample and hold circuit 734 is cleared. PES载入信号736设定PES采样和保持电路734使其接收多路转换器722产生的被积函数。 PES PES load signal 736 is set so that the sample and hold circuit 734 integrand multiplexer 722 receives generated. 就在积分器使能信号718变低电平时,PES载入信号736对标准位置误差区域变高电平。 Just as the integration enable signal 718 goes low, PES load signal 736 pairs of normal position error field goes high. 从而,积分器716一产生标准位置误差区域被积函数,PES载入信号736就变成高电平。 Thus, the integrator 716 produces a normal position error field integrand, PES load signal 736 becomes high level. 位置误差信号采样和保持电路734在其输出端740保持标准位置误差区域被积函数直至由PES复位信号738复位。 Position error signal sample and hold circuit 734 holding at its normal position error field integrand output terminal 740 until 738 is reset by PES reset signal.

向除法电路742提供采样和保持电路724与734的输出732与740,该除法电路进行标准位置误差区域被积函数除以相位区域被积函数的除法运算。 Provide a sample and hold circuit 724 and 734 outputs 732 and 740, the divider circuit normal position error field integrand area is divided by the product of a function of the phase division to division circuit 742. 在除法电路输出端744上产生第1位置误差信号估值,向模—数转换器746提供以产生第1数字位置误差信号估值。 Generating a first position error signal estimate at the output of the divider circuit 744, to the analog - digital converter 746 provides to produce a first digital position error signal estimate.

PES复位信号738在积分器716刚产生正交位置误差区域被积函数前使PES采样和保持电路734复位。 PES reset signal 738 generated in the integrator 716 just before the quadrature position error field integrand make PES sample and hold circuit 734 is reset. 然后,PES载入信号736设定PES采样和保持电路734,以便在其输出端740接收正交位置误差区域被积函数并保持该被积函数。 Then, PES PES load signal 736 to set the sample and hold circuit 734, in order to receive the quadrature position error field at its output terminal 740 integrand and holds the integrand. 除法电路742把正交位置误差区域被积函数除以相位区域被积函数以产生向模—数转换器746提供的第2位置误差信号估值。 Divider circuit 742 quadrature position error field integrand phase region is divided by the plot function to produce the mold - the second position error signal estimate provided by digital converter 746. 模—数转换器746把第2位置误差信号估值转换成第2数字位置误差信号估值。 Analog - digital converter 746 of the second position error signal estimate is converted into the second digital position error signal estimate. 在本发明的数字版本中,标准位置误差信号被积函数与正交位置误差信号被积函数除以相位区域被积函数排除了伺服系统引入各被积函数的公共误差。 In the digital version of the present invention, the standard position error signal is integrated functions and quadrature position error signal is divided by the product of a function of the phase field integrand ruled out the introduction of each servo system integrand public errors. 这使本发明可去除AGC电路与锁相环。 This allows the AGC circuit of the present invention can be removed and phase-locked loop.

图19表示图17的除去电路742的一个实施例。 Figure 19 shows removing circuit 742 of Fig. 17 an embodiment. 在图19中,向运算放大器750的反相输入端提供位置误差信号采样和保持电路734的输出740。 In Figure 19, to the inverting input of operational amplifier 750 provides a position error signal sample-and-hold circuit 734 output 740. 运放750的输出馈送至乘法器752,乘法器也接收相位区域采样和保持电路724的输出732。 The output of op amp 750 is fed to the multiplier 752, the multiplier also receives the phase field sample and hold circuit 724 is output 732. 乘法器752的输出向放大器750的同相输入端提供。 The multiplier 752 with the output of the amplifier 750 to the inverting input terminal provided.

虽然上述模拟解调器700的描述是在位置误差区域被积函数被相位区域被积函数除前,模拟值不转换成数字值,但在其它实施例中被积函数可在积分器716后的任意点转换成数字值。 Although the above description of analog demodulator 700 is at a position error field integrand by the phase field integrand before addition, the analog values are not converted to digital values, but in other embodiments the integrand may, after the integrator 716 at any point into a digital value.

总之,本发明提供一种根据读取头110经过相位区域404与位置误差区域408、410时由该读取头110产生的伺服信号522,确定所述读取头110在存储媒体106上的位置的方法。 In summary, the present invention provides a method based on the servo signal read head 110 through the phase field 404 and position error field 408, 410, 110 when generated by the readhead 522, to determine the position of the head 110 on the storage medium 106 of the reading method. 该方法包括对与所述相位区域404关联的伺服信号452的一部分456执行一组解调操作542、546、712、716以产生相位区域值732的步骤。 The method includes the servo signal 404 associated with the phase field 452 of the demodulation part 456 performs a set of operations 542,546,712,716 phase field value to produce a step 732. 该方法还包括对与所述位置误差区域408、410关联的伺服信号452的一部分458、460执行一组解调操作542、546、712、716以产生位置误差区域值并用所述相位区域值除所述位置误差区域值,产生表示读取头在所述存储媒体上位置的位置误差估值744的步骤。 The method further includes performing a set of operations 542,546,712,716 demodulation of the servo signal and the position error field 408, 410, 452 associated with a portion of 458,460 to produce a position error field value and the phase field value with the addition The position error field value is generated to indicate that the read head on the storage medium in step 744 the position of the position error estimate.

本发明还包括确定表示读取头110在存储媒体106上位置的位置误差信号744的方法。 The present invention also includes a method of determining the read head 110 represents the position on the storage medium 106 of the position error signal 744. 该方法包括读取头110经相位区域404以产生相位区域信号456及产生具有部分相位区域信号456设定的相位的相位区域解调信号710、Rn。 The method includes reading head 110 by phase field 404 to generate a phase field demodulating signal phase field signal 456 and generating a phase field signal 456 having a partial set of phases 710, Rn. 读取头110然后经位置误差区域408、410以产生位置误差区域信号456、460。 Readhead 110 and then by the position error field 408,410 to produce a position error field signal 456,460. 产生具有位置误差区域信号458、460的一部分462、466设定的相位的位置误差区域解调信号710、Rn。 Generating position error field demodulating signal having a position error field signal 458,460 setting part 462, 466 a phase of 710, Rn. 解调的相位区域信号710、Rn用于解调相位区域信号456以产生相位区域归一化因子732。 Demodulating phase field signal 710, Rn is used to demodulate the phase field signal 456 to produce a phase field normalization factor 732. 解调的位置误差区域信号710、Rn用于解调位置误差区域信号458、460以产生未换算的位置误差信号值。 Demodulating the position error field signal 710, Rn is used to demodulate the position error field signal 458,460 to produce an unscaled position error signal value of. 由归一化因子732除未换算的位置误差信号值,产生定标的位置误差值744。 By the normalization factor 732 except unscaled position error signal value, and generating the scaled position error value 744.

本发明还包含一种用于伺服信号450、452、454以产生位置误差信号值744的解调电路520、700。 The present invention also includes a demodulation circuit 520,700 for a servo signal 450,452,454 to produce a position error signal value 744. 该解调电路包括:校正电路540、542、708、712,用于校正相位区域信号456、470、490与位置误差区域信息458、460、472、474、492、494,产生经校正的相位区域信号与经校正的位置误差区域信号。 The demodulation circuit comprising: a correction circuit 540,542,708,712, 456,470,490 for correcting the phase field and position error field signal 458,460,472,474,492,494 information, generate a phase corrected region signal and the corrected position error field signal. 该解调电路还包括加法电路546、716,耦联至所述校正电路,可随时间累加所述经校正的相位区域信号以产生归一化因子并可随时间累加所述位置误差区域信号以产生未换算的位置误差区域值。 The demodulation circuit also includes a summing circuit 546,716, coupled to the correction circuit, can be accumulated over time by the phase field signal to produce a corrected normalization factor and accumulating the position error field signal over time to generating position error field value is not converted. 除法电路566、568、742,可接收所述归一化因子732与未换算的位置误差区域值并可用归一化值除未换算的位置误差区域值,产生位置误差信号值744。 Dividing circuit 566,568,742, can receive the normalization factor 732 and the unscaled position error field value and can be used in addition to the normalized value of the unscaled position error field value, and generates a position error signal value 744.

虽然对消除锁相环与自动增益控制作了描述,但本领域技术人员理解,本发明可用于保留锁相环与自动增益控制的盘驱动器。 While the elimination of the phase locked loop and automatic gain control has been described, those skilled in the art appreciate that the present invention may be used to retain the disk drive with the phase locked loop automatic gain control.

应理解,虽然以上结合本发明各实施例的结构和功能的详述,已说明本发明各实施例的种种特征和优点,但这种揭示仅是为了说明,在本发明的原理及所附权利要求广义表示的范围中,可尤其对部件的结构和配置作出改变。 It should be understood, although described in detail above in connection with the structure and function of various embodiments of the present invention have been described various features and advantages of various embodiments of the present invention, but merely to illustrate this disclosure, the principles of the invention and the appended claims Generalized represented range requirements, and may in particular structural components to change the configuration. 例如,不脱离本发明的精神,取决于具体应用,可顺序用相同电路或通过并行电路进行相位和位置误差的解调。 For example, without departing from the spirit of the invention, depending on the application, or may be sequentially by the same circuit for demodulating the phase and position error through the parallel circuit. 也可作出其它修改。 Other modifications may be made.

Classifications
International ClassificationG11B21/10, G11B5/55, G11B21/08, G11B5/596
Cooperative ClassificationG11B21/081, G11B5/59655, G11B5/5552
European ClassificationG11B5/55D2, G11B21/08A, G11B5/596F5
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