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Publication numberCN101248493 A
Publication typeApplication
Application numberCN 200680031148
PCT numberPCT/EP2006/063793
Publication date20 Aug 2008
Filing date3 Jul 2006
Priority date26 Aug 2005
Also published asDE602006009123D1, EP1917662A1, EP1917662B1, US7394608, US7684139, US20070047121, US20080259484, WO2007023012A1
Publication number200680031148.5, CN 101248493 A, CN 101248493A, CN 200680031148, CN-A-101248493, CN101248493 A, CN101248493A, CN200680031148, CN200680031148.5, PCT/2006/63793, PCT/EP/2006/063793, PCT/EP/2006/63793, PCT/EP/6/063793, PCT/EP/6/63793, PCT/EP2006/063793, PCT/EP2006/63793, PCT/EP2006063793, PCT/EP200663793, PCT/EP6/063793, PCT/EP6/63793, PCT/EP6063793, PCT/EP663793
InventorsE埃莱夫特里乌, GA伽奎特, J耶利托, RA哈钦斯, S厄尔策尔
Applicant国际商业机器公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Read channel apparatus for asynchronous oversampling, synchronous fractionally spaced equalization and digital gain control
CN 101248493 A
Abstract  translated from Chinese
公开了一种读取通道接收器设备和方法。 Discloses a read channel receiver apparatus and method. 读取通道接收器链路包含:以固定速率对通过读取数据轨道形成的模拟信号进行异步采样的模拟到数字转换器,其中,数据轨道以符号速率被写入数据存储介质;上采样器与内插器,其与模拟到数字转换器互连。 Read channel receiver chain comprises: a fixed rate to an analog signal formed by reading a data track asynchronously sampled analog to digital converter, wherein the data tracks are written symbol rate data storage medium; upsampler and interpolator interconnected with the analog-to-digital converter. 接收器还包含分数间隔均衡器,其中,内插器以大于符号速率的内插速率向分数间隔均衡器提供信号。 The receiver further comprises fractionally spaced equalizer, wherein the interpolator to interpolate the symbol rate greater than the rate provided to fractionally spaced equalizer signal. 分数间隔均衡器形成同步均衡化信号。 Fractionally spaced equalizer form a synchronized signal equalization. 接收器还包含与分数间隔均衡器互连的数字增益控制模块以及输出最大似然信号序列的序列检测器。 The receiver also includes a fractional spaced equalizer interconnected digital gain control module and output maximum likelihood sequence detector natural signal sequence.
Claims(29)  translated from Chinese
1.一种读取通道,其包含: 异步模拟到数字转换器,其以大于第一速率的速率对通过读取数据轨道形成的模拟信号进行异步采样,其中,所述数据轨道以所述第一速率被写入数据存储介质; 内插器,其与所述模拟到数字转换器互连; 分数间隔均衡器,其与所述内插器互连,其中,所述内插器以内插速率向所述分数间隔均衡器提供内插采样,且其中,所述分数间隔均衡器以均衡化速率形成同步均衡化采样,其中,所述内插速率大于或等于所述均衡化速率,且其中,所述内插速率大于所述第一速率; 增益控制模块,其与所述分数间隔均衡器互连;以及序列检测器,其与所述增益控制模块互连。 A read channel, comprising: an asynchronous analog to digital converter at a rate greater than the first rate to an analog signal formed by reading a data track asynchronously sampled, of which the first, the data track A data rate of the storage medium is written; interpolator, with which the analog to digital converter interconnected; fractionally spaced equalizer, which is interconnected with the inner plug, which is inserted within the interpolation rate The fractional spaced equalizer to provide interpolated samples, and wherein said fractionally spaced equalizer to equalize the rate of formation of equalizing synchronous sampling, wherein said interpolation rate is greater than or equal to the equalization rate, and wherein, The interpolation rate is greater than said first rate; gain control module, with the fractionally spaced equalizer interconnected; and a sequence detector interconnected with said gain control module.
2. 根据权利要求1的读取通道,其还包含在异步领域内以大于所述第一速率的速率对所述模拟信号进行过采样的上采样器。 2. The read channel of claim 1, further comprising in the field of asynchronous rate greater than said first rate of said analog signal sampled through the sampler.
3. 根据权利要求2的读取通道,其还包含第一反馈电路,该电路包含与所述序列检测器以及所述内插器互连的定时控制电路。 3. The read channel of claim 2, further comprising a first feedback circuit which comprises the sequence detector and said interpolator timing control circuit interconnected.
4. 根据权利要求3的读取通道,其还包含第二反馈电路,该电路包含与所述序列检测器以及所述分数间隔均衡器互连的最小均方更新电路。 4. The read channel of claim 3, further comprising a second feedback circuit which comprises the sequence detector and said fractionally spaced equalizer interconnected least mean square update circuit.
5. 根据权利要求4的读取通道,其还包含第三反馈电路,该电路与所述序列检测器以及所述增益控制模块互连。 5. The read channel of claim 4, further comprising a third feedback circuit, the circuit and the sequence detector and said gain control module interconnected.
6. 根据权利要求5的读取通道,其中,所述第二反馈电路与所述第三反馈电路解耦合。 6. The read channel of claim 5, wherein said second feedback circuit and the third circuit is decoupled feedback.
7. 根据权利要求6的读取通道,其中,所述序列检测器包含部分响应最大似然序列检测器。 According to claim 6, the read channel, wherein the sequence detector contains a partial response maximum likelihood sequence detector.
8. 根据权利要求6的读取通道,其中,所述序列检测器包含噪音预测最大似然序列检测器。 According to claim 6, the read channel, wherein the sequence detector contains NEF maximum likelihood sequence detector.
9. 根据权利要求8的读取通道,其中,所述噪音预测最大似然序列检测器包含分支度量计算算法和多个预测器滤波器,其中,所述预测器滤波器被嵌入所述分支度量计算算法,其中,所述算法的每个变化与所述多个预测器滤波器中不同的一个相关联。 9. The read channel of claim 8, wherein the noise predictive maximum likelihood sequence detector comprises a branch metric computation algorithm and a plurality of predictor filters, wherein said predictor filters are embedded in the branch metric calculation algorithm, wherein the algorithm for each of said plurality of changes in prediction filter associated with a different one.
10. —种读取在数据存储介质中编码的信息的方法,其包含以下步骤: 提供读取通道,所述读取通道包含模拟到数字转换器、与所述才莫拟到数字转换器互连的内插器、与所述内插器互连的分数间隔均衡器、与所述分数间隔均衡器互连的增益控制模块以及与所述增益控制模块互连的序列检测器;读取被写入数据存储介质的数据轨道以形成模拟信号,其中,所述数据轨道包含以第一速率编码的信息;以固定的采样速率对所述模拟信号进行异步采样,以形成采样信号; 形成内插采样;以内插速率将所述内插采样提供给所述分数间隔均衡器,其中,所述内插速率大于所述第一速率;以均衡化速率形成同步均衡化采样,其中,所述均衡化速率小于所述内插速率;调节所述均衡化采样的增益;使用所述增益调节后的同步均衡化采样检测表示最大似然序列估计的数据符号。 10. - kind of in the process of reading the information encoded in the data storage medium, comprising the steps of: providing a read channel, the read channel contains an analog to digital converter, and said it intends to digital converter Mo mutual Even interpolator, the interpolator interconnected with the fractionally spaced equalizer, and the fractionally spaced equalizer gain control module interconnected with said gain control module interconnected sequence detector; reads write data storage medium to form a data track analog signal, wherein said data track comprises information encoded at a first rate; fixed sampling rate of the analog signal sampled asynchronously to the sampling signal is formed; the formed interpolation sampling; interpolate the interpolation sampling rate provided to said fractionally spaced equalizer, wherein said interpolation rate is greater than said first rate; to form a synchronized equalization equalization sampling rate, wherein said equalization rate is less than said interpolation rate; adjust the gain of the equalized samples; equalization sampling synchronous detection using said gain adjusted represents the maximum likelihood sequence estimation of the data symbols.
11. 根据权利要求10的方法,其中,所述提供步骤还包含提供上采样器,所述方法还包含以上采样速率在异步领域中进行上采样的步骤,其中, 所述上采样速率大于所述第一速率。 11. The method according to claim 10, wherein said providing step further comprises providing a sampler, the method further comprises the step of sampling rates above will be sampled in the asynchronous area, wherein the sampling rate is greater than the upper first rate.
12. 根据权利要求10的方法,其还包含以下步骤: 提供定时控制电路,该电路与所述序列检测器以及所述内插器互连; 产生定时信号;将所述定时信号提供给所述内插器。 The timing signal is supplied to the; providing the circuit and the sequence detector and said interpolator timing control circuit interconnection,; generating a timing signal: 12. The method according to claim 10, further comprising the step of interposer.
13. 根据权利要求12的方法,其还包含以下步骤: 产生均衡器误差信号;将所述均衡器误差信号提供给所述分数间隔均衡器。 13. The method according to claim 12, further comprising the steps of: generating equalizer error signal; the equalizer error signal to said fractionally spaced equalizer.
14. 根据权利要求13的方法,其还包含以下步骤:产生通过来自所述序列检测器的决策形成的信号估计; 其中,在增益控制之前,所述产生均衡器误差信号的步骤还包含产生包含所述信号估计与延迟均衡化信号之间的差的均衡器误差信号。 14. The method according to claim 13, further comprising the steps of: generating a signal estimate from the decision by the sequence detector formed; wherein, before the gain control, the equalizer error signal generating step further comprises generating comprising The equalizer error signal estimation poor signal equalization and delay between signals.
15. 根据权利要求14的方法,其还包含以下步骤: 产生包含延迟增益调节信号与所述信号估计之间的差的增益控制误差信号;将所述增益控制误差信号提供给所述增益控制^^莫块; 其中,所述产生均衡器误差信号的步骤与所述产生增益控制误差信号的步骤解耦合。 15. The method according to claim 14, further comprising the steps of: generating a gain comprises adjusting the gain of the difference between the delay signal and the signal estimate error between the control signal; said gain control error signal to the gain control ^ ^ Mo block; wherein said step of generating equalizer error signal and the step gain control of the error signal generating decoupling.
16. 根据权利要求15的方法,其中,所述提供序列检测器的步骤还包含提供包含目标的序列检测器,所述方法还包含以下步骤:产生调节后的目标;将所述调节后的目标提供给所述序列检测器; 将所述目标设置到所述调节后的目标。 The adjusted target; generating target adjusted: 16. The method according to claim 15, wherein said providing step further comprises sequence detector provides a detector comprising the target sequence, said method further comprising the steps of provided to the sequence detector; the target is set to the adjusted target.
17. 根据权利要求15的方法,其中,所述提供序列检测器的步骤还包含提供部分响应最大似然序列检测器,且其中,所述检测步骤还包含使用所述部分响应最大似然序列检测器检测表示最大似然序列估计的数据符号。 17. The method according to claim 15, wherein said providing step further comprises sequence detector provides a partial response maximum likelihood sequence detector, and wherein said step of detecting further comprises using said partial response maximum likelihood sequence detection detects represents the maximum likelihood sequence estimation of data symbols.
18. 根据权利要求15的方法,其中,所述提供序列检测器的步骤还包含提供噪音预测最大似然序列检测器,且其中,所述检测步骤还包含使用所述噪音预测最大似然序列检测器检测表示最大似然序列估计的数据符号。 18. The method according to claim 15, wherein said providing step further comprises sequence detector provides NEF maximum likelihood sequence detector, and wherein said detecting step further comprises using the noise predictive maximum likelihood sequence detection detects represents the maximum likelihood sequence estimation of data symbols.
19. 根据权利要求18的方法,其中,所述噪音预测最大似然序列检测器包含分支度量计算算法和多个预测器滤波器,其中,所述预测器滤波器嵌入所述分支度量计算算法中,其中,所述算法的每个变化与所述多个预测器滤波器的不同的一个相关联。 19. The method according to claim 18, wherein said noise predictive maximum likelihood sequence detector comprises a branch metric computation algorithm and a plurality of prediction filter, wherein said filter is embedded in the prediction branch metric calculation algorithm , wherein each change in said algorithm with said plurality of prediction filter associated with a different one.
20. —种适用于可编程计算机处理器的计算机程序产品,其用于使用读取通道读取在数据存储介质中编码的信息,所述读取通道包含模拟到数字转换器、与所述模拟到数字转换器互连的内插器、与所述内插器互连的分数间隔均衡器、与所述分数间隔均衡器互连的增益控制^=莫块以及与所述增益控制模块互连的序列检测器,所述计算机程序产品包含;计算机可读程序代码,其使所述可编程计算机处理器读取被写入数据存储介质的数据轨道以形成模拟信号,其中,所述数据轨道包含以第一速率编码的信息;计算机可读程序代码,其使所述可编程计算机处理器以固定的采样速率对所述模拟信号进行异步采样,以形成采样信号;计算机可读程序代码,其使所述可编程计算机处理器形成内插采样; 计算机可读程序代码,其使所述可编程计算机处理器以内插速率将所述内插采样提供给所述分数间隔均衡器,其中,所述内插速率大于所述第一速率;计算机可读程序代码,其使所述可编程计算机处理器以均衡化速率形成同步均衡化采样,其中,所述均衡化速率小于所述内插速率;计算机可读程序代码,其使所述可编程计算机处理器调节所述均衡化采样的增益;计算机可读程序代码,其使所述可编程计算机处理器使用所述增益调节后的同步均衡化采样检测表示最大似然序列估计的数据符号。 20. - species suitable programmable computer processor, a computer program product, for use in the read channel to read the data encoded information storage medium, the read channel comprising an analog to digital converter, and the analog to-digital converter interpolator interconnected with said interposer interconnect fractionally spaced equalizer, and the fractional spaced equalizer interconnection ^ = Mo gain control block and the gain control module interconnection and The sequence detector, the computer program product comprising; computer readable program code that causes said programmable computer processor to read the data track is written in the data storage medium to form an analog signal, wherein said data track comprises information encoded at a first rate; computer readable program code which causes said programmable computer processor at a fixed sampling rate of the analog signal sampled asynchronously, to form a sampled signal; computer readable program code that causes The programmable computer processor form interpolated samples; computer readable program code which causes said programmable computer processor socket within the interpolated sample rate to said fractionally spaced equalizer, wherein the inner interpolation rate is greater than said first rate; computer readable program code which causes said programmable computer processor to form a synchronized equalization equalization sampling rate, wherein said equalization rate is less than the rate of said interpolation; computer- readable program code that causes said programmable computer processor for adjusting the gain of the equalized samples; computer readable program code which causes said programmable computer processor to synchronize the equalized samples detected after the gain adjustment represents The maximum likelihood sequence estimation of data symbols.
21. 根据权利要求20的计算机程序产品,其中,所述读取通道还包含上采样器,所述计算机程序产品还包含使所述可编程计算机处理器以大于所述第一速率的速率在异步领域中进行上采样的计算机可读程序代码。 21. The computer program product of claim 20, wherein said read channel further comprises a sampler, the computer program product further comprising a programmable computer processor to enable said first rate is greater than the rate in asynchronous computer art upsampling readable program code.
22. 根据权利要求21的计算才M呈序产品,其中,所述读取通道还包含定时控制电路,该电路与所述序列检测器以及所述内插器互连;所述计算机程序产品还包含:计算机可读程序代码,其使所述可编程计算机处理器产生定时信号; 计算机可读程序代码,其使所述可编程计算机处理器将所述定时信号提供给所述内插器。 22. Calculation of claim 21 M was only program product, wherein said read channel further comprises a timing control circuit, the circuit and the sequence detector and said interpolator interconnected; the computer program product further comprising: computer readable program code which causes said programmable computer processor to generate a timing signal; computer readable program code which causes said programmable computer processor to said timing signal to said interpolator.
23. 根据权利要求22的计算机程序产品,其还包含: 计算机可读程序代码,其使所述可编程计算机处理器产生均衡器误差信号;计算机可读程序代码,其使所述可编程计算机处理器将所述均衡器误差信号提供给所述分数间隔均衡器。 23. The computer program product of claim 22, further comprising: computer readable program code which causes said programmable computer processor to generate an equalizer error signal; computer readable program code which causes said programmable computer processing will the equalizer error signal to said fractionally spaced equalizer.
24. 根据权利要求23的计算机程序产品,其还包含: 计算机可读程序代码,其使所述可编程计算机处理器接收来自所述序列检测器决策的信号估计;计算机可读程序代码,其使所述可编程计算机处理器在增益控制前产生包含所述信号估计与延迟均衡化信号之间的差的均衡器误差信号。 24. The computer program product of claim 23, further comprising: computer readable program code which causes said programmable computer processor to receive signals from the sequence detector is estimated decisions; computer readable program code that causes said programmable computer processor before the gain control signal generating comprising the estimate of the delay equalizer error signal difference between signals equalization. 计算机可读程序代码,其使所述可编程计算机处理器将所述均衡化误差信号提供给所述分数间隔均衡器。 Computer readable program code which causes said programmable computer processor to the equalization error signal to said fractionally spaced equalizer.
25. 根据权利要求24的计算机程序产品,其还包含: 计算机可读程序代码,其使所述可编程计算机处理器产生包含延迟增益调节信号与所述信号估计之间的差的增益控制误差信号;计算机可读程序代码,其使所述可编程计算机处理器将所述增益控制误差信号提供给所述增益控制模块;其中,产生所述均衡器误差信号与产生所述增益控制误差信号解耦合。 25. The computer program product of claim 24, further comprising: computer readable program code which causes said programmable computer processor to generate a gain comprises adjusting the gain difference between the delay signal and the signal estimate error between the control signal ; computer readable program code which causes said programmable computer processor to said gain control error signal to the gain control module; wherein, said equalizer generating an error signal and generating said gain error signal to control the coupling solution .
26. 根据权利要求24的计算枳一呈序产品,其中,所述序列检测器包含目标,所述计算机程序产品还包含:计算机可读程序代码,其使所述可编程计算机处理器产生调节后的目标;计算机可读程序代码,其使所迷可编程计算机处理器将所述调节后的目标提供给所述序列检测器;计算机可读程序代码,其使所述可编程计算机处理器将所述目标设置到所述调节后的目标。 After the computer readable program code which causes said programmable computer processor generates adjustment: 26. calculated according to claim 24, one was orange order product, wherein the sequence detector contains the target, the computer program product also includes goals; computer readable program code that causes the programmable computer processor fans will target the regulator is supplied to the sequence detector; computer readable program code which causes said programmable computer processor to the said target is set to the adjusted target.
27. 根据权利要求26的计算机程序产品,其中,所述序列检测器包含部分响应最大似然序列检测器,所述计算机程序产品还包含使所述可编程计算机处理器使用所述部分响应最大似然序列检测器检测表示最大似然序列估计的所述数据符号的计算机可读程序代码。 27. The computer program product of claim 26, wherein said sequence detector comprises a Partial Response Maximum Likelihood sequence detector, the computer program product further comprising contacting said programmable computer processor using the Partial Response Maximum Likelihood However, the sequence detector indicates that the computer maximum likelihood sequence estimation of the data symbols readable program code.
28. 根据权利要求26的计算机程序产品,其中,所述序列检测器包含噪音预测最大似然序列检测器,所述计算机程序产品还包含使所述可编程计算机处理器使用所述噪音预测最大似然序列检测器检测表示最大似然序列估计的所述数据符号的计算机可读程序代码。 28. The computer program product of claim 26, wherein said sequence detector comprises noise predictive maximum likelihood sequence detector, the computer program product further comprises computer cause the programmable processor to use the noise predictive maximum likelihood However, the sequence detector indicates that the computer maximum likelihood sequence estimation of the data symbols readable program code.
29. —种增强由存储服务提供者提供给存储服务用户的服务的方法, 其包含以下步骤:以第一速率将接收自存储服务用户的数据编码到信息存储介质;从所述信息存储介质读取所述数据以形成模拟信号;以固定采样速率对所述模拟信号进行异步采样以形成采样信号;形成内插采样;以内插速率向分数间隔均衡器提供所述内插采样;其中,所述内插速率大于所述第一速率;以均衡化速率形成同步均衡化采样,其中,所述均衡化速率小于所述内插速率;调节所述均衡化采样的增益;使用所述增益调节后的同步均衡化采样检测表示最大似然序列估计的数据符号。 29. - kind of enhanced storage services provided by the service provider to store the user's service, comprising the steps of: receiving a first rate service users from storing data encoded in the information storage medium; read from the information storage medium Take the data to form an analog signal; a fixed sampling rate of the analog signal asynchronous sample to form a sampled signal; interpolated samples within the form; interpolated rate fractionally spaced equalizer to provide interpolated samples of the inner; wherein interpolation rate is greater than said first rate; equalization rate to form a synchronized sampling equalization, wherein said equalization rate is less than the inner interpolation rate; adjusting the gain equalization sampling; using said gain adjusted synchronous sampling detector equalization is the maximum likelihood sequence estimation of data symbols.
Description  translated from Chinese

用于异步过采样、同步分数间隔均衡化以及数字增益控制的读取通道设备技术领域l明劲信息的设备和方法,背景技术人们知道,自动化介质存储库用于提供对大量存储介质的节约成本的访问。 For asynchronous oversampling, equipment and method for synchronizing fractionally spaced equalization and digital gain control of the read channel technology in the field of information equipment l Ming Jin, background people know, the robotic library storage medium for providing a large number of cost savings access. 一般而言,介质存储库包含大量数据存储介质。 In general, media library contains a large amount of data storage media. 在某些实施方式中,这种信息存储与检索系统包含多个存储器槽(storage slot),其上为存储信息的便携式数据存储介质。 In certain embodiments, the information storage and retrieval system comprising a plurality of memory slot (storage slot), on which the portable data storage medium for storing information. 典型的数据存储介质包括一个或一个以上的》兹带、 一个或一个以上的光盘、 一个或一个以上的石更磁盘、电子存储介质等等。 A typical data storage medium comprises one or more of the "tape hereby, one or more than one disc, one or more than one stone disk, electronic storage media, and so on. 随着被写入数据存储介质的信息量的增大,读取该信息以及从噪音中识别有效数据信号变得更加困难。 With the increase of data to be written in the information storage medium, reading the identification information and the data valid signal from the noise becomes more difficult. 所需要的是可靠地读取^L编码到数据存储介质的信息的设备和方法。 What is needed is reliably read ^ L encoding apparatus and method information to a data storage medium. 发明内容本发明提供了一种读取通道(read channel)以及使用该读取通道的方法。 Summary of the Invention The present invention provides a read channel (read channel) and the method of use of the read channel. 读取通道包含:模拟到数字转换器,该转换器对通过读取数据轨道形成的模拟信号进行异步采样,其中,数据轨道以符号速率(symbol rate) 或者由写入均衡化处理指定的速率被写到数据存储介质;内插器,其与模拟到数字转换器互连。 Read channel comprising: an analog-to-digital converter which converts the analog signal formed by reading a data track sampling asynchronously, wherein, in order to track the data symbol rate (symbol rate) or specified by the write equalization processing rate is Data written to the storage medium; interpolator interconnected with the analog-to-digital converter. 读取通道还包含分数间隔均衡器(fractionally-spaced equalizer),其中,内插器以内插速率向分数间隔均衡器提供内插信号,内插速率大于符号速率。 Read channel also includes a fractionally spaced equalizer (fractionally-spaced equalizer), which, within the interpolator interpolated rate fractionally spaced equalizer to provide interpolated signal, the interpolation rate is greater than the symbol rate. 分数间隔均衡器形成同步符号间隔均衡化信号。 Fractionally spaced equalizer form a synchronized symbol interval equalized signals. 读取通道还包含:增益控制模块,该模块与分数间隔均衡器互连;序列检测器,其与增益控制模块互连。 Read channel further comprising: gain control module, which is interconnected with the fractionally spaced equalizer; sequence detector interconnected with the gain control module. 附图说明结合附图,通过阅读下面的详细介绍可更好地理解本发明,在附图中, 相同的参考标号用于表示相同的元件,其中:图1A为一框图,其示出了申请人的读取通道的第一实施例; 图1B为一框图,其示出了申请人的读取通道的第二实施例; 图2为一框图,其示出了申请人的分数间隔均衡器; 图3为一框图,其示出了申请人的读取通道的第三实施例; 图4为一框图,其示出了申请人的读取通道的第四实施例; 图5为一框图,其示出了申请人的读取通道的第五实施例; 图6为一框图,其示出了申请人的读取通道的第六实施例; 图7为一流程图,其概括了申请人的方法中的某些步骤;以及图8为一流程图,其概括了申请人的方法中的附加步骤。 BRIEF DESCRIPTION OF THE DRAWINGS by reading the following detailed description of the present invention will be better understood in the drawings, like reference numerals used to denote the same elements, in which: Figure 1A is a block diagram illustrating the application The first embodiment of the read channel a person; FIG. 1B is a block diagram illustrating the read channel of the applicant to the second embodiment; FIG. 2 is a block diagram showing the applicant's fractionally spaced equalizer ; FIG. 3 is a block diagram illustrating the read channel applicant third embodiment; FIG. 4 is a block diagram illustrating the read channel applicant fourth embodiment; FIG. 5 is a block diagram , which shows the applicant's read channel to a fifth embodiment; FIG. 6 is a sixth embodiment of a block diagram illustrating the read channel of the applicant; Fig. 7 is a flowchart which summarizes the application Some people in a method step; and Figure 8 is a flow chart outlines the applicant's method of additional steps. 具体实施方式参照附图,同样的符号对应于附图所示同样的部件。 DETAILED DESCRIPTION Referring to the drawings, the same reference numerals correspond to like parts shown in the drawings. 本发明的实例将被介绍为在用于从磁带读取信息的读取通道组件中实现。 Examples of the present invention will be described as being implemented in read channel module is used to read information from the magnetic tape. 然而,下面对用于调节多个数字信号幅度的方法的介绍不意味着将本发明限制为^磁带读取信息或限制为数据处理应用,因为这里的本发明可适用于从一般的信息存储介质读取信息。 However, the following description of the method for adjusting a plurality of digital signal amplitude is not meant to limit the invention to read information as ^ tape or limited to data processing applications, because of the present invention may be applied to this information from the general store media read information. 本发明的实例包含通过对模拟信号(其包含被编码到存储介质的信息) 进行异步采样并接着对这些采样进行同步均衡化来从信息存储介质读取信息的设备一一即读取通道一一以及使用该设备的方法。 Examples of the present invention comprises by analog signals (which contains is encoded into the information storage medium) is asynchronous sample and then synchronize these samples equalization device information read from the information storage medium, one that is read channels one by one and methods of using the device. 申请人的方法在图7和8中概括。 Applicants methods summarized in Figures 7 and 8. 现在参照图1A和7,在步骤710中,该方法提供这样的读取通道,其包含:模拟到数字转换器;内插器,其与模拟到数字转换器互连;分数间隔均衡器,其与内插器互连;增益控制模块,其与分数间隔均衡器互连;序列检测器,其与增益控制模块互连。 Referring now to Figures 1A and 7, in step 710, the method provides such a read channel, comprising: an analog-to-digital converter; an interpolator, with the analog to digital converter interconnected; fractionally spaced equalizer, which and interpolation interconnected; gain control module and the fractionally spaced equalizer interconnection; sequence detector interconnected with the gain control module. 在步骤720中,随着带102移过读取头105,读取头105由读取被编码在磁带102上的数据产生模拟信号。 In step 720, as the belt 102 moves past the read head 105, read by the reading head 105 generates an analog signal is encoded data on a magnetic tape 102. 在某些实施例中,写入带102的数据以第一速率一一即符号速率一一被编码。 In certain embodiments, the write data 102 with a first rate to one that is one symbol rate is encoded. 在某些实施例中,第一速率由写入均衡化处理指定。 In some embodiments, the first rate specified by the write equalization process. 读取头105将该模拟信号提供给模拟到数字转换器120。 Readhead 105 provide the analog signal to an analog-to-digital converter 120. 固定频率时钟110向A/D转换器120提供定时信号。 A fixed frequency clock 110 provides timing signals to the A / D converter 120. 在步骤730中,关于用于写入数据符号的时钟异步地对模拟信号进行采样。 In step 730, with respect to the symbol clock for writing data asynchronously sampling the analog signal. 据发现,异步采样通道允许减小的实现复杂性,因为数字锁相环代替了在同步采样中使用的模拟锁相振荡器。 It was found that the channel asynchronous sample allows reducing implementation complexity, because the digital phase-locked loop instead of the analog phase-locked oscillator used in synchronous sampling. 结果,消除了模拟部件中的变化引起的许多问题。 As a result, it eliminates many of the problems caused by the change in the analog part of. 在(N)个数据轨道使用同步采样被读取的情况下, 需要(N)个模拟PLO,即每个通道一个模拟PLO。 In the (N) data using synchronous sampling track to be read, it is necessary (N) analog PLO, that is, one for each channel analog PLO. 相反,在使用实现本发明的方法和设备读取(N)个数据轨道的情况下, 一个整个系统范围内的自由运行(freerunning)的时钟110控制(N) 个模拟信号的采样,以获得对于(N)个通道的异步采样。 In contrast, in the case of using the method and apparatus of the present invention to achieve reading (N) data tracks, a free-running system-wide (freerunning) clock 110 controls (N) sampled analog signal to get to asynchronous (N) channel samples. 在这种情况下, 避免了对(N)个模拟PLO的需求,并使用(N)个数字锁相环。 In this case, eliminating the need for (N) analog PLO, and the use of (N) digital phase-locked loop. 相对于数据速率增加采样速率减小了由于混淆现象引起的误差。 With respect to the data rate increases the sampling rate is reduced due to the error caused by aliasing. 在步骤740中,异步采样的信号被提供给上釆样器(叩sampler) /内插器135,上采样器/内插器135通过以指定的上采样速率进行内插来计算同步采样。 In step 740, the asynchronous sampling signal is supplied to the injector Bian (percussion sampler) / interpolator 135, the sampler / interpolator 135 designated by the sampling rate is interpolated to calculate the synchronous sampling. 在步骤750中,上采样器/内插器135向分数间隔均衡器150提供同步采样。 In step 750, the sampler / interpolator 135 to fractionally spaced equalizer 150 provides synchronous sampling. 因此,该设备和方法结合同步分数间隔均衡化使用异步信号采样。 Thus, the apparatus and method with synchronized fractionally spaced equalization use asynchronous signal sampling. 现在参照图1A、 2、 7,在步骤750中,分数间隔均衡器150以速率p/T接收来自采样器/内插器135的采样。 Referring now to Figure 1A, 2, 7, in step 750, the fractionally spaced equalizer 150 at a rate of p / T received samples from the sampler / interpolator 135. p的值为大于或等于2的整数。 p is an integer value greater than or equal to 2. 均衡器权重wl、 w2、 w3.,wL每q*T/p个延迟元件(从第一个延迟元件前开始)分接出均衡器延迟线。 Equalizer weights wl, w2, w3., WL every q * T / p delay elements (starting before the first delay element) Tap the equalizer delay line. 在步骤760中,分数间隔均衡器150每个数据符号间隔T接收p个输入采样,并且每个T产生一个采样。 In step 760, the fractionally spaced equalizer 150 receives each data symbol interval T p input samples, and each T generates a sampling. 均衡器权重wl、 w2、 w3…wL也每个符号间隔T被更新。 Equalizer weights wl, w2, w3 ... wL each symbol interval T is also updated. 因此,输出采样速率为1/T,而输入采样速率为p/T。 Thus, the output sampling rate is 1 / T, the input sample rate p / T. 权重更新以输出速率1/T发生。 Weight update output rate 1 / T occur. 来自均衡器150的输出包含理想的无失真的失真。 Output from the equalizer preferably comprises a distortion-free 150. 恭-、'-' 、 b , 。 Christine -, '-', b,. 分数间隔均衡器150以1/T的速率向增益控制模块160提供同步均衡化采样。 150 fractionally spaced equalizer with 1 / T rate to gain control module 160 provides synchronous equalized samples. 在步骤770中,增益控制模块160调节均衡化采样的增益。 In step 770, the gain equalization control module 160 samples the gain adjustment. 在步骤780中,增益调节后的同步均衡化采样受到序列检测器170的处理,其中,检测器170被配置为基于检测器决策产生信号估计,例如来自沿着最大似然序列检测器的残余序列的数据决策的信号估计。 In step 780, the synchronous sampling gain adjustment equalization after processing by the sequence detector 170, which detector 170 is configured to generate a signal based on the estimated decision detectors, e.g., from a maximum likelihood sequence detector along the residual sequence decisions estimate data signals. 本领域技术人员将会明了,序列检测器将这些检测到的数据符号提供给对这些数据符号进行解码的解码器。 Those skilled in the art will appreciate, the sequence detector these detected data symbols to these data decoder for decoding symbols. 现在参照图1A和8,读取通道IOO包含第一反馈环,第一反馈环包含通信链路165。 Referring now to Figures 1A and 8, the read channel comprising a first feedback loop IOO, a first feedback loop comprising communication link 165. 在步骤810中,该方法通过序列检测器170产生信号估计199。 In step 810, the method 170 generates a signal by the estimated 199 sequence detector. 在步骤820中,这些信号估计199被提供给增益控制模块160。 In step 820, an estimated 199 of these signals are supplied to the gain control module 160. 读取通道100还包含第二反馈环,第二反馈环包含通信链路166、最小均方("LMS")算法180和通信链路185。 Read channel 100 further comprises a second feedback loop, the second feedback loop comprising communication link 166, a minimum mean square ("LMS") algorithm 180 and a communications link 185. 传统的LMS算法可显示出明显的稳定性与性能缺陷,这些缺陷是由于(1)非恒定、脉冲环境噪音, (2)精度有限的算法,以及(3)与量化以及电子放大器相关联的测量噪音引起的。 The traditional LMS algorithm shows significant stability and performance defects, which is due to (1) non-constant pulse ambient noise, (2) finite precision arithmetic, and (3) to quantify and measure associated with electronic amplifiers Noise-induced. 在某些实施例中,LMS算法180包含"泄漏的(leaky) " LMS 算法,其中,泄漏参数解决由于非恒定的输入、低的信噪比以及精度有限的算法引起的稳定性缺陷。 In certain embodiments, LMS algorithm 180 with "leaks (leaky)" LMS algorithm, which solve the stability parameters leakage defects due to non-constant input, and a low SNR due to the limited accuracy of the algorithm. 在步骤830中,信号估计199净皮提供给LMS算法180。 In step 830, the signal estimate 199 180 Net bark supply LMS algorithm. 在步骤840中, LMS算法180将更新后的一组均衡器系数提供给分数间隔均衡器150。 In step 840, LMS algorithm 180 a set equalizer coefficients updated to the fractionally spaced equalizer 150. 读取通道100还包含第三反馈环,第三反馈环包含通信链路167、定时控制模块l卯、通信链路195。 Read channel 100 also includes a third feedback loop, the third feedback loop includes a communications link 167, the timing control module l d, the communication link 195. 在步骤850中,信号估计199被提供给定时控制模块l卯,定时控制才莫块l卯产生定时信号。 In step 850, the signal estimate 199 is supplied to the timing control module l d, the timing control block was Mo l d generates a timing signal. 在步骤860中,该定时信号被提供给上采样器/内插器135。 In step 860, the timing signal is supplied to the sampler / interpolator 135. 在某些实施例中,该方法从步骤860转移到步骤740,并如这里所介绍的那样继续。 In certain embodiments, the method moves from step 860 to step 740 and continues as described herein, such as. 尽管图8显示出步骤810到860被依次执行,在该设备和方法的某些实施例中,步骤810到860基本上同步地执行。 Although Figure 8 shows the steps 810 to 860 are successively executed, in some embodiments, the apparatus and method, the steps 860 to 810 is substantially in synchronization. 现在参照图1B,图1B为示出读取通道101的框图。 Referring now to FIG. 1B, FIG. 1B is a block diagram showing read channel 101. 读取通道101包含分立的上采样器130和内插器140。 Read channel 101 includes a separate sampler 130 and the interpolator 140. 在读取通道100/101的某些实施例中,将均衡器适配反馈环与增益适配反馈环解耦合。 In the read channel 100/101 in some embodiments, the equalizer adaptation feedback loop and gain adaptation feedback loop decoupled. 在没有解耦合的情况下,这两个反馈环的交互作用可能导致增益和/或均衡器系数移动,其可降低读取通道的整体性能,和/或可在均衡器与增益控制适配未被适当约束的情况下导致适应性环的发散。 In the absence of decoupling case, the interaction of the two feedback loops may cause the gain and / or moving the equalizer coefficients, which can reduce the overall performance of the read channel, and / or control the gain adaptation in the equalizer is not lead to divergent adaptive loop case is properly constrained. 现在参照图3,读取通道300包含增益适配环310,其中,增益控制误差信号使用通信链路340被提供给增益控制模块160,增益控制误差信号包含通过通信链路330提供的来自增益控制才莫块160的延迟输出信号与通过通信链路320提供的由序列检测器170的决策形成的信号估计199之间的差。 Referring now to Figure 3, the read channel 300 comprises gain adaptation loop 310, wherein, the gain control error signal using the communication link 340 is provided to the gain control module 160, the gain control error signal comprising a communication link provided by the gain control 330 from Mo before block 160 and the output signal of the delay signal supplied via a communication link 320 by the sequence detector 170 decisions 199 formed on the difference between estimated. 读取通道300还包含均衡器适配环350,其中,均衡器误差信号通过通信链路380被提供给LMS算法180,均衡器误差信号包含延迟均衡化信号(通过通信链路370提供)与信号估计199 (通过通信链路360提供, 由序列检测器170的决策形成)之间的差。 Read channel 300 further comprises an equalizer adapter ring 350, wherein the equalizer error signal is supplied to the LMS algorithm 180 via the communication link 380, the delay equalizer error signal comprises equalizing signal (provided by a communication link 370) and the signal an estimated 199 (provided through a communication link 360, formed by the sequence detector Decision 170) the difference between. 在某些实施例中,该设备和方法使用采用欧几里德距离度量到部分响应4类(PR4)目标和最大似然序列检测的均衡化, 一种在现有技术中被称为PRML的组合。 In certain embodiments, the apparatus and method of using the Euclidean distance metric to partial response equalization Class 4 (PR4) target and maximum likelihood sequence detection, a condition known in the prior art PRML combination. 在这些PRML检测器实施例中,序列检测器170包含PRML检测器,目标多项式175 (图1A)包含整数系数,即,其中,D 表示延迟运算符。 PRML detectors in these embodiments, sequence detector 170 comprises PRML detector, target polynomial 175 (FIG. 1A) contains integer coefficients, i.e., wherein, D represents a delay operator. 在较高的线性记录密度下,线性PR4均衡器产生相当大的噪音增强。 At higher linear recording density, linear PR4 equalizer considerable noise enhancement. 在该设备和方法的某些实施例中,检测器170包含扩展PRML检测器("EPRML,,)。具有目标多项式的这种EPRML检测器170也为固定结构,其中,目标多项式175不能被适配到变化的通道运行点。在更高的线性记录密度下,EPR4目标可导致进一步的噪音增强。在申请人的设备和方法的某些实施例中,检测器170包含扩展EPRML检测器("E2PRML,,)。 In certain embodiments of the apparatus and method, detector 170 comprises extended PRML detector ("EPRML ,,). Having a target polynomial that EPRML detector 170 is also fixed structure, wherein the target polynomial 175 can not be adapted Change the channel assigned to the operating point. At higher linear recording density, EPR4 target may result in further noise enhancement. In some embodiments of the apparatus and method of the applicant, the detector 170 includes extended EPRML detector (" E2PRML ,,). 具有目标多项式的这种E2PRML检测器170也为固定的结构,其中,目标多项式175不能被适配到变化的通道运行点。 Such a target polynomial E2PRML detector 170 is also a fixed structure wherein the target polynomial 175 can not be adapted to changing channel operating points. 在某些实施例中,据发现,均衡化到短的目标不允许减轻通道与目标的不匹配,且改变总体响应所要求的、接下来的均衡化导致噪音着色(noise coloration)、噪音增强以及结果引起的性能劣化。 In certain embodiments, it was found that equalization is not allowed to target short of the target to reduce the channel does not match, and change the overall response to the requirements of the next equalization coloring cause noise (noise coloration), noise enhancement and The results of performance deterioration caused. 或者,过度增大目标的长度引起最大似然序列检测器的复杂性的、不受欢迎的增大。 Alternatively, the excessive increase in the length of the target caused by the complexity of the maximum likelihood sequence detector however, increasing unpopular. 在某些实施例中,该设备和方法采用噪音预测最大似然("NPML,,) 检测器。通过在到序列检测器的输入上增加噪音白化滤波器并基于较长的有效目标进行序列检测,NPML检测器提供增强的可靠性。在某些NPML 实施例中,目标多项式包含非整数系数。通过允许PR目标多项式采用非整数系数,到通道的更好的匹配是可能的。在某些实施例中,目标多项式175 (图1A, 1B)在包含读取通道100 的信息存储与检索系统的初始化过程中被设置。在其他实施例中,目标多项式175由与包M取通道100的信息存储与检索系统互连的主计算机提供。在该设备和方法的某些实施例中,部分响应目标和分数间隔均衡器祐: 连带地更新。现在参照图4,申请人的读取通道400包含NPML检测器410 和目标适配环440,其中,电路430向NPML检测器410提供更新后的目标420。同时,均衡器输出信号450被用于产生均衡器误差信号,该信号被提供给分数间隔均衡器150。在本实施例中,均衡器结合信号整形与噪音预测的功能。读取通道400还包含固定时钟110、模拟到数字转换器120、上采样器/内插器135 (图1A)或上采样器130 (图1B)与内插器140 (图1B)。 在某些实施例中,读取通道400还包含增益适配环310 (图3),其中,均衡器/目标适配以及定时与增益调节被解耦合,如上面所介绍的那样。现在参照图4和8,在目标适配实施例中,该方法包含步骤870,其中, 该i殳备和方法产生调节后的目标。在步骤880中,该i殳备和方法将调节后的目标提供给NPML检测器410。在某些实施例中,读取通道包含分数间隔均衡器与噪音预测滤波器的分立的实施。例如参照图5,读取通道500包含与噪音预测滤波器510结合的分数间隔均衡器150,噪音预测滤波器510包含噪音预测滤波器更新环520,其中,两滤波器被适应性地调节。读取通道500还包含固定时钟110、模拟到数字转换器120、上采样器/内插器135 (图1A)或上采样器130 (图1B)与内插器140 (图1B)。在某些实施例中,读取通道500还包含增益适配环310 (图3 ),其中,均衡器适配以及定时与增益调节被解耦合,如上面所介绍的那样。在某些实施例中,该设备包含依赖于状态的NPML检测器。现在参照图6,读取通道600包含NPML检测器610,其包含度量计算单元620, 其中,Pk(D), k-0,l,…2xNstates-l表示对应于NPML框架上的第k个变化的一组预测器系数。 In certain embodiments, the apparatus and method using maximum likelihood noise prediction ("NPML ,,) detector. And based on longer valid target sequence detection by increasing the noise whitening filter on the sequence detector input , NPML detector provides enhanced reliability. NPML In some embodiments, the target comprises a non-integer coefficients of a polynomial. PR target polynomial by allowing the use of non-integer coefficients, a better match to the channel is possible. In certain embodiments example, target polynomial 175 (FIG. 1A, 1B) comprising a read channel initialization information storage and retrieval system 100 is provided. In other embodiments, target polynomial 175 and packet by the channel information memory fetch M 100 and the host computer retrieval system interconnection is provided in some embodiments of the apparatus and method, the partial response target and fractionally spaced equalizer woo: updated joint Referring now to FIG. 4, the applicant's read channel 400 includes NPML. detector 410 and the target adapter ring 440, wherein the circuit 430 to provide the updated target NPML detector 410 420. At the same time, the equalizer output signal 450 is used to generate the equalizer error signal which is supplied to the fractional spaced equalizer device 150. In this embodiment, the equalizer combined signal shaping and noise prediction capabilities. read channel 400 also includes a fixed clock 110, an analog-to-digital converter 120, the sampler / interpolator 135 (FIG. 1A) or upsampler 130 (FIG. 1B) and interpolator 140 (FIG. 1B). In certain embodiments, read channel 400 further comprises gain adaptation loop 310 (FIG. 3), wherein the equalizer / target adaptation and timing and gain adjustment is decoupled, as described above. Referring now to FIG. 4 and 8, in the target adapter embodiment, the method comprises the step 870, in which the apparatus and method for generating i Shu target adjusted. In step 880, the apparatus and method i Shu target adjusted to the NPML detector 410. In some embodiments, the read channel comprising implementation fractionally spaced equalizer and noise prediction filter discrete example reference 5, read channel 500 comprises a noise prediction filter 510 combined fractionally spaced equalizer 150, the noise prediction filter 510 comprises a ring 520 updates the noise prediction filter, wherein two filters are adaptively adjusted. read channel 500 further comprises fixed clock 110, analog-to-digital converter 120, upsampler / interpolator 135 (FIG. 1A) or upsampler 130 (FIG. 1B) and interpolator 140 (FIG. 1B). In certain embodiments the read channel 500 further comprises gain adaptation loop 310 (FIG. 3), wherein the equalizer adaptation as well as the timing and gain adjustments are decoupled, as described above. In some embodiments, the apparatus comprising dependent on the state NPML detector. Referring now to Figure 6, the read channel 600 comprises NPML detector 610, comprising 620 metric calculation unit, wherein, Pk (D), k-0, l, ... 2xNstates-l representation corresponds to changes in the k-th frame NPML on a set of prediction coefficients. 读取通道600还包含固定时钟110、模拟到数字转换器120、上釆样器/内插器135 (图1A)或上采样器130 (图1B)与内插器140 (图1B)。 Read channel 600 further comprises fixed clock 110, analog-to-digital converter 120, the sampler Bian / interpolator 135 (FIG. 1A) or upsampler 130 (FIG. 1B) and interpolator 140 (FIG. 1B). 在某些实施例中,读取通道600还包含增益适配环310 (图3),其中,均衡器适配以及定时与增益调节被解耦合,如上面所介绍的那样。 In certain embodiments, read channel 600 further comprises gain adaptation loop 310 (FIG. 3), wherein the equalizer adaptation as well as the timing and gain adjustments are decoupled, as described above. 存储服务提供者可使用该设备和方法向存储服务用户提供增强信息存储服务。 Storage service provider can use the device and method for providing enhanced information storage services to the storage service user. 具体而言,存储服务提供者可通过以符号速率将接收自存储服务用户的数据编码到信息存储介质并在此后从所述信息存储介质读取该数据以形成模拟信号来增强提供给存储服务用户的服务。 Specifically, the storage service provider can be a symbol rate received from the storage service user data is encoded into an information storage medium and thereafter reads the data from the information storage medium to form an analog signal enhancement provided to the storage service user service. 存储服务提供者可使用该设备和方法以固定采样速率对模拟信号进行异步采样以形成采样信号,形成内插采样,并以内插速率将这些内插采样提供给分数间隔均衡器, 其中,内插速率大于符号速率。 Storage service provider can use the device and method at a fixed sample rate analog signal asynchronous sample to form a sample signal form interpolated samples, and the interpolation rate of these interpolated samples to the fractionally spaced equalizer, wherein the interpolation rate is higher than the symbol rate. 存储服务提供者可使用该设备和方法以均衡化速率形成同步均衡化采样(其中,均衡化速率小于或等于内插速率), 调节这些均衡化采样的增益,并使用所述增益调节后的同步均衡化采样检测表示最大似然序列估计的数据符号。 Storage service provider can use the device and method to form a synchronized rate equalization equalization sampling (where equalization rate is less than or equal to the interpolation rate), adjust the gain equalization sampling, and use the gain adjusted synchronous equalization sample testing indicates the maximum likelihood sequence estimation of data symbols. 图7与8所示方法的实施例可分别实现。 7 and the method shown in the embodiment of FIG. 8 respectively realized. 另外,在某些实施例中,可对图7和/或8所示的单独的步骤进行合并、消除或重新排序。 Further, in some embodiments, can separate steps 7 and 8 shown in FIG / or merged, to eliminate or reordered. 在某些实施例中,本发明包含驻留在布置在包含读取通道的数据存储装置中的存储器内的指令,其中,这些指令由布置在包含读取通道的数据存储装置中的处理器执行,以执行图7所示的步骤720、 730、 740、 750、 760、 770和/或780,和/或图8所示的步骤810、 820、 830、 840、 850、 860、 870和/或880。 In certain embodiments, the present invention is contained in the instruction resides in the data storage means is arranged to read the channel comprises a memory, wherein the instructions executed by the data storage device disposed in a read channel comprising a processor , steps to implement 720 shown in FIG. 7, 730, 740, 750, 760, 770 and / or 780, steps and / or 810 shown in FIG. 8, 820, 830, 840, 850, 860, 870, and / or 880. 在其他实施例中,本发明包含驻留在任何其他计算机程序产品中的指令,其中,这些指令由包含读取通道的信息存储与检索系统内部或外部的计算机执行,以执行图7所示的步骤720、 730、 740、 750、 760、 770和/ 或780,和/或图8所示的步骤810、 820、 830、 840、 850、 860、 870和/ 或880。 In other embodiments, the present invention includes instructions residing in any other computer program product, where those instructions from the information storage and retrieval system comprises an internal or external computer executing the read channel, to execute as shown in FIG. 7 Steps 720, 730, 740, 750, 760, 770 and / or 780, and / or step 810 shown in FIG. 8, 820, 830, 840, 850, 860, 870 and / or 880. 在每种情况下。 In each case. 指令可被编码在包括例如磁信息存储介质、光信息存储介质、电子信息存储介质等的信息存储介质中。 Instructions may be encoded in the magnetic information storage medium, including, for example, the optical information storage medium, an electronic information storage medium such as an information storage medium. "电子存储介质" 意p木着例如PROM、 EPROM、 EEPROM、闪速ROM、压缩闪存(compact flash)、智能介质等装置。 "Electronic storage media" means wood with for example p PROM, EPROM, EEPROM, flash ROM, Compact Flash (compact flash), smart media and other devices. 尽管详细示出了本发明的优选实施例,应当明了,在不脱离所附权利要求书所述本发明的范围的情况下,本领域技术人员可想到对这些实施例的4务改和变型。 Although shown in detail a preferred embodiment of the present invention, it should be appreciated that the appended claims without departing from the scope of the invention being described, those skilled in the conceivable embodiments of these 4 service changes and variations.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
CN102668399B *26 Nov 200927 May 2015飞思卡尔半导体公司Receiver and method for equalizing signals
Classifications
International ClassificationG11B20/10, H04N5/52
Cooperative ClassificationG11B20/10027, G11B20/10009, G11B20/10046, G11B20/10055
European ClassificationG11B20/10A4A, G11B20/10A6, G11B20/10A6A, G11B20/10A
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