WO2008135914A3 - Multivalued logic circuit - Google Patents

Multivalued logic circuit Download PDF

Info

Publication number
WO2008135914A3
WO2008135914A3 PCT/IB2008/051671 IB2008051671W WO2008135914A3 WO 2008135914 A3 WO2008135914 A3 WO 2008135914A3 IB 2008051671 W IB2008051671 W IB 2008051671W WO 2008135914 A3 WO2008135914 A3 WO 2008135914A3
Authority
WO
WIPO (PCT)
Prior art keywords
resistors
logic
push
logic circuit
multivalued logic
Prior art date
Application number
PCT/IB2008/051671
Other languages
French (fr)
Other versions
WO2008135914A2 (en
Inventor
Viktor Viktorovich Oleksenko
Original Assignee
Buddha Biopharma Oy Ltd
Viktor Viktorovich Oleksenko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Buddha Biopharma Oy Ltd, Viktor Viktorovich Oleksenko filed Critical Buddha Biopharma Oy Ltd
Priority to EP08738033A priority Critical patent/EP2171847B8/en
Priority to US12/598,669 priority patent/US7859312B2/en
Priority to AT08738033T priority patent/ATE520203T1/en
Publication of WO2008135914A2 publication Critical patent/WO2008135914A2/en
Publication of WO2008135914A3 publication Critical patent/WO2008135914A3/en
Priority to US12/951,914 priority patent/US8120384B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM

Abstract

In a bridge adder circuit, a first (1,3) and a second (2,4) complementary pair of current mirrors is connected between the input terminals (1,2) and a positive (9) and a negative (10) supply voltage bus, respectively, to control a first (5,6) and a second (7,8) push-pull output stage. The outputs of the push-pull output stages are connected to the respective inputs (11,12) through first resistors (24,25) and to a common output node (26) through second resistors (27,28). As a result, a universal circuit element for a multivalued logic element, such as ternary logic or 5-valued logic is provided.
PCT/IB2008/051671 2007-05-04 2008-04-30 Multivalued logic circuit WO2008135914A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP08738033A EP2171847B8 (en) 2007-05-10 2008-04-30 Multivalued logic circuit
US12/598,669 US7859312B2 (en) 2007-05-10 2008-04-30 Multivalued logic circuit
AT08738033T ATE520203T1 (en) 2007-05-10 2008-04-30 MULTI-VALUE LOGIC CIRCUIT
US12/951,914 US8120384B2 (en) 2007-05-10 2010-11-22 Multivalued logic circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2007117392 2007-05-10
RU2007117392/09A RU2331105C1 (en) 2007-05-10 2007-05-10 Universal bridge inverting adder

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/598,669 A-371-Of-International US7859312B2 (en) 2007-05-10 2008-04-30 Multivalued logic circuit
US12/951,914 Continuation US8120384B2 (en) 2007-05-10 2010-11-22 Multivalued logic circuit

Publications (2)

Publication Number Publication Date
WO2008135914A2 WO2008135914A2 (en) 2008-11-13
WO2008135914A3 true WO2008135914A3 (en) 2008-12-31

Family

ID=39746504

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/IB2008/051671 WO2008135914A2 (en) 2007-05-04 2008-04-30 Multivalued logic circuit
PCT/RU2008/000292 WO2008140357A1 (en) 2007-05-10 2008-05-12 Multipurpose bridge inverting adder

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/RU2008/000292 WO2008140357A1 (en) 2007-05-10 2008-05-12 Multipurpose bridge inverting adder

Country Status (5)

Country Link
US (2) US7859312B2 (en)
EP (1) EP2171847B8 (en)
AT (1) ATE520203T1 (en)
RU (1) RU2331105C1 (en)
WO (2) WO2008135914A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2331105C1 (en) 2007-05-10 2008-08-10 Виктор Викторович Олексенко Universal bridge inverting adder
WO2012143016A1 (en) * 2011-04-18 2012-10-26 Abo Warda Magdi Al Saeed Ahmed Magdi's logic (ternary logic)
JP5738749B2 (en) * 2011-12-15 2015-06-24 ルネサスエレクトロニクス株式会社 PLL circuit
RU2546082C1 (en) * 2014-04-30 2015-04-10 Федеральное Государственное Бюджетное Образовательное Учреждение Высшего Профессионального Образования "Донской Государственный Технический Университет" (Дгту) k MODULO MULTIPLE-VALUED ADDER
WO2017160863A1 (en) 2016-03-15 2017-09-21 Louisiana Tech Research Corporation Method and apparatus for constructing multivalued microprocessor
US10646996B2 (en) * 2017-07-21 2020-05-12 Vicarious Fpc, Inc. Methods for establishing and utilizing sensorimotor programs
CN109857368B (en) * 2018-12-20 2022-07-26 上海大学 Multi-digit, grouping and reconfigurable multi-value electronic arithmetic device and method
RU2724802C1 (en) * 2019-12-30 2020-06-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Забайкальский государственный университет" (ФГБОУ ВО "ЗабГУ") Natural number adder

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4229803A (en) * 1978-06-02 1980-10-21 Texas Instruments Incorporated I2 L Full adder and ALU
US4814644A (en) * 1985-01-29 1989-03-21 K. Ushiku & Co. Basic circuitry particularly for construction of multivalued logic systems
RU2176850C1 (en) * 2000-10-20 2001-12-10 Олексенко Виктор Викторович Low-noise wide-band current amplifier
US20050093629A1 (en) * 2003-10-31 2005-05-05 Nec Electronics Corporation Differential amplifying circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855922A1 (en) * 1978-12-23 1980-07-10 Hoechst Ag METHOD FOR PRODUCING ZINC-FREE ALKALIPHOSPHATE SOLUTIONS
US4577160A (en) * 1983-01-03 1986-03-18 Robert H. Rines Method of and apparatus for low noise current amplification
JPS61153778A (en) * 1984-12-27 1986-07-12 Toshiba Corp Analog arithmetic circuit
RU2178235C1 (en) * 2000-09-29 2002-01-10 Олексенко Виктор Викторович Low-noise broad-band current amplifier
US7187208B2 (en) * 2005-01-19 2007-03-06 Phaselink Semiconductor Corporation Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer
US7579872B2 (en) * 2006-05-31 2009-08-25 Fujitsu Limited Low-voltage differential signal driver for high-speed digital transmission
RU2331105C1 (en) 2007-05-10 2008-08-10 Виктор Викторович Олексенко Universal bridge inverting adder
KR100912964B1 (en) * 2007-09-04 2009-08-20 주식회사 하이닉스반도체 Current mode logic - complementary metal oxide semiconductor converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4229803A (en) * 1978-06-02 1980-10-21 Texas Instruments Incorporated I2 L Full adder and ALU
US4814644A (en) * 1985-01-29 1989-03-21 K. Ushiku & Co. Basic circuitry particularly for construction of multivalued logic systems
RU2176850C1 (en) * 2000-10-20 2001-12-10 Олексенко Виктор Викторович Low-noise wide-band current amplifier
US20050093629A1 (en) * 2003-10-31 2005-05-05 Nec Electronics Corporation Differential amplifying circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CURRENT K W: "CURRENT-MODE CMOS QUATERNARY THRESHOLD LOGIC FULL ADDER CIRCUIT", INTERNATIONAL JOURNAL OF ELECTRONICS, TAYLOR AND FRANCIS.LTD. LONDON, GB, vol. 74, no. 4, 1 April 1993 (1993-04-01), pages 587 - 591, XP000365264, ISSN: 0020-7217 *

Also Published As

Publication number Publication date
ATE520203T1 (en) 2011-08-15
EP2171847A2 (en) 2010-04-07
WO2008135914A2 (en) 2008-11-13
RU2331105C1 (en) 2008-08-10
WO2008140357A1 (en) 2008-11-20
US7859312B2 (en) 2010-12-28
EP2171847B8 (en) 2012-02-08
US8120384B2 (en) 2012-02-21
EP2171847B1 (en) 2011-08-10
WO2008140357A8 (en) 2009-09-11
US20110121861A1 (en) 2011-05-26
US20100164596A1 (en) 2010-07-01

Similar Documents

Publication Publication Date Title
WO2008135914A3 (en) Multivalued logic circuit
KR100791934B1 (en) High amplitude output buffer circuit for high speed system
CN101083464B (en) Semiconductor integrated circuit including output circuit
JP2009525595A5 (en)
TW200632664A (en) An updating system for updating a firmware of a circuit module from an update module and related method
WO2007091211A3 (en) Circuit arrangement and method for detecting a power down situation of a voltage supply source
JP2017505898A5 (en)
JP2006042349A5 (en)
CN103098374A (en) Comparator and AD converter comprising the same
TW200629726A (en) A common-mode shifting circuit for CML buffers
ATE524873T1 (en) AMPLIFIER CIRCUIT
ATE524874T1 (en) CONVERTER WITH DIFFERENTIAL INPUTS CONNECTED IN PARALLEL
CN100530965C (en) High performance level shift circuit with low input voltage
DE102005054291A1 (en) Electrical protective circuit for e.g. three-level inverter, has fuse which is connected to one of three connecting lines, where one connecting line is separated into two lines that are coupled with remaining connecting lines, respectively
WO2009063527A3 (en) Logic gate with a reduced number of switches, especially for applications in integrated circuits
US10256818B2 (en) Level shifter
JP2016162216A (en) Reference voltage circuit
JP4616871B2 (en) Hysteresis comparator
JP2005202658A (en) Output circuit
JPH0440020A (en) D/a converter
CN106788432A (en) D/A converting circuit
CN103151766B (en) A kind of controllable quiescent current current limliting acceleration protection circuit
WO2008105157A1 (en) Amplifying circuit and associative memory
JP4814072B2 (en) Logic circuit
TW200509549A (en) Receiving apparatus and transmission apparatus utilizing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08738033

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 12598669

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2008738033

Country of ref document: EP