WO2007067070A1

WO2007067070A1 - A tuneable diffraction grating (tdg) optical chip comprising a fork like structural embodiment of electrodes

Info

Publication number: WO2007067070A1
Application number: PCT/NO2006/000465
Authority: WO
Inventors: Vladimir Kartashov; Gunnar Hedin; Arne Skauge Johannessen; Tore Svortdal; Erling Kolltveit; Richard Berglind
Original assignee: Polight As
Priority date: 2005-12-07
Filing date: 2006-12-06
Publication date: 2007-06-14
Also published as: NO20055795D0

Abstract

The present invention is related to Tunable Diffraction Grating (TDG) optical chips providing reduced or eliminated light scattering artifacts. According to the present invention, such artifacts can be reduced or eliminated by introducing a fork like structural embodiment of electrodes. According to another aspect of the present invention, a conducting material arranged in between said electrodes will also due to physical properties of said applied material eliminate contributions to scattering artifacts from charges and height differences between said electrodes and said modulating surface of said gel.

Description

A Tuneable Diffraction Grating (TDG) optical chip comprising a fork like structural embodiment of electrodes.

The present invention is generally related to Tuneable Diffraction Grating optical chips, and especially to Tuneable Diffraction Grating optical chips comprising a fork like structural embodiment of electrodes reducing scattering artefacts according to the independent claim 1.

An example of a typical Tuneable Diffraction Grating (TDG) optical chip is disclosed in US 6,897,995. This TDG chip is used in a telecom application, but as known to a person skilled in the art, the TDG chip design providing diffraction of light maybe used in a variety of applications, including, but not limited to, such applications as light valve applications and line scanning projection display systems. Figure 1 illustrates a TDG chip used in a telecom application, while figure 2 illustrates an example of a line scanning proj ection display system.

The interest in light modulators are generally increasing due to the need of enhanced optical communication solutions in telecom, but also due to increased demand of more reliable and better performing components, higher resolution in display applications (High Definition Television etc.), more generally stated - more versatile optical components and systems.

Such increased demand on the performance the TDG technology increases the demand on the optical characteristics of the component. One area of special importance is to reduce or avoid inaccuracies or errors in the light scattering process itself. Such errors are manifesting itself as artefacts in the output light from the optical component which implies that parameters such as light efficiency etc. are not optimal in the design of the component. More seriously is that such artefacts may result in unintended or unwanted scattering of light which may lead to errors in operation of the optical component. Therefore there is a need for Tuneable Diffraction Grating (TDG) optical chips that provide reduced scattering artefacts.

Different embodiments of the TDG chip itself can be imagined, both as exemplified by US 6,897,995 (detailed in Fig 3) and also with a gel or polymer material with acceptable conductivity that eliminates the need for an optically transparent electrode layer between the gel (or polymer) and the prism. A conductive layer or metal film on the surface of the flexible gel material on the side that turns away from the prism and electrically connected to the desired voltage will also eliminate the need for this electrode layer. The substrate in Fig 3 can be silicon or glass. In the latter case, the additional insulating layer is not necessarily needed.

The article "Elastomer-Based Diffractive Optical Modulator", by Uma S., et al., IEEE Journal of Selected Topics in Quantum Electronics, Vol. 10, No. 3, May/June 2004, page 435-439 disclose a device structure and measurements on a diffractive optical modulator fabricated using a elastomer layer. The device structure is fairly simple with an interdigitated bottom electrode, an elastomer layer, and a top electrode. Application of voltage to one of the bottom interdigitated electrodes causes and electrostrictive force, which in turn corrugates the elastomer layer. This method is used to create a configurable reflective phase grating that enables an analog control of the diffracted intensity.

US Patent No. 4,729,030 disclose an analog video frame store, resident in certain types of video displays that is used to obtain video signal noise reduction. A frame storage system has an array of semiconductor control storage units for receiving and storing frames of video information as a pattern of stored charge. A circuit is provided for applying sampled portions of the video signals to respective ones of the elemental storage units of the frame storage system. The circuit is operative to apply the sample portions of video signals to the respective semiconductor unit storage regions with a time constant for each particular storage unit that depends on the difference between the sample signal level being applied to the particular storage unit and a signal level stored at a particular storage unit. The stored charge is converted into a viewable image by using a deformable material whose shape is affected by the charge pattern and an optical subsystem for generating the viewable image as a function of the shape of the deformable material. The working principle for the TDG is the surface modulation of a gel or polymer film by electrical fields applied by electrodes attached to a substrate. The surface modulation needs to be carefully controlled in order to give the desired scattering effect on the incident optical signals. Undesired electrical field contributions may lead to undesired surface modulation patterns which in turn may cause different artefacts in the intended scattering of light. For example, stray light, higher optical insertion loss, reduced contrast ratio, increased black level, image ghosting, blur artefacts, and reduced dynamic range amongst others in the form of memory effects. These are undesired effects in the aforementioned applications such as optical communication and display systems and components.

Due to the finite height of physical electrodes, embodiments of substrate designs as proposed in US 6,897,995 will have height differences. Due to the physical properties of the design, the resulting electrical field experienced by the gel surface will depend on the distance between the gel surface and the substrate below. This will cause an undesired surface modulation of the gel, and a contribution to the modulation will be present even in the case of no signal voltage being applied to the electrodes as this is caused by the height difference between the electrodes and the area between the electrodes. Merely the presence of a bias voltage in the absence of applied signal voltage (Vl = V2) will cause this modulation. The consequence is a reduced efficiency (contrast ration and black level in display applications and reduced dynamic range in telecom applications, together with increased insertion loss which is undesired in both applications).

According to an aspect of the present invention, these undesired artifacts can be eliminated or sufficiently reduced by shaping all or parts of the undesired contributions into spatial orders that cause less harmful scattering of the incoming light.

According to an example of embodiment of the present invention, said spatial orders maybe achieved by a forked pattern of the electrodes provided on the insulating layer supporting the electrodes. Charges in the insulating layer shown in figure 3 or in the substrate itself in case of a substrate made from glass or another insulating material may disturb the desired electrical potential set up by the electrodes when charges are located in between adjacent electrodes. The low conductivity of the insulating layer slows down the draining and re-distribution process of these charges whenever the signal voltages of the electrodes are changed or modified, thereby creating a kind of memory effect in the potential distribution and thereby a superposition of unintended and intended patterns on the gel surface. These charges thereby lead to undesired artefacts in the resulting scattering of incoming light: Examples are, stray light, higher optical insertion loss, reduced contrast ratio, increased black level, image ghosting, blur artefacts, and reduced dynamic range amongst others in the form of memory effects. According to an aspect of the present invention, these undesired artefacts may be reduced to an acceptable level or even removed by providing a layer of appropriate conductivity for a sufficiently fast draining and/or re-distribution of charges in between the electrodes.

According to an example of embodiment of the present invention, a lower limit for the conductivity can be defined by the slowest time response or maximum memory effect that can be tolerated in a specific application. The upper limit for the conductivity can be decided by the maximum current allowed to flow between electrodes from considerations of the desired maximum current or heat dissipation in the TDG chip.

According to yet another aspect of the present invention, undesired artifacts due to finite height differences on the substrate may be strongly reduced or even removed by arranging the surface of the substrate facing the gel planar or sufficiently planar, wherein the combination with the forked electrode design will reduce the artifacts to the extent found necessary for a specific application.

According to an example of embodiment of the present invention, the space in between the electrodes is filled with a dielectric material.

According to yet another example of embodiment of the present invention, a material with an appropriate conductivity as discussed above is used to fill said spaces between electrodes in order to combine the effects of the appropriate conductive layer with a planar substrate surface.

According to a preferred embodiment of the present invention, a TDG chip is manufactured with a fork like structural embodiment of electrodes providing the grating effect of the gel, while spaces between electrodes are filled with a material comprising a conductivity providing an appropriate time-constant for drainage of charges in a insulating layer supporting the fork like electrodes, and the filled material is flush with surfaces of said fork like electrodes.

Fig. 1 illustrates an example of embodiment of the Tuneable Diffraction Grating (TDG) optical chip as known from prior art (US 6,897,995).

Fig. 2 illustrates an example of embodiment of a projector system comprising a

Tuneable Diffraction Grating (TDG) optical chip. Fig. 3 depicts a cross sectional view an example of embodiment of a light modulator as exemplified in US 6,897,995, wherein the Electrode direction is perpendicular to the drawing plane, Vl is unequal to V2 and Vbias is unequal to Vsubstrate.

Fig. 4 illustrates a cross sectional view of an example of embodiment of the present invention compensating the effect of finite electrode height, Vl = V2, Vbias unequal to Vsubstrate. Fig. 5 illustrates a top view of electrode patterns according to the present invention.

Fig. 6 illustrates an example of difference in gel surface tension when using a fork like structural embodiment of electrodes according to the present invention, upper drawing without fork like electrodes, bottom drawing with fork like electrodes.

Fig. 7 illustrates an example of stable charge distribution in the insulating layer, when V2>V1.

Fig. 8 illustrates a simplified distributed RC model for a section of the substrate between one pair of electrodes with voltages Vl and V2 applied by driving electronics (not shown).

Fig. 9 illustrates examples of voltage potential distributions in the electrode plane with an acceptable conductivity: i) after a long time with stable values of all voltages, ii) instantaneously after Vl and V2 have changed, and iii) after a long time with stable voltages when the charge distribution is stable.

Fig. 10 illustrates a cross sectional view of an example of a fork electrode embodiment combined with conductive layers in order to reduce the transportation time for surface charges in between the electrodes, according to the present invention.

Fig. 11 illustrates a cross sectional view of an example of a fork electrode embodiment combined with conductive layers in order to reduce the transportation time for surface charges in between the electrodes, according to the present invention. Fig. 12 illustrates a cross sectional view of an example of a fork electrode embodiment combined with conductive layers in order to reduce the transportation time for surface charges in between the electrodes, according to the present invention. Fig. 13 illustrates a cross sectional view of an example of embodiment according to the present invention, comprising: planarized substrate with conductive layer or film between electrodes, not to scale.

Fig. 14 illustrates a cross sectional view of an example of embodiment according to the present invention, comprising planarization with a dielectric material between electrodes, not to scale.

The TDG design as disclosed in US 6,897,995, has finite height differences between the electrodes and the area in between the electrodes as indicated in figure 4, alternatively with a substrate made from an insulating material which would eliminate the need for an insulating layer beneath the electrodes. For illustrative purposes, the situation for a gel surface intended to be flat can be regarded where the basic relation between a potential difference ΔV = Vbias - Vsubstrate and the corresponding electrical field strength E governed by the distance h over which the difference ΔV is applied, is given by E = ΔV /h. The field strength E will vary due to the substrate height in figure 4 as Emax = ΔV/H2 and Emin = ΔV/H1 assuming that the gel surface is at the same potential as Vbias, giving a maximum fluctuation of ΔE - Emax - Emin = (H1-H2) times ΔV/(H1 times H2). The resulting equiopotential surface will define a finite surface modulation even in the absence of signal voltages.

This causes an unintended scattering of the incoming light and thereby a reduced degree of control over the manipulation of the incoming light. This reduced control will also be present when Vl is unequal to V2 as the total surface modulation will be a

superposition of an intended and an unintended pattern

According to an aspect of the present invention, replacing a prior art TDG electrode pattern as depicted on the left hand side of figure 5 with a fork-like structural embodiment according to the present invention comprising at least two teeth, as depicted on the right hand side of figure 5, will shape into higher spatial order all or a significant part of the unwanted contributions to the local electrical field experienced by the gel/polymer. The resulting undesired surface modulation is smaller due to the surface tension of the gel/polymer material which becomes more significant for higher spatial frequencies as for all materials of gel/polymer types.

The advantages with a fork design as described above are demonstrated in Figure 6, where for illustrative purposes Vl = V2: The upper part illustrates the regular electrode design of prior art where each electrode pulls on a virtual slab of the gel material with a certain width and thereby mass. The lower part of the figure illustrates the situation for an example of embodiment comprising a two-tooth fork embodiment, where each electrode is narrower than in the prior art design, and therefore pulls on a virtual material slab of a narrower width and thereby smaller volume. The reduced surface modulation amplitude in the fork design is due to the fact that the height of narrower slabs of a compressible material will be less modulated than wider slabs, translating into a higher surface tension. The insulating layer below the electrodes in case of a silicon substrate (or the glass substrate itself in case of a glass substrate) will be exposed to the electrical fields set up by the Vbias, Vsubstrate, and Vl and V2 imposed on the electrodes, ref. figure3.

According to the physical properties of this arrangement, the insulating layer will become charged due to material defects and a finite conductivity.

Schematically illustrated, the charge distribution will build up as indicated in figure 7. The electrical equivalent between adjacent electrodes with voltages Vl and V2, respectively, imposed by the drive electronics can be modeled as a distributed RC circuit as indicated in figure 8. The charge stored in the distributed capacity of the insulating layer needs to be transported away by the conductivity of the layer, represented by the distributed resistors in figure 8. However, if the conductivity of the insulating layer is too low, the resulting time constant for the charge transportation will exceed the time constant required for the end application. This will cause the surface of the gel to experience undesired electrical stray fields from the undesired charge distribution in the insulating layer, causing increased insertion loss, reduced dynamic range, and reduced contrast ratio due to this memory effect caused by the charge distribution in the insulating layer.

According to an aspect of the present invention, a modification of the conductivity of the insulating layer in order to achieve an appropriate time constant according to the equivalent RC circuit depicted in figure 8 is possible by applying a material in contact with said charges in between said electrodes comprising said appropriate conductivity. This modification may also modify the distributed capacitance in figure 8. However, the overall goal is to establish a time constant that is acceptable for the end application.

The steady state of the model in Figure 8 allows analytic evaluation of the steady- state currents flowing through the surface layer between electrodes: The current I flowing between one pair of electrodes is given by I = ΔV/R = (Vl-V2)/R where the resistance R between a pair of adjacent electrodes is given by R = s/(σ x A) where s is the spacing between electrodes, σ is the conductivity of the suitably conductive layer, and A is the cross section area of the aforementioned layer. This allows for seed values of conductivity to be manufactured for characterization of the actual voltages and currents, thereby allowing for trimming of the conductivity based on experimental observations. This is a well-known technique from the manufacturing of integrated electronics where post-manufacturing trimming or reduction of resistor values is common. An example is if the acceptable steady-state current flow per pair of electrodes is 0.01 mA. ΔV = 10V, A = IO x 1000 square micrometer, s = 30 micrometer: The desired conductivity σ of the suitably conductive layer should be about 3x10^"3 l/(ohm x m).

A similar calculation can be made based on maximum electrical power consumption Pmax induced by the steady-state current flow I between a single pair of electrodes when ΔV is the relative potential difference between the electrodes and the remaining parameters as in the preceding paragraph: Pmax = ΔV x I. If P = 0.01 mW, the desired conductivity σ of the suitably conductive layer should be about 3x10^"4 l/(ohm x m). An example of voltage potential distribution in the electrode plane is depicted in figure 9 for a sequence of signal voltages Vl and V2. The upper section in figure 9 illustrates the situation after a long time of stable voltage signals, the middle section the situation immediately after Vl and V2 have changed values, and the lower section the situation after a sufficiently long time for re-distribution of charges according to the new values of Vl and V2. The unintended surface modulation causing the optical artifacts appear in the phase represented by the middle phase which needs to be made as short in time as needed for the specific end application by tuning the conductivity of the conductive layer between the electrodes. Example of embodiments can be found in figures 10, 11, 12, 13 and 14.

According to an aspect of the present invention, a sufficiently planar surface of the substrate as decided by experimental observations by filling the space between the electrodes with an insulator or a material with conductivity as discussed above will result in reduction of the effect of the different heights of the TDG chip electrode assembly, as described above. Examples of embodiments according to the present invention are depicted in figure 13 and 14. The resulting surface can be planar or as near to being planar as necessary for the end application and for the combined effect of fork electrodes and a planar substrate.

As can be understood by a person skilled in the art, all aspects of the present invention may be combined in examples of embodiments. All such combinations and/or sub combinations are inside the scope of the present invention.

Claims

C l a i m s :

1.

Tunable Diffraction Grating (TDG) optical chip comprising an insulating layer or a 5 substrate itself with insulating properties, a gel or membrane or elastomer, wherein the TDG chip comprises: a fork like structural embodiment of electrodes arranged on top of the insulating layer providing an electric field, when voltages are applied on the electrodes, providing a₀ surface modulation of the gel or membrane or elastomer scattering incident light on the modulated surface, wherein a conducting layer is in contact with adjacent electrodes of the insulating layer, wherein the conducting layer comprises a material with a conductivity defining a times constant for drainage of surface charges between the adjacent electrodes.

2.

TDG chip according to claim 1, wherein said defined time constant is calculated from an equivalent distributed RC model circuit of adjacent electrodes supported on saido insulating layer.

3.

TDG chip according to claim 2, wherein said calculation comprises establishing a lower and upper limit of said time constant by using the slowest response time of said TDG5 chip which an application of said TDG chip can tolerate as said lower limit, while

defining an upper limit of said time constant by considering a maximum allowable current that may flow between adjacent electrodes.

4.

0 TDG chip according to claim 1, further comprising post-manufacturing trimming of said conductivity.

5.

TDG chip according to claim 1, wherein said conducting layer is in between said5 adjacent electrodes of said insulating layer.

6.

TDG chip according to claim 1, wherein said conducting layer is on top and interconnecting said adjacent electrodes of said insulating layer. s

7.

TDG chip according to claim 1, wherein said conducting layer is under and interconnecting said adjacent electrodes of said insulating layer.

8.

o TDG chip according to claim 1, wherein said conducting layer is arranged such that a top surface of said conducting layer is flush with top surfaces of said fork like electrodes.

9.

s TDG chip according to claim 1, wherein said conducting layer comprise a dielectric material.

10.

TDG chip according to claim 1, wherein a dielectric material is filled in between said0 adjacent electrodes of said insulating layer flush with top surfaces of said electrodes, and wherein said conducting material is arranged as a layer on top of said dielectric material and said top surfaces of said electrodes. 5