CN201548484U - Universal multi-path digital image simulating source - Google Patents

Universal multi-path digital image simulating source Download PDF

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Publication number
CN201548484U
CN201548484U CN2009200351125U CN200920035112U CN201548484U CN 201548484 U CN201548484 U CN 201548484U CN 2009200351125 U CN2009200351125 U CN 2009200351125U CN 200920035112 U CN200920035112 U CN 200920035112U CN 201548484 U CN201548484 U CN 201548484U
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China
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fpga
output
data
bus
usb
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Expired - Fee Related
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CN2009200351125U
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陈静
刘青
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XI'AN REALECT ELECTRONICS DEVELOPMENT Co Ltd
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XI'AN REALECT ELECTRONICS DEVELOPMENT Co Ltd
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Abstract

The utility model discloses a universal multi-path digital image simulating source which comprises a USB/network interface card and a plurality of function sub-cards. The USB/network interface card which comprises a core processor is respectively connected with the function sub-cards by backplane buses; the core processor is respectively connected with a switch, a 12C bus, an FPGA and a drive; the FPGA is connected with a USB/network receiving/transmitting unit, and the drive is connected with the backplane buses. Each function sub-card is formed by the sequential connection of a memory, an FPGA controller and an LVDS output drive, and can finish transmitting image simulating sources of corresponding lines at the same time. In the utility model, the FPGA is adopted as the controller to process images, a programmable clock is combined with an internal PLL of the FPGA so as to serve as a clock source, the output images can be controlled in real time by an LVDS interface; 8 paths of image data can be output at the same time, and each path of data can respectively control such information as initial lines, end lines and the like of auxiliary data, output data formats, output data clocks and the output images.

Description

General Multiplex digital picture dummy source
Technical field
The utility model belongs to the electron and information technology field, is specifically related to a kind of General Multiplex digital picture dummy source.
Background technology
In fields such as chemicals detection, medical imaging, fruit detection, avionics measurements, camera just develops towards the aspect of multichannel, many speed, multiple data format.Such as the multispectral camera of often using, area array cameras, line-scan digital camera etc.Each camera all has its unique characteristic, and the view data of multispectral camera is made up of red spectral coverage, green spectral coverage, blue spectral coverage, near infrared spectral coverage four circuit-switched data; The linear array data then have only a circuit-switched data.The camera of two-forty also produces endlessly, and from 10MHz~40MHz, and along with the continuous development of electronic information technology, its frequency range is about to surpass 100MHz such as the pixel clock ranges of CCD camera.
As the subsequent processing device that receives camera data, that stands in the breach will be consistent with the camera output interface exactly, if equipment must be through coming into operation after the strict test. in test process each time, subsequent processing device is all docked with the CCD camera system of its front end, will certainly cause the waste of time and material resources. in order to guarantee carrying out smoothly of Flame Image Process follow-up equipment (as image compression apparatus) research and development and test.
Image simulation source performance in the past is more single, can only send image with fixing pixel clock and specific data layout, and the image auxiliary data of camera data leading part also trouble when changing.This also needs when just causing exploitation camera subsequent processing device to develop corresponding image simulation source as its checkout equipment according to different camera requirements.And the dummy source implementation procedure has a lot of similarities, and each design once more research and development all can constitute the work of repetition, loses time, energy, material resources.
Summary of the invention
The purpose of this utility model provides a kind of General Multiplex digital picture dummy source, it is more single to solve the transmission speed that exists in the prior art, the transmission form is single, needs to develop the problem of corresponding image simulation source as its checkout equipment according to different camera requirements.
The technical scheme that the utility model adopted is, a kind of General Multiplex digital picture dummy source, comprise USB network interface unit and several function subcard, USB interconnect by core bus between network interface unit and each function subcard, described USB network interface unit comprise a core processor, core processor is connected respectively with switch, 12C bus, FPGA, driving, and FPGA is connected with USB/ network Transmit-Receive Unit, drives to be connected with core bus; Described each function subcard can be finished the transmission in respective lines image simulation source simultaneously, and each function subcard is driven successively and connected by storer, FPGA controller, LVDS output.
General Multiplex digital picture dummy source of the present utility model, its feature also is:
Described storer comprises FLASH primary storage chip and SDRAM auxiliary storage chip composition.
In the described function subcard, the FPGA controller is connected respectively with bus buffer driver, external clock, and the bus buffer driver is externally exported by backboard universal serial bus and CCD simulation output board.
The beneficial effect of the utility model device is, the data that the output of image simulation source can be set easily send form, sequential, artificial control chart is as the view data in the dummy source, output speed obviously improves, thereby reach general technical requirement, output pixel clock can change according to demand and do not influence the image output data in 1MHz~100MHz scope, and is simple in structure.
Description of drawings
Fig. 1 is the realization block diagram of the utility model device embodiment;
Fig. 2 is that the function subcard of the utility model device embodiment is realized block diagram;
Fig. 3 is the function subcard specific implementation functional diagram of the utility model device embodiment;
Fig. 4 is the function subcard data output timing diagram of the utility model device embodiment.
Among the figure, 1.USB network interface unit, 2. function subcard, 3. core processor, 4. switch, 5.12C bus, 6.FPGA, 7.USB/ network Transmit-Receive Unit, 8. drive 9. storer, 10.FPGA controller, 11.LVDS output drives, 12. core buss, 13. computing machines, 14.FLASH the primary storage chip, 15.SDRAM auxiliary storage chip, 16. bus buffer drivers, 17. external clock, 18. backboard universal serial bus, 19.CCD simulates output board.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is elaborated.
Image simulation of the present utility model source is connected with computing machine (host computer), relates to the storage, splicing, transfer of linear array, multispectral, facet array camera view data and export technique synchronously.
As Fig. 1, the structure of the utility model device is, comprise USB network interface unit 1 and function subcard 2, USB interconnect by core bus 12 between network interface unit 1 and each the function subcard 2, reach the purpose of high-speed transfer and control.Described USB network interface unit 1 include core processor 3, core processor 3 is connected respectively with switch 4,12C bus 5, FPGA6, driving 8, FPGA6 is connected with USB/ network Transmit-Receive Unit 7, drives 8 and is connected with core bus 12; Described function subcard 2 includes several, can finish the transmission in respective lines image simulation source simultaneously, and each function subcard 2 drives 11 by storer 9, FPGA controller 10, LVDS output and constitutes.Function subcard 2 is according to configuration, can one card for multiple uses, finish the output function of camera datas such as multispectral, face battle array, linear array, high score CCD flexibly.Host computer computing machine 13 utilizes VC to write user interface, can with view data by USB network interface unit 1 be loaded on each function subcard 2.In addition, the output format configuration information of image also is loaded on each function subcard 2 by this interface.
Therefore be illustrated in figure 2 as the inner structure of the utility model embodiment function subcard, include 8 same function subcards, can finish the transmission in 8 road image simulation sources simultaneously, because the structure unanimity of each function subcard can increase and decrease according to actual needs.Each function subcard drives 11 by storer 9 (comprise a FLASH primary storage chip 14 form with a SDRAM auxiliary storage chip 15), FPGA controller 10, LVDS output and is connected successively, FPGA controller 10 is connected respectively with bus buffer driver 16, external clock 17, external clock 17 comprises that same external clock A and external clock B form, and bus buffer driver 16 is externally exported by backboard universal serial bus 18 and CCD simulation output board 19.
As Fig. 3, function subcard 2 in the inner concrete functional module of FPGA is, comprises that respectively FLASH control interface, data deposit and functions such as buffer memory, sequential control and generation, data fusion.At first, the time schedule controller among the FPGA is exported the control clock, is got phase clock, data fusion clock according to the value in the configuration register array; The FLASH storer is got I/O view data under the control of phase clock at time schedule controller then, SDRAM is as the buffer memory of centre, output or reception FLASH view data, enter the data fusion unit by the auxiliary data in view data and the auxiliary data register, according in the configuration register be configured to and the output of the clock of time schedule controller finally meets the data that certain output requires.Time schedule controller has played conclusive effect in this process.It adopts the streamline form to carry out work, coordinates the time relationship of several respects such as FLASH read or write speed, SDRAM read or write speed, data fusion speed.The function subcard links to each other with the USB2.0 interface board by the core bus interface.Be divided into two kinds of working methods: default working method and programing work mode.Default working method: power on and stable operation stage in system, each function subcard is according to the datamation that is stored in advance on the FLASH, read image information among separately the FLASH respectively by the FPGA on each function subcard, convert them to data by configuration parameter with certain output format, be carried on the lvds driver, export through the SCSI68 interface.At first, FPGA judges the FLASH control authority, if FPGA is a master controller, then FPGA reads the controlled variable of depositing thereon from the some fixing zone of FLSAH, according to the pattern of parameter regulation, write programmable clock control, require output data according to certain clock period and sequential; If peripheral control unit is master controller, then FPGA enters waiting status, discharges control authority to FLASH up to peripheral control unit, and FPGA obtains till the control to FLASH again.
The programing work mode: the function subcard suspends output, receive the parameter or the data of host computer or the local configuration of equipment by the USB2.0 interface card, by addressing with the information stores that receives in function corresponding subcard FLASH, at this moment, function subcard controller outside obtains the control authority to FLASH.Work as end of transmission, the function subcard is according to the information work that newly receives, and duty goes back to default duty from the programing work state, and peripheral control unit discharges the authority to FLASH.
As Fig. 4, the data output unit of the utility model device embodiment comprises 4 road signals, i.e. pixel clock signal, synchronous (gate) signal of row, image auxiliary data and view data.The pixel clock signal is operated in 1MHz~100MHz scope according to the actual needs that require, and image auxiliary data and view data can be combined into various export structures according to the output configuration parameter.
In image simulation source in the past, because the basis of adopting fixing crystal oscillator to take place as sequential, thereby define its output can only be in fixing several Frequency point work, in the utility model, adopted external clock (comprising the clock that programmable clock combines with the PLL of the FPGA inside) way of output, by sending the pixel clock that different clock programming Control parameters produces 1MHz~100MHz.
Each image of camera output data bit wide is all inconsistent, and that have is 5bit, and that have is 1bit.In order to adapt to different types of view data output, in the FPGA software design, designed the streamline decoding process, once from storage chip, take out the 32bit data, export according to final output figure place.
In addition, image simulation of the prior art source output data frequency limited is the readout time of memory device, adopted SDRAM to cooperate FLASH to come images in the utility model, the position of adopting SDRAM directly to describe in according to configuration parameter at the device power-on initial stage, from the Flash storage chip, read view data, in ensuing data output procedure view data directly by SDRAM output, thereby reduced the limited field of output frequency.
The transmission speed of data of the prior art is more single, and speed≤40Mhz, and this is mainly by the decision of the speed of storer, and the utility model is used SDRAM dynamic call view data mode instead and sent data, and then output speed can reach 100MHz; The transmission form of data of the prior art is single, a kind of dummy source can only be finished the function of a camera, and the utility model is used principal and subordinate's control model instead, can dispose the output type of dummy source dynamically according to reality by upper computer software, thereby reaches general technical requirement.

Claims (3)

1. General Multiplex digital picture dummy source is characterized in that: comprises USB network interface unit (1) and several function subcard (2), interconnects by core bus (12) between USB network interface unit (1) and each function subcard (2),
Described USB network interface unit (1) comprise a core processor (3), core processor (3) is connected respectively with switch (4), 12C bus (5), FPGA (6), driving (8), FPGA (6) is connected with USB/ network Transmit-Receive Unit (7), drives (8) and is connected with core bus (12);
Described each function subcard (2) can be finished the transmission in respective lines image simulation source simultaneously, and each function subcard (2) drives (11) by storer (9), FPGA controller (10), LVDS output and connects successively.
2. General Multiplex digital picture dummy source according to claim 1 is characterized in that: described storer (9) comprises FLASH primary storage chip (14) and SDRAM auxiliary storage chip (15) composition.
3. General Multiplex digital picture dummy source according to claim 1, it is characterized in that: in the described function subcard (2), FPGA controller (10) is connected respectively with bus buffer driver (16), external clock (17), and bus buffer driver (16) is by backboard universal serial bus (18) and externally output of CCD simulation output board (19).
CN2009200351125U 2009-10-20 2009-10-20 Universal multi-path digital image simulating source Expired - Fee Related CN201548484U (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102186011A (en) * 2011-05-13 2011-09-14 合肥埃科光电科技有限公司 Digital high-definition camera based on full hardware
CN102331975A (en) * 2011-09-06 2012-01-25 中国科学院长春光学精密机械与物理研究所 Method for storing multi-path high-speed short-blanking interval linear array CCD (charge-coupled device) image data
CN105163108A (en) * 2015-08-03 2015-12-16 青岛市光电工程技术研究院 Image data dummy source
CN106885956A (en) * 2016-12-28 2017-06-23 中国科学院长春光学精密机械与物理研究所 Aircraft pod test simulation source device
CN110868559A (en) * 2019-11-26 2020-03-06 中国电子科技集团公司第五十四研究所 Camera Link image signal generating device and method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102186011A (en) * 2011-05-13 2011-09-14 合肥埃科光电科技有限公司 Digital high-definition camera based on full hardware
CN102331975A (en) * 2011-09-06 2012-01-25 中国科学院长春光学精密机械与物理研究所 Method for storing multi-path high-speed short-blanking interval linear array CCD (charge-coupled device) image data
CN102331975B (en) * 2011-09-06 2013-11-27 中国科学院长春光学精密机械与物理研究所 Method for storing multi-path high-speed short-blanking interval linear array CCD (charge-coupled device) image data
CN105163108A (en) * 2015-08-03 2015-12-16 青岛市光电工程技术研究院 Image data dummy source
CN106885956A (en) * 2016-12-28 2017-06-23 中国科学院长春光学精密机械与物理研究所 Aircraft pod test simulation source device
CN110868559A (en) * 2019-11-26 2020-03-06 中国电子科技集团公司第五十四研究所 Camera Link image signal generating device and method

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C14 Grant of patent or utility model
GR01 Patent grant
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of utility model: Universal multi-path digital image simulating source

Effective date of registration: 20140808

Granted publication date: 20100811

Pledgee: Xi'an Taixin financing Company limited by guarantee

Pledgor: Xi'an Realect Electronics Development Co., Ltd.

Registration number: 2014610000015

PLDC Enforcement, change and cancellation of contracts on pledge of patent right or utility model
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Granted publication date: 20100811

Termination date: 20151020

EXPY Termination of patent right or utility model
PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20161230

Granted publication date: 20100811

Pledgee: Xi'an Taixin financing Company limited by guarantee

Pledgor: Xi'an Realect Electronics Development Co., Ltd.

Registration number: 2014610000015

PLDC Enforcement, change and cancellation of contracts on pledge of patent right or utility model