CN103929209A - High-performance combined RS processor based on FPGA - Google Patents
High-performance combined RS processor based on FPGA Download PDFInfo
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- CN103929209A CN103929209A CN201410140098.0A CN201410140098A CN103929209A CN 103929209 A CN103929209 A CN 103929209A CN 201410140098 A CN201410140098 A CN 201410140098A CN 103929209 A CN103929209 A CN 103929209A
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Abstract
The invention discloses a high-performance combined RS processor based on an FPGA. The main problems that in the prior art, transportability is poor, calculation speed is low, and burst error correction is weak are solved. The high-performance combined RS processor based on the FPGA comprises a transmitting end buffering module, a control module, an RS code decoding module, an interleaving module, a receiving end buffering module, a de-interleave module and an RS code coding module. A code length control signal is added into the transmitting end buffering module, and RS coding is performed on a message block for interleaving, and then the message block is sent to a channel; a code length control signal and a correction factor are respectively added into the receiving end buffering module, a received code block is sent to the de-interleave module for de-interleave, single clock rising edge and falling edge double control is adopted for the RS decoding module, and a chien search sub-module and a Forney algorithm sub-module work at the same time. Transportability of an RS coding and decoding device is improved, calculation speed of the RS coding and decoding device is increased, the occupation rate of hardware is effectively reduced, the capacity for burst error correcting is very high, and the RD processor can be used for wireless communication.
Description
Technical field
The invention belongs to communication technical field, further relate to the continuous Read-Solomon RS CODEC based on on-site programmable gate array FPGA in channel coding technology field, can be widely applicable for radio communication, and in Digital Subscriber Line system.
Background technology
RS code is the abbreviation of Read-Solomon (Reed-Solomon) code, belongs to forward error correction FEC mode.Being attributable to BCH code, is the BCH code of non-2 systems.Certainly be also cyclic code, linear block codes, it is particularly suitable for entangling error burst.Be to improve the reliability of transmission by increasing redundant symbol by the object of RS code, obviously the rate of information throughput has declined.In information source coding, be to remove as far as possible some useless information, to improve the rate of information throughput.So say from the side, chnnel coding makes the reliability of transmission become relative contradictory entity with the rate of information throughput.
RS code is widely used in various commercial uses, is the use on CD, DVD and Blu-ray Disc the most significantly; In transfer of data, it is also used to Digital Subscriber Line and worldwide interoperability for microwave access (WiMAX); Also flashing its figure of digital video broadcasting in broadcast system (DVB) and United States of america digital television national standard (ATSC); In computer science, it is the important member of layer 6 standard disk array (RAID).
In the RS code decode procedure based on FPGA, due to the restriction of the solving complexity of key equation in interpretation method, adopt repeatedly the method for iteration to process, thereby limit decoding speed, so the practical application of a RS processor, depends in the improvement of key equation in interpretation method to a great extent.Wang Feng (RS decoder algorithms research and implementation, University Of Suzhou's papers written by postgraduates, 2010) provided a kind of decoder based on iBM algorithm and realized, its processing speed on FPGA is not high, is only 94.54Mbits/s at the XC3S100E of Xilinx company working frequency of chip.
Although RS code is very ripe in the coding and decoding technical research based on FPGA, but the RS coder of existing FPGA is all only to input fixing code length, owing to needing to input the code length of different length under different wireless communications environments, therefore make RS coder under multiple communication environment, to move, cause the portability of RS coder not good.
Secondly in general radio communication, there is burst error, use separately RS CODEC can not correct well burst error.For example, the RS code processor that patent CN102122964A proposes, although have higher throughput, does not use interleaving technology to process burst error problem.
Summary of the invention
The object of the invention is to for above-mentioned existing technological deficiency, propose a kind of combination of the high-performance based on FPGA RS processor, to improve clock resource utilization and the throughput of processor, and make it have portability, and can correct in time burst error.
For achieving the above object, combination RS processor of the present invention, comprise: transmitting terminal buffer module 1, control module 2, RS code coding module 3, rx-side buffering module 4, RS code decoding module 5, transmitting terminal buffer module 1 is connected with RS code coding module 3, it is characterized in that:
The output of RS code coding module 3 is connected with interleaving block 6, for code character after encoding is carried out to interleaving treatment, and is sent to channel;
Between rx-side buffering module 4 and RS decoding module 5, be connected with de-interleaving block 7, for to decoding through deinterleaver code character after treatment, export to again RS decoding module 5 thereby recover coded message;
Transmitting terminal buffer module (1), is provided with two and receives signal end, is respectively used to receive data message k and the code length control signal ctrl of data/address bus;
Rx-side buffering module (4), is provided with two and receives signal end, is respectively used to receive the data message { R' of data/address bus
1, R'
2..., R'
ctrl+16and code length control signal ctrl-r, wherein ctrl-r=ctrl+16;
RS decoding module 5, it comprises:
Syndrome calculating sub module 51, for to receiving code character { R
1, R
2..., R
ctrl+16carry out interative computation, and under the rising edge control of clock clk, computing obtains 16 associated polynomial coefficient { S
1, S
2..., S
16, and by multinomial coefficient { S
1, S
2..., S
16be sent in RiBM algorithm submodule;
RiBM algorithm submodule 52, the associated polynomial coefficient { S according to RiBM algorithm to input
1, S
2..., S
16carry out interative computation, and under the trailing edge control of clock clk, obtain respectively error location polynomial { Λ
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8, and by error location polynomial { Λ
0, Λ
1..., Λ
8output to money searching algorithm submodule 53 and Fa Ni algorithm submodule 54, by improper value multinomial { Ω
0, Ω
1..., Ω
8output to method Buddhist nun algorithm submodule 54;
Money searching algorithm submodule 53, for the error location polynomial { Λ to input
0, Λ
1..., Λ
8carry out interative computation, and solve errors present under the rising edge control of clock clk
Method Buddhist nun's algorithm submodule 54, for the error location polynomial { Λ to input
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8carry out interative computation, and solve improper value under the rising edge control of clock clk
FIFO submodule 55, for by input code character { R
1, R
2..., R
ctrl+16store into sequentially in the cell fifo of fpga chip, obtaining errors present
and improper value
after, according to error situation output code character { R
1, R
2..., R
ctrl+16in error correcting circuit, correct;
Described syndrome calculating sub module 51, money searching algorithm submodule 53 and Fa Ni algorithm submodule 54, it is equipped with modifying factor { α
0, α
j, α
2*j..., α
16*j, for the requirement to code length according to reception data/address bus, these three errors that module produces in iterative process of adaptive correction, to adapt to different code lengths;
Described money searching algorithm submodule 53 is worked with method Buddhist nun algorithm submodule 54 simultaneously, to reduce hardware resource occupancy and to realize high-speed cruising.
The present invention compared with prior art, has following beneficial effect:
1. the present invention is owing to adding code length control signal ctrl in transmitting terminal buffer module 1, and added modifying factor in RS decoding module, makes RS processor adapt to the requirements of different input code lengths, greatly improved the portability of RS processor.
The present invention due in RS processor cascade interleaving block 6 and de-interleaving block 7, make this processor there is very strong burst error correcting capability.
3. the present invention, owing to making money searching algorithm submodule 53 and method Buddhist nun algorithm submodule 54 work in RS decoding module simultaneously, greatly reduces hardware resource occupancy and has improved clock utilization.
4. the present invention is owing to having used the method for single clock rising edge trailing edge dual control system in RS decoding module, greatly improve the operating frequency of RS processor, as the XC6VCX75T with Xilinx company carries out comprehensive simulating and static timing analysis, wherein coded portion maximum operating frequency is 374Mbit/s, decoding part maximum operating frequency is 301Mbit/s, and its data throughout is about 2.48Gbit/s.Its hardware resource occupancy is very low in addition, as shown in the following chart:
Brief description of the drawings:
Fig. 1 is high speed combination RS coder block diagram of the present invention;
Fig. 2 is that the RS coding module in the present invention is realized schematic diagram;
Fig. 3 is the interleaving block circuit diagram in the present invention;
Fig. 4 is the de-interleaving block circuit diagram in the present invention;
Fig. 5 is the RS decoding module structured flowchart in the present invention;
Fig. 6 is the syndrome calculating sub module circuit diagram in the present invention;
Fig. 7 is the money searching algorithm submodular circuits figure in the present invention;
Fig. 8 is the method Buddhist nun's algorithm submodular circuits figure in the present invention;
Fig. 9 is that the RS decoding module clock in the present invention takies schematic diagram;
Figure 10 is the RS encoder sequential emulation schematic diagram in the present invention;
Figure 11 is the RS decoder sequential emulation schematic diagram in the present invention;
Specific embodiments:
Be easy to understand understanding in order to make technological means of the present invention, creation characteristic and to reach object, further set forth the present invention in conjunction with instantiation once.
With reference to Fig. 1, RS coder of the present invention, it comprises: transmitting terminal buffer module 1, control module 2, RS code coding module 3, interleaving block 6, rx-side buffering module 4, de-interleaving block 7, RS code decoding module 5.This transmitting terminal buffer module 1 is connected with RS code coding module 3, and RS code coder 3 is connected with interleaving block 6; This rx-side buffering module 4 is connected with de-interleaving block 7, and de-interleaving block 7 is connected with RS code decoding module 5; This control module 2 is connected with transmitting terminal buffer module 1, RS code coding module 3, interleaving block 6, rx-side buffering module 4, de-interleaving block 7, RS code decoding module 5 respectively.Wherein:
Described transmitting terminal buffer module 1, is made up of a random access memory ram 5, and the front end of this random access memory ram 5 is provided with two and receives signal end, is respectively used to receive data message k and the code length control signal ctrl of data/address bus; This module receives from the data message k of data/address bus and is stored in the random access memory ram 5 of this module, simultaneously again according to the code length control signal ctrl receiving, data message k is divided into groups to obtain information code character { k
1, k
2..., k
ctrl, and by this code character { k
1, k
2..., k
ctrlbe sent in RS code coding module 3;
Described control module 2, is provided with three signal input parts, is respectively clock control signal clk, asserts signal rst and enable signal EN; This module, for controlling and coordinate the transfer of data between transmitting terminal buffer module module 1, RS code coding module 3, interleaving block 6, rx-side buffering module 4, de-interleaving block 6 and RS code decoding module 5, is controlled RS coder and data/address bus simultaneously and is carried out exchanges data;
Described RS coding module 3, adopts constant coefficient Galois field multiplier, for inputting code character { k to every group
1, k
2..., k
ctrlencode, obtain 16 check digit { p
1, p
2..., p
16, and will input code character { k
1, k
2..., k
ctrland check digit { p
1, p
2..., p
16the sequencing output code character { C that obtains encoding
1, C
2..., C
ctrl+16, this coding code character { C
1, C
2..., C
ctrl+16export to interleaving block 6.
Described interleaving block 6, receives the coding code character { C sending from RS coding module 3
1, C
2..., C
ctrl+16, this code character is carried out to interleaving treatment, exchange each code word C by the algorithm that interweaves
iposition, wherein 1≤i≤ctrl, code character { C' after obtaining interweaving
1, C'
2..., C'
ctrl+16and be sent to channel.
Described rx-side buffering module 4, forms two by a random access memory ram 6 and receives signal end, and the front end of this random access memory ram 6 is provided with two and receives signal end, is respectively used to receive the code character { R' from data/address bus
1, R'
2..., R'
ctrl+16and code length control signal ctrl-r, wherein ctrl-r=ctrl+16, and obtain corresponding modifying factor { α by code length control signal ctrl-r
0, α
j, α
2*j..., α
16*j, simultaneously by the code character { R' receiving
1, R'
2..., R'
ctrl+16be stored in the random access memory ram 6 of this module, then from RAM6 by code character { R'
1, R'
2..., R'
ctrl+16sequentially be sent in de-interleaving block 7.
Described de-interleaving block 7, for receiving the code character { R' sending from rx-side buffering module 4
1, R'
2..., R'
ctrl+16, this code character is carried out to deinterleaving processing, exchange each code word R' by the algorithm of deinterleaving
l, wherein 1≤l≤ctrl-r, obtains the code character { R1 after deinterleaving
1, R1
2..., R1
ctrl+16and being sent to RS decoding module 5, described deinterleaving algorithm is reciprocal with the algorithm that interweaves.
Described RS code decoding module 5, for the code character { R1 sending receiving deinterleaver
1, R1
2..., R1
ctrl+16carry out decoding, thus coded message recovered, and by its output.
With reference to Fig. 2, the RS coding module 3 in the present invention, by 16 registers reg1, reg2 ..., reg16}, 16 constant coefficient Galois field multiplier { mul
1, mul
2..., mul
16, 16 XOR gate Xor1, Xor2 ..., Xor16} and two K switch 5, K6 composition; Wherein: the back contact of the 6th K switch 6 is connected respectively on a end of the 5th K switch 5 front contacts and the input of the 16 XOR gate Xor16; The output of the 16 XOR gate Xor16 respectively with 16 constant coefficient Galois field multiplier { mul
1, mul
2..., mul
16input and the b end of the 5th K switch 5 front contacts be connected; The first constant coefficient Galois field multiplier mul
1output is connected to the first register reg1, remaining 15 constant coefficient Galois field multiplier { mul
2, mul
3..., mul
16output be connected to 15 XOR gate Xor1, Xor2 ..., the input of Xor15}, and these 15 registers reg1, reg2 ..., the output of reg15} be also connected to 15 XOR gate Xor1, and Xor2 ..., the input of Xor15}, simultaneously these 15 XOR gate { Xor1, Xor2, ..., the output of Xor15} is connected to 15 registers { reg2, reg3, ..., the input of reg16}, and the 16 register reg16 output is connected with the 16 XOR gate Xor16 input.
When there being information code character { k
1, k
2..., k
ctrlwhen input, the 5th K switch 5 is placed in front contact a, the 6th K switch 6 closures, input { k successively under the control of clock clk rising edge
1, k
2..., k
ctrl, the k of each input
iobtain return value databack, wherein 1≤i≤ctrl with the 16 register reg16 phase XOR; Under the control of clock clk rising edge, databack sends into the first constant coefficient Galois field multiplier mul
1carry out computing, obtain result and leave in the first register reg1; Meanwhile, under the control of clk rising edge, databack sends into respectively other constant coefficient Galois field multiplier { mul
2, mul
3..., mul
16in carry out computing, then by operation result and register reg1, reg2 ..., reg15} phase XOR, obtain result deposit in respectively register reg2, reg3 ..., in reg16}; As information { k
1, k
2..., k
ctrlend of input, the 5th K switch 5 is placed in to front contact b, disconnect the 6th K switch 6, under the control of clock clk rising edge, export successively 16 memories reg16, reg15 ..., the check digit { p storing in reg1}
1, p
2..., p
16, will input code character { k
1, k
2..., k
ctrland check digit { p
1, p
2..., p
16output code character { the C that obtains encoding sequentially
1, C
2..., C
ctrl+16in.
With reference to Fig. 3, interleaving block 6 of the present invention, is made up of a read only memory ROM 1, two random access memory rams 1, RAM2 and two K switch 1, K2; Wherein the back contact of the first K switch 1 and the front contact of second switch K2 and the 5th K switch 5 of RS coding module is connected, the back contact of the first K switch 1 is connected with the first random access memory ram 1 information input terminal, the back contact of second switch K2 is connected with the second random access memory ram 2 information input terminals, and the information output of the first read only memory ROM 1 is connected with the address input end of the second random access memory ram 2 with the first random access memory ram 1 respectively;
As first group of data { C1
1, C1
2..., C1
ctrl+16when input the first K switch 1 closure, second switch K2 opens, under the control of clock clk rising edge, the address input end that the address information in the first read only memory ROM 1 is read into the first random access memory ram 1 stores in the first random access memory ram 1 to control data; After the first random access memory ram 1 is filled with, under the control of clock clk trailing edge, the data message in the first random access memory ram 1 is exported to { C1' in order
1, C1'
2..., C1'
ctrl+16, the first K switch 1 is opened simultaneously, second switch K2 closure, and under the control of clock clk rising edge, the address information in the first read only memory ROM 1 is read into the address input end of the second random access memory ram 2 to control next group data { C2
1, C2
2..., C2
ctrl+16be read in the second random access memory ram 2, after the second random access memory ram 2 is filled with, under the control of clock clk trailing edge, the data message in the second random access memory ram 2 is exported to { C2' in order
1, C2'
2..., C2'
ctrl+16; The first K switch 1 is alternately opened with second switch K2's, and data are alternately input in the first random access memory ram 1 and the second random access memory ram 2, alternately exports the result after interweaving by the first random access memory ram 1 and the second random access memory ram 2.
With reference to Fig. 4, de-interleaving block 7 of the present invention, is made up of a read only memory ROM 2, two random access memory rams 3, RAM4 and K switch 3, K4; Wherein, the front contact of the 3rd K switch 3 and the 4th K switch 4 is connected with the information output of the 6th random access memory ram 6 of rx-side buffering module, the back contact of the 3rd K switch 3 is connected with the 3rd random access memory ram 3 information input terminals, the back contact of the 4th K switch 4 is connected with the 4th random access memory ram 4 information input terminals, and the second read only memory ROM 2 information outputs are connected with the address input end of the 4th random access memory ram 4 with the 3rd random access memory ram 3 respectively;
As first group of data { R1'
1, R1'
2..., R1'
ctrl+16when input the 3rd K switch 3 closures, the 4th K switch 4 is opened, under the control of clock clk rising edge, the address input end that address information in the second read only memory ROM 2 is read into the 3rd random access memory ram 3 stores in the 3rd random access memory ram 3 to control data, and in this second read only memory ROM 2, in the address information of storage and interleaving block 6, the address information of the first read only memory ROM 1 is reciprocal; After the 3rd random access memory ram 3 is filled with, the data message in the 3rd random access memory ram 3 to be exported in order, Output rusults is { R1
1, R1
2..., R1
ctrl+16, the 3rd K switch 3 is opened simultaneously, the 4th K switch 4 closures, and under the control of clock clk rising edge, the address information in the second read only memory ROM 2 is read into the address input end of the 4th random access memory ram 4 to control next group data { R2'
1, R2'
2..., R2'
ctrl+16be read in the 4th random access memory ram 4, after the 4th random access memory ram 4 is filled with, by the data message output in order in the 4th random access memory ram 4; By alternately opening of the 3rd K switch 3 and the 4th K switch 4, data are alternately input in the 3rd random access memory ram 3 and the 4th random access memory ram 4, alternately export the result after deinterleaving by the 3rd random access memory ram 3 and the 4th random access memory ram 4.
With reference to Fig. 5, RS decoding module 5 of the present invention, by syndrome calculating sub module 51, RiBM algorithm submodule 52, money searching algorithm submodule 53, method Buddhist nun's algorithm submodule 54, FIFO submodule 55 and the electric circuit constitute of correcting a mistake; Wherein, the 3rd random access memory ram 3 of de-interleaving block and the information output of the 4th random access memory ram 4 are connected with the input of FIFO submodule 55 with syndrome calculating sub module 51, the output of syndrome calculating sub module 51 is connected with the input of RiBM algorithm submodule 52, the output of RiBM algorithm submodule 52 is connected with the input of Fa Ni algorithm submodule 54 with money searching algorithm submodule 53 respectively, and the output of money searching algorithm submodule 53, method Buddhist nun's algorithm submodule 54 and FIFO submodule 55 is connected with the input of the circuit of correcting a mistake;
When there being code character { R
1, R
2..., R
ctrl+16when input, respectively by code character { R
1, R
2..., R
ctrl+16be sent in syndrome calculating sub module 51 and FIFO submodule 55, in syndrome calculating sub module 51, to receiving code character { R
1, R
2..., R
ctrl+16carry out interative computation, and under the rising edge control of clock clk, computing obtains 16 associated polynomial coefficient { S
1, S
2..., S
16, and by multinomial coefficient { S
1, S
2..., S
16be sent in RiBM algorithm submodule, under the trailing edge control of clock clk, to the associated polynomial coefficient { S of input
1, S
2..., S
16carry out interative computation according to RiBM algorithm, obtain respectively error location polynomial { Λ
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8, and by error location polynomial { Λ
0, Λ
1..., Λ
8output to money searching algorithm submodule 53 and Fa Ni algorithm submodule 54, by improper value multinomial { Ω
0, Ω
1..., Ω
8output to method Buddhist nun algorithm submodule 54; Money searching algorithm submodule 53 is the error location polynomial { Λ to input under the rising edge control of clock clk
0, Λ
1..., Λ
8carry out interative computation, solve errors present
and this result is sent to the circuit of correcting a mistake; Method Buddhist nun's algorithm submodule 54 is the error location polynomial { Λ to input under the rising edge control of clock clk
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8carry out interative computation, solve improper value
and this result is sent to the circuit of correcting a mistake; FIFO submodule 55 is by the code character { R receiving
1, R
2..., R
ctrl+16store into sequentially in the cell fifo of fpga chip, obtaining errors present
and improper value
after, according to error situation output code character { R
1, R
2..., R
ctrl+16in error correcting circuit, correct.
With reference to Fig. 6, the syndrome calculating sub module 51 in the present invention, by 16 Galois field multiplier { β
1, β
2..., β
16, 16 constant coefficient Galois field multiplier { S_mul
1, S_mul
2..., S_mul
16, 16 XOR gate S_Xor1, S_Xor2 ..., S_Xor16} and 16 register { S_reg
1, S_reg
2..., S_reg
16composition; Wherein, the 3rd random access memory ram 3 of de-interleaving block and the information output of the 4th random access memory ram 4 respectively with 16 Galois field multiplier { β
1, β
2..., β
16input be connected, 16 Galois field multiplier { β
1, β
2..., β
16output and 16 XOR gate S_Xor1, S_Xor2 ..., the input of S_Xor16} is connected, simultaneously 16 constant coefficient Galois field multiplier { S_mul
1, S_mul
2..., S_mul
16output also with 16 XOR gate S_Xor1, S_Xor2 ..., the input of S_Xor16} is connected, 16 XOR gate S_Xor1, S_Xor2 ..., S_Xor16} output and 16 register { S_reg
1, S_reg
2..., S_reg
16input be connected, 16 register { S_reg
1, S_reg
2..., S_reg
16output and 16 constant coefficient Galois field multiplier { S_mul
1, S_mul
2..., S_mul
16input be connected.
When there being code character { R
1, R
2..., R
ctrl+16while being sent to this submodule, under the rising edge control of clock clk by code character { R
1, R
2..., R
ctrl+16simultaneously order be input to 16 Galois field multiplier { β
1, β
2..., β
16in, enter code word is added to modifying factor { α
i, α
2*i..., α
16*i, will add the result after modifying factor to be stored in 16 register { S_reg
1, S_reg
2..., S_reg
16in; Again by 16 register { S_reg
1, S_reg
2..., S_reg
16in storage result be input to 16 constant coefficient Galois field multiplier { S_mul
1, S_mul
2..., S_mul
16in carry out multiplying, by the result through the computing of constant coefficient Galois field multiplier and next group Galois field multiplier { β
1, β
2..., β
16output rusults phase XOR, and be stored in 16 register { S_reg
1, S_reg
2..., S_reg
16in; As code character { R
1, R
2..., R
ctrl+16after input, by 16 register { S_reg
1, S_reg
2..., S_reg
16in the associated polynomial { S that deposits
1, S
2..., S
16be sent in next son module.
With reference to Fig. 7, money search submodule 53 of the present invention, by 9 Galois field multiplier { γ
0, γ
1..., γ
8, 9 constant coefficient Galois field multiplier { σ _ mul
0, σ _ mul
1..., σ _ mul
8, 1 XOR gate σ _ Xor and 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8composition; Wherein, 9 Galois field multiplier { γ
0, γ
1..., γ
8input and the error location polynomial { Λ of RiBM algorithm submodule 52
0, Λ
1..., Λ
8be connected, 9 Galois field multiplier { γ simultaneously
0, γ
1..., γ
8output and 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8input be connected, 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8output and 9 constant coefficient Galois field multiplier { σ _ mul
0, σ _ mul
1..., σ _ mul
8input be connected, 9 constant coefficient Galois field multiplier { σ _ mul
0, σ _ mul
1..., σ _ mul
8output be connected to 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8input, simultaneously 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8output be jointly connected on σ XOR gate σ _ Xor;
When money search submodule 53 receives the error location polynomial { Λ from a upper submodule
0, Λ
1..., Λ
8time, under the control of clock clk rising edge by error location polynomial { Λ
0, Λ
1..., Λ
8be input to 9 Galois field multiplier { γ simultaneously
0, γ
1..., γ
8in carry out multiplying, enter code word is added to modifying factor { α
0, α
i..., α
8*i, will put into 9 register { σ _ reg through the result of multiplier computing
0, σ _ reg
1..., σ _ reg
8in, the result of storing in register is sent to 9 constant coefficient Galois field multiplier { σ _ mul simultaneously
0, σ _ mul
1..., σ _ mul
8carry out multiplying computing, and leave operation result in 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8in, simultaneously by 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8in the result deposited to output to XOR gate σ _ Xor upper, in the time that σ XOR gate σ _ Xor Output rusults is 0, control the circuit working of correcting a mistake.
With reference to Fig. 8, method Buddhist nun's algorithm submodule 54 of the present invention, by 9 multiplier { γ
0, γ
1..., γ
8, 4 multipliers γ '
0, γ '
2..., γ '
6, 9 register { ω _ reg
0, ω _ reg
1..., ω _ reg
8, 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6, 9 multiplication of constant coefficient device { ω _ mul
0, ω _ mul
1..., ω _ mul
8, 4 multiplication of constant coefficient devices σ ' _ mul
0, σ ' _ mul
2..., σ ' _ mul
6, two XOR gate σ ' _ Xor and ω _ Xor, a read only memory ROM 3 and one three input multiplier F_mul composition; Wherein, 9 multiplier { γ
0, γ
1..., γ
8input and the improper value multinomial { Ω of RiBM algorithm submodule 52
0, Ω
1..., Ω
8be connected, 9 multiplier { γ
0, γ
1..., γ
8output and 9 register { ω _ reg
0, ω _ reg
1..., ω _ reg
8input be connected, 9 register { ω _ reg
0, ω _ reg
1..., ω _ reg
8output and 9 multiplication of constant coefficient device { ω _ mul
0, ω _ mul
1..., ω _ mul
8input be connected, simultaneously 9 multiplication of constant coefficient device { ω _ mul
0, ω _ mul
1..., ω _ mul
8output and 9 register { ω _ reg
0, ω _ reg
1..., ω _ reg
8input be connected; 4 multipliers γ '
0, γ '
2..., γ '
6input and the error location polynomial { Λ of RiBM algorithm submodule 52
1, Λ
3..., Λ
7be connected, 4 multipliers γ '
0, γ '
2..., γ '
6output and 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6input be connected, 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6output and 4 multiplication of constant coefficient devices σ ' _ mul
0, σ ' _ mul
2..., σ ' _ mul
6input be connected, simultaneously 4 multiplication of constant coefficient devices σ ' _ mul
0, σ ' _ mul
2..., σ ' _ mul
6output and 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6input be connected; 9 register { ω _ reg
0, ω _ reg
1..., ω _ reg
8output be jointly connected with ω XOR gate ω _ Xor, 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6output be publicly connected with σ ' XOR gate σ ' _ Xor; The output of σ ' XOR gate σ ' _ Xor is connected with the 3rd read only memory ROM 3 front ends; Multiplier F_mul input is connected with the 3rd read only memory ROM 3 outputs with ω XOR gate ω _ Xor output respectively;
When method Buddhist nun submodule 54 receives the error location polynomial { Λ from a upper submodule
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8time, under the control of clock clk rising edge by improper value multinomial { Ω
0, Ω
1..., Ω
8be input to 9 multiplier { γ simultaneously
0, γ
1..., γ
8in carry out multiplying, enter code word is added to modifying factor { α
0, α
i..., α
8*i, will put into 9 register { σ _ reg through the result of multiplier computing
0, σ _ reg
1..., σ _ reg
8in; Simultaneously by error location polynomial { Λ
1, Λ
3..., Λ
7be input to simultaneously 4 multipliers γ '
0, γ '
2..., γ '
6in carry out multiplying, enter code word is added to modifying factor { α
0, α
2*i..., α
6*i, by put into through the result of multiplier computing 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6in; To 9 register { σ _ reg
0, σ _ reg
1..., σ _ reg
8and 4 registers σ ' _ reg
0, σ ' _ reg
2..., σ ' _ reg
6in the value of storage carry out interative computation, interative computation result is outputed to respectively to ω XOR gate ω _ Xor and σ XOR gate σ _ Xor simultaneously, ω XOR gate ω _ Xor and σ XOR gate Output rusults are processed and are obtained improper value
and this improper value is sent to the circuit participation computing of correcting a mistake.
With reference to Fig. 9, RS decoding module clock in the present invention takies schematic diagram, wherein syndrome calculates 51 of submodules and takies ctrl clock, RiBM algorithm submodule 52 takies 16 clocks, money search submodule 53 and Fa Ni algorithm submodule 54 move simultaneously, and these two submodules have only taken ctrl+1 clock, whole RS decoding module takies the individual clock of 2* (ctrl+16) altogether.
Effect of the present invention can further illustrate by following sequential simulation result:
Figure 10 provide with RS(255,239) code be the clock delay situation sequential simulation result of the each module of RS encoder of example, wherein clk is clock control, rst is reset signal, EN be data input effective Enable Pin, ctrl is transmitting terminal code length control signal.As seen from Figure 10, there is 0.5 clock delay in transmitting terminal buffer module, have 0.5 clock delay at RS coding module, there are 255 clock delays at interleaving block, 256 clock delays of Information commons in RS encoder, the coded system of this streamline, has reduced the clock delay of RS encoder.
Figure 11 provide with RS(255,239) code be the clock delay situation sequential analogous diagram of the each module of RS decoder of example, wherein clk is clock control, rst is reset signal, EN be data input effective Enable Pin, ctrl-r is receiving terminal code length control signal.As seen from Figure 11, there is 0.5 clock delay in rx-side buffering module, have 255 clock delays at de-interleaving block, have 271.5 clock delays at RS decoding module, 527 clock delays of Information commons in RS decoder.
More than describing is only example of the present invention, does not form any limitation of the invention.The obvious professional person for this area; understanding after content of the present invention and principle; all may be in the situation that not deviating from the principle of the invention, structure; carry out various corrections and change in form and details, but these corrections based on inventive concept and changing still within claim protection range of the present invention.
Claims (5)
1. the combination of the high-performance based on a FPGA RS processor, comprise: transmitting terminal buffer module (1), control module (2), RS code coding module (3), rx-side buffering module (4), RS code decoding module (5), transmitting terminal buffer module (1) is connected with RS code coding module (3), it is characterized in that:
The output of RS code coding module (3) is connected with interleaving block (6), for code character after encoding is carried out to interleaving treatment, and is sent to channel;
Between rx-side buffering module (4) and RS decoding module (5), be connected with de-interleaving block (7), for to decoding through deinterleaver code character after treatment, export to again RS decoding module (5) thereby recover coded message;
Transmitting terminal buffer module (1), is provided with two and receives signal end, is respectively used to receive data message k and the code length control signal ctrl of data/address bus;
Rx-side buffering module (4), is provided with two and receives signal end, is respectively used to receive the data message { R' of data/address bus
1, R'
2..., R'
ctrl+16and code length control signal ctrl-r, wherein ctrl-r=ctrl+16;
RS decoding module (5), it comprises:
Syndrome calculating sub module (51), for to receiving code character { R
1, R
2..., R
ctrl+16carry out interative computation, and under the rising edge control of clock clk, computing obtains 16 associated polynomial coefficient { S
1, S
2..., S
16, and by multinomial coefficient { S
1, S
2..., S
16be sent in RiBM algorithm submodule;
RiBM algorithm submodule (52), the associated polynomial coefficient { S according to RiBM algorithm to input
1, S
2..., S
16carry out interative computation, and under the trailing edge control of clock clk, obtain respectively error location polynomial { Λ
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8, and by error location polynomial { Λ
0, Λ
1..., Λ
8output to money searching algorithm submodule and Fa Ni algorithm submodule, by improper value multinomial { Ω
0, Ω
1..., Ω
8output to method Buddhist nun algorithm submodule;
Money searching algorithm submodule (53), for the error location polynomial { Λ to input
0, Λ
1..., Λ
8carry out interative computation, and solve errors present under the rising edge control of clock clk
Method Buddhist nun's algorithm submodule (54), for the error location polynomial { Λ to input
0, Λ
1..., Λ
8and improper value multinomial { Ω
0, Ω
1..., Ω
8carry out interative computation, and solve improper value under the rising edge control of clock clk
FIFO submodule (55), for by input code character { R
1, R
2..., R
ctrl+16store into sequentially in the cell fifo of fpga chip, obtaining errors present
and improper value
after, according to error situation output code character { R
1, R
2..., R
ctrl+16in error correcting circuit, correct;
Described syndrome calculating sub module (51), money searching algorithm submodule (53) and method Buddhist nun algorithm submodule (54), it is equipped with modifying factor { α
0, α
j, α
2*j..., α
16*j, for the requirement to code length according to reception data/address bus, these three errors that module produces in iterative process of adaptive correction, to adapt to different code lengths;
Described money searching algorithm submodule (53) is worked with method Buddhist nun algorithm submodule (54) simultaneously, to reduce hardware resource occupancy and to realize high-speed cruising.
2. the combination of the high-performance based on FPGA RS processor according to claim 1, it is characterized in that: described RS code coding module (3), adopt constant coefficient Galois field multiplier, this multiplier is to be made up of the XOR gate walking abreast, the input of XOR gate is by preset parameter requirement input multiplier, to be reduced to one-level XOR by multistage with computing and XOR, the multiplier { a of this multiplier to input
0, a
1, a
2..., a
7carry out finite field multiplier processing, by multiplier { a
0, a
1, a
2..., a
7multiply each other with the preset parameter of multiplier inside, obtain and Output rusults { y
0, y
1, y
2..., y
7, realize the high-speed cruising of encoder.
3. the high-performance based on FPGA according to claim 1 combination RS processor, is characterized in that: described interleaving block is made up of a read only memory ROM 1, two random access memory rams 1, RAM2 and two K switch 1, K2; The back contact of the first K switch 1 is connected with the first random access memory ram 1 information input terminal, the back contact of second switch K2 is connected with the second random access memory ram 2 information input terminals, and the first read only memory ROM 1 information output is connected with the address input end of the second random access memory ram 2 with the first random access memory ram 1 respectively; The first K switch 1 closure in the time of first group of data input, second switch K2 opens, and the address input end that the address information in the first read only memory ROM 1 is read into the first random access memory ram 1 stores in the first random access memory ram 1 to control data; After the first random access memory ram 1 is filled with, by the data message output in order in the first random access memory ram 1, the first K switch 1 is opened simultaneously, second switch K2 closure, the address input end that address information in the first read only memory ROM 1 is read into the second random access memory ram 2 is read in the second random access memory ram 2 to control next group data message, after the second random access memory ram 2 is filled with, by the data message output in order in the second random access memory ram 2; Two switches are alternately opened, and data are alternately input in the first random access memory ram 1 and the second random access memory ram 2, and the first random access memory ram 1 and the second random access memory ram 2 are alternately exported the result after interweaving.
4. the high-performance based on FPGA according to claim 1 combination RS processor, is characterized in that: described de-interleaving block is made up of a read only memory ROM 2, two random access memory rams 3, RAM4 and K switch 3, K4; The back contact of the 3rd K switch 3 is connected with the 3rd random access memory ram 3 information input terminals, the back contact of the 4th K switch 4 is connected with the 4th random access memory ram 4 information input terminals, and the second read only memory ROM 2 information outputs are connected with the address input end of the 4th random access memory ram 4 with the 3rd random access memory ram 3 respectively; The 3rd K switch 3 closures in the time of first group of data input, the 4th K switch 4 is opened, and the address input end that the address information in the second read only memory ROM 2 is read into the 3rd random access memory ram 3 stores in the 3rd random access memory ram 3 to control data; After the 3rd random access memory ram 3 is filled with, by the data message output in order in the 3rd random access memory ram 3, the 3rd K switch 3 is opened simultaneously, the 4th K switch 4 closures, the address input end that address information in the second read only memory ROM 2 is read into the 4th random access memory ram 4 is read in the 4th random access memory ram 4 to control next group data message, after the 4th random access memory ram 4 is filled with, by the data message output in order in the 4th random access memory ram 4; Two switches are alternately opened, and data are alternately input in the 3rd random access memory ram 3 and the 4th random access memory ram 4, and the 3rd random access memory ram 3 and the 4th random access memory ram 4 are alternately exported the result after deinterleaving; Wherein in the second read only memory ROM 2, the address information of storage and the address information of the first read only memory ROM 1 are reciprocal.
5. the high-performance based on FPGA according to claim 1 combination RS processor, is characterized in that: described code length control signal ctrl for receiving the length with control inputs code character from the control information of data/address bus, provides corresponding modifying factor { α simultaneously
0, α
j, α
2*j..., α
16*j, make RS processor adapt to the different requirements of inputting code lengths, to improve the portability of RS processor.
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