CN101969358A - High-speed parallel RS decoding method for space communication - Google Patents

High-speed parallel RS decoding method for space communication Download PDF

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CN101969358A
CN101969358A CN2010102978843A CN201010297884A CN101969358A CN 101969358 A CN101969358 A CN 101969358A CN 2010102978843 A CN2010102978843 A CN 2010102978843A CN 201010297884 A CN201010297884 A CN 201010297884A CN 101969358 A CN101969358 A CN 101969358A
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张拯宁
崔骞
战勇杰
朱翔宇
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Space Star Technology Co Ltd
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Abstract

The invention relates to a high-speed parallel Reed-Solomon (RS) decoding method for space communication. In the method, two decoding modules RS (255, 223) and RS (255, 239) are configured simultaneously, so that a decoder can configure decoding types on line according to coding parameters to flexibly adapt to two coding formats specified by the consultative committee for space data system (CCSDS) standard; input data is filled and acquired in first in first out (FIFO) by ping-pong operation during deinterlacing and interlacing, a multi-channel parallel pipeline mode is adopted during decoding, and a composite structure ensures the maximization of system performance and realizes the minimization of resources and is suitable for 1 to 8 arbitrary interlacing depths; and measures such as multi-channel parallel RS decoding, the optimization of realization logic of a finite field multiplier, and the like are adopted, so that decoding rate is greatly improved. The method can be directly applied to a high-code-rate remote sensing satellite ground receiving system and can further increase parallelism degree and improve performance when necessary by modular design.

Description

A kind of high-speed parallel RS interpretation method that is used for space communication
Technical field
The present invention relates to a kind of high speed decoding method that is used for the RS coding of space communication, be mainly used in the space communication terrestrial channel decoder data after demodulating is carried out High-Speed RS decoding, correct the Channel Transmission mistake, also can be used in the data demodulates receiving equipment of other application direction.
Background technology
The RS sign indicating number is the multi-system BCH code that a class has very strong error correcting capability, also is the Algorithms of Algebraic Geometric Codes of a quasi-representative.It is at first used the MS multinomial by Reed and Solomon and constructs in nineteen sixty.RS sign indicating number with the MS polynomial construction is a nonsystematic code, and can produce systematic code with the BCH code building method.Add 1 because the minimum range of the maximum possible of linear code is the number of verification unit, and the RS sign indicating number is accomplished this point just, therefore, claims that the RS sign indicating number is very big minimum distance seperable code (a MDS sign indicating number).The RS sign indicating number is particularly suitable for using in fading channel, to overcome sudden mistake.Just owing to its superior performance, the RS sign indicating number is obtained extensive use in fields such as deep space communication, digital audio/video communication, magnetic recording medias, and it is the error correction coding that is most widely used at present.
Space communication is RS (255,223) or RS (255, the 239) sign indicating number that consultative committee for space data system (CCSDS) is recommended with the RS sign indicating number, and these two kinds of sign indicating number basic coding parameters are identical, mainly are the error correcting capability differences.The adoptable interleave depth of CCSDS regulation RS sign indicating number is 1,2,3,4,5,8 totally 6 kinds.Often selected different RS type of codings and different interleave depths in different satellite communication systems for use, this has just just brought very big difficulty to space communication with the development of RS decoder.The interpretation method that existing RS decoder adopts realizes deinterleaving and decode procedure respectively that generally the advantage of doing like this is that implementation is simple, and shortcoming is that flexibility is not enough.The decode procedure of RS decoder need carry out a large amount of finite field operations, and wherein the multiplying unit is maximum and also maximum to the influence of decoding speed.Because at present the multiplier that uses in the RS decoder is through optimizing, cause the work clock of decoder can not be too high.Simultaneously, improve constantly because the remote sensing satellite number passes bit rate, it is just bigger further to improve the bit rate difficulty on the basis of different RS coded formats of compatibility and interleave depth.
At present common in the various types of communication system all is the RS decoder of low bit rate rate usually, and general bit rate is at tens bit/s; Space communication be about 470Mbps with RS decoder single channel the highest decoding speed at present, and compatible RS (255,223) and RS (255,239) yard simultaneously, and the interleave depth that can adapt to is generally fixed value.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of high speed decoding method that is used for the RS coding of space communication is provided, this interpretation method is compatible RS (255 simultaneously, 223) and RS (255,239) sign indicating number and any interleave depth (1-8), and decoding speed is far above prior art.
Technical solution of the present invention is:
A kind of high-speed parallel RS interpretation method that is used for space communication, step is as follows:
(1) parameter of decode procedure is set, described parameter comprises pass-through state parameter, interleave depth parameter, total frame length, decoding type parameter;
(2) judge according to the pass-through state parameter that is provided with in the step (1) whether decode procedure is pass-through state, if pass-through state then will be imported data and directly export; If not pass-through state then enters step (3);
(3) by the frame length counter input data are counted, whether the count results according to the total frame length judgment frame long counter that is provided with in the step (1) equals total frame length, if be not equal to total frame length, then data are write among i the input FIFO, the count results of frame length counter adds 1 simultaneously, enters step (4) afterwards; If equal total frame length, the data that then read among all input FIFO enter step (5) afterwards; Described i is 1 natural number between the interleave depth parameter, and the initial value of i is 1;
(4) judge whether i equals the interleave depth parameter,, then i is initialized as 1 and returns step (3) afterwards if equal; If be not equal to, then return afterwards step (3) for i the i+1 assignment;
(5) judge that according to the decoding type parameter using any decoding module to carry out RS deciphers, if the decoding type parameter is 255/223, then use the RS223 decoding module to carry out RS decoding, the data after the decoding are imported among j the output FIFO, enter step (6) afterwards; If the decoding type parameter is 255/239, then use the RS239 decoding module to carry out RS decoding, the data after the decoding are imported among j the output FIFO, enter step (6) afterwards; Described j is 1 natural number between the interleave depth parameter, and the initial value of j is 1;
(6) judge that whether j output FIFO is empty, if empty, then enters step (7); If be not empty, then reading of data and output from j output FIFO enters step (8) afterwards;
(7) judge whether j equals the interleave depth parameter,, then return afterwards step (6) for j the j+1 assignment if be not equal to; If equal, then return step (2);
(8) judge whether j equals the interleave depth parameter,, then j is initialized as 1 and returns step (6) afterwards if equal; If be not equal to, then return afterwards step (6) for j the j+1 assignment.
The middle RS223 of use of described step (5) decoding module carries out RS decoding and uses the RS239 decoding module to carry out RS decoding and carry out according to following steps:
(a) data that receive are deposited in the receiving sequence buffer memory wait for correction process, simultaneously, the described data that receive with Horner algorithm computation syndrome S, are entered step (b) afterwards;
(b) use the RiBM algorithm to try to achieve error location polynomial and improper value multinomial, enter step (c) afterwards by the syndrome S that obtains in the step (a);
(c) utilize the error location polynomial that obtains in the step (b) to make the searching algorithm mistake in computation position of spending money, utilize the improper value multinomial that obtains in the step (b) to use Forney algorithm computation improper value simultaneously, according to described errors present and improper value the data of waiting for correction process in the receiving sequence buffer memory in the step (a) are carried out correction process and output afterwards.
Employed multiplication calculates according to following formula and realizes in described Horner algorithm, RiBM algorithm, money searching algorithm and the Forney algorithm:
C=AB=d+Q Te=Lb+Q TUb,
Wherein, C is the product of A and B,
Figure BSA00000291227400031
Figure BSA00000291227400032
The vector representation of A is a=[a 0, a 1..., a M-1] TThe vector representation of B is b=[b 0, b 1..., b M-1] T,
Figure BSA00000291227400042
Q is for satisfying α The matrix of=Q α modp (α), p (α) is GF (2 m) primitive polynomial in territory, α is the root of primitive polynomial, α =[α m, α M+1..., α 2m-1] TThe present invention's beneficial effect compared with prior art is:
(1) the present invention makes decoder decipher type, above-mentioned two kinds of coded formats of flexible adaptation CCSDS standard code according to the coding parameter Configuration Online by disposing RS (255,223) and two kinds of decoding modules of RS (255,239) simultaneously;
(2) the present invention by in deinterleaving and interleaving process, adopt ping-pong operation finish the input data in FIFO filling and obtain, and in decode procedure, adopt the mode of multidiameter delay flowing water, guarantee the maximization of systematic function and realized minimizing of resource by this composite construction, and can adapt to any interleave depth of 1 to 8;
(3) the present invention is by taking the measures such as realization logic of multidiameter delay RS decoding, optimization Galois field multiplier, improved decoding rate greatly, can directly apply to high bit rate remote sensing satellite ground receiving system, by adopting modularized design, can further increase degree of parallelism when needed and improve performance.
Description of drawings
Fig. 1 forms schematic diagram for RS code decoder of the present invention;
Fig. 2 is a RS decoder process chart of the present invention;
Fig. 3 is a high-speed parallel RS interpretation method flow chart of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described in detail.
The RS sign indicating number is a kind of chnnel coding form, and it belongs to linear block codes.Because the RS sign indicating number is to be based upon on the basis of finite field algebraically to make up, and is well suited for being used for the multi-system modulating system.The main application of RS sign indicating number is to overcome the unexpected error that produces in the fading channel, and it also usually uses as ISN and convolution code cascade, so that obtain bigger coding gain.Since in the space communication owing to often run into the unexpected error that lightning etc. causes, so RS is well suited for using in space communication.Be accompanied by the development of space communications technique, the transfer of data bit rate improves constantly, and the RS decoding rate also needs corresponding raising to adapt to growth requirement.The present invention mainly solves the problem that how to improve decoding rate in the realization of RS decoder, by the interpretation method that adopts the present invention to propose, can increase substantially decoding rate, compatible RS (255,223) and RS (255,239) two kinds of coded formats, and adapt to any interleave depth of 1 to 8, can directly apply to high bit rate remote sensing satellite ground receiving system.
Be illustrated in figure 1 as RS code decoder of the present invention and form schematic diagram, the present invention deciphers part and adopts 8 road parallel organizations, each road includes input FIFO, output FIFO, decoding type gate, decoding nuclear is formed, and like this can decoding speed accelerates greatly and can decipher needs according to reality and select interleave depth, and adapt to any interleave depth of 1 to 8.
High-speed parallel RS interpretation method of the present invention is carried out according to following steps as shown in Figure 3:
(1) parameter of decode procedure is set, described parameter comprises pass-through state parameter, interleave depth parameter, total frame length, decoding type parameter; The pass-through state parameter is for more flexible when the RS decoder uses, and selecting to lead directly to when not needing RS decoding can be with data without directly output of decoding; The interleave depth parameter is any natural number of 1 to 8; Total frame length is determined to get final product according to the practical communication agreement; The decoding type parameter refers to that the RS coded format of using in the communication system is specially any of RS (255,233) or RS (255,239) sign indicating number.
(2) judge according to the pass-through state parameter that is provided with in the step (1) whether decode procedure is pass-through state, if pass-through state then will be imported data and directly export; If not pass-through state then enters step (3).
What step 3 and step 4 were described is the process partly that interweaves, and belongs to ping-pong operation.
(3) by the frame length counter input data are counted, whether the count results according to the total frame length judgment frame long counter that is provided with in the step (1) equals total frame length, if be not equal to total frame length, then data are write among i the input FIFO, the count results of frame length counter adds 1 simultaneously, enters step (4) afterwards; If equal total frame length, the data that then read among all input FIFO enter step (5) afterwards; Described i is 1 natural number between the interleave depth parameter, and the initial value of i is 1; Finish the deinterleaving process by this step, interleaving data is reverted to the output format of single channel RS coding.The frame length counter is exactly to be used for a counter of continuous data frame length.
(4) judge whether i equals the interleave depth parameter, and the interleave depth parameter sets when being the first step,, then i is initialized as 1 and returns step (3) afterwards if equal; If be not equal to, then return afterwards step (3) for i the i+1 assignment.
(5) judge that according to the decoding type parameter using any decoding module to carry out RS deciphers, if the decoding type parameter is 255/223, then use the RS223 decoding module to carry out RS decoding, the data after the decoding are exported among j the output FIFO, enter step (6) afterwards; If the decoding type parameter is 255/239, then use the RS239 decoding module to carry out RS decoding, the data after the decoding are exported among j the output FIFO, enter step (6) afterwards; Described j is 1 natural number between the interleave depth parameter, and the initial value of j is 1; This step realizes RS decoding by the decoder that calls corresponding RS type, and the RS decode procedure comprises 5 modules, as shown in Figure 2.
1) with the Horner algorithm by the syndrome that calculates that receives;
2) try to achieve error location polynomial and improper value multinomial by Si with the key equation solving algorithm with the RiBM algorithm;
3) search method of spending money is tried to achieve the root of error location polynomial, obtains the errors present number, determines errors present;
4) try to achieve improper value with the Forney algorithm by the improper value multinomial, obtain improper value;
5) deduct improper value by the input data at corresponding errors present place at last, finish error correction.
If the receiving sequence multinomial is R (x)=r N-1x N-1+ ...+r iX+r 0, then consider the data input condition of decoding algorithm, syndrome can be expressed as by the Horner algorithm computation:
S i = R ( α m 0 + i - 1 ) = ( . . . ( ( r N - 1 α m 0 + i - 1 + r N - 2 ) α m 0 + i - 1 + r N - 3 ) α m 0 + i - 1 + . . . + r 1 ) α m 0 + i - 1 + r 0
i=1,2,…D-1
Finding the solution the Horner algorithm of syndrome, the RiBM algorithm of finding the solution key equation, the Forney algorithm of finding the solution " the money search method " of errors present and finding the solution improper value has had fairly perfect achievement in research, belongs to the known technology of this area.But use in the process of these several algorithm computation, can relate to a lot of multiplyings, in other words, the speed of a large amount of multiplyings has also just determined the execution speed of these several algorithms, therefore, the present invention has designed a kind of method of new multiplying, has accelerated the arithmetic speed of these several algorithms greatly, thereby has improved the speed of decoding on the whole.
Following several steps belongs to the process of deinterleaving part, belongs to ping-pong operation.
(6) judge that whether j output FIFO is empty, if empty, then enters step (7); If be not empty, then reading of data and output from i output FIFO enters step (8) afterwards.
(7) judge whether j equals the interleave depth parameter,, then return afterwards step (6) for j the j+1 assignment if be not equal to; If equal, then return step (2).
(8) judge whether j equals the interleave depth parameter,, then j is initialized as 1 and returns step (6) afterwards if equal; If be not equal to, then return afterwards step (6) for j the j+1 assignment.
Employed multiplication calculates according to following formula and realizes in described Horner algorithm, RiBM algorithm, money searching algorithm and the Forney algorithm:
C=AB=d+Q Te=Lb+Q TUb,
Wherein, C is the product of A and B,
Figure BSA00000291227400071
Figure BSA00000291227400072
The vector representation of A is a=[a 0, a 1..., a M-1] TThe vector representation of B is b=[b 0, b 1..., b M-1] T,
Figure BSA00000291227400073
Figure BSA00000291227400074
Q is for satisfying α The matrix of=Q α modp (α), p (α) is GF (2 m) primitive polynomial in territory, be known content, so α is the root of primitive polynomial, contents known just, α =[α m, α M+1..., α 2m-1] TTherefore, from top these conditions, can obtain the value of Q, and then obtain product.
The realization of the element multiplication on two galois fields is difficulty comparatively, can realize with the method for checking numerical table and antilogarithm table when software is realized; In realizing, then realizes by hardware with combinational logic.In the algebraic(al) decoder of RS sign indicating number, Galois field multiplier is to use at most and the maximum parts of time delay, and its calculation delay has determined the working clock frequency of decoder.How realizing Galois field multiplier, reduce its arithmetic time delay, improve the performance of RS code decoder, is a key issue will considering in the RS code decoder implementation procedure.Other computing in the finite field, for example division, invert and can realize indirectly with multiplier.In engineering practice, the most frequently used Galois field multiplier is nature base multiplier and antithesis-basic naturally multiplier.
Galois field multiplier can be divided into two kinds of bit serial multiplier and bit parallel multipliers from implementation structure.The bit serial multiplier architecture is realized going up fairly simple, and the area complexity is O (m), but because computing is undertaken by bit, the realization of High Speed difficulty is bigger.The bit parallel multiplier connects by circuit, directly realizes the result of output multidigit computing, can significantly improve processing speed, and the area complexity is O (m2).Be exactly mixing (Hybrid) structure of string and combination in addition.Remove the influence of implementation structure, the complexity that Galois field multiplier is realized the substrate main and territory is closely related.
The parallel finite field multiplier algorithm of the low complexity bit that this method adopts, its main design philosophy is to do the processing that a similar LU decomposes, and greatly reduces the hardware implementation complexity, and tactical rule, processing speed is fast.Its principle is described below.
If p (α) is GF (2 m) primitive polynomial in territory, α is the root of primitive polynomial, A, B are the element among the C=AB,
Figure BSA00000291227400081
The vector representation of A is a=[a 0, a 1..., a M-1] TSimilarly, the vector representation of B is b=[b 0, b 1..., b M-1] TIntroduce GF (2 m) in variable α (m-1) * and m rank matrix Q, satisfy:
α =Q·αmodp(α)
Wherein
α =[α m,α m+1,…,α 2m-1] T
Introduce matrix:
Figure BSA00000291227400082
Figure BSA00000291227400091
If:
d=Lb
e=Ub
Then can prove and draw:
C=AB=d+Q Te
Through a large amount of emulation and engineering test, use this method can make the RS decoding rate reach 1.2Gbit/s, be better than the performance index of the decoder of the same type delivered in the present document, the present invention when needed can also further improve performance by increasing degree of parallelism.
The content that is not described in detail in the specification of the present invention belongs to the known technology of this area.

Claims (3)

1. high-speed parallel RS interpretation method that is used for space communication is characterized in that step is as follows:
(1) parameter of decode procedure is set, described parameter comprises pass-through state parameter, interleave depth parameter, total frame length, decoding type parameter;
(2) judge according to the pass-through state parameter that is provided with in the step (1) whether decode procedure is pass-through state, if pass-through state then will be imported data and directly export; If not pass-through state then enters step (3);
(3) by the frame length counter input data are counted, whether the count results according to the total frame length judgment frame long counter that is provided with in the step (1) equals total frame length, if be not equal to total frame length, then data are write among i the input FIFO, the count results of frame length counter adds 1 simultaneously, enters step (4) afterwards; If equal total frame length, the data that then read among all input FIFO enter step (5) afterwards; Described i is 1 natural number between the interleave depth parameter, and the initial value of i is 1;
(4) judge whether i equals the interleave depth parameter,, then i is initialized as 1 and returns step (3) afterwards if equal; If be not equal to, then return afterwards step (3) for i the i+1 assignment;
(5) judge that according to the decoding type parameter using any decoding module to carry out RS deciphers, if the decoding type parameter is 255/223, then use the RS223 decoding module to carry out RS decoding, the data after the decoding are imported among j the output FIFO, enter step (6) afterwards; If the decoding type parameter is 255/239, then use the RS239 decoding module to carry out RS decoding, the data after the decoding are imported among j the output FIFO, enter step (6) afterwards; Described j is 1 natural number between the interleave depth parameter, and the initial value of j is 1;
(6) judge that whether j output FIFO is empty, if empty, then enters step (7); If be not empty, then reading of data and output from j output FIFO enters step (8) afterwards;
(7) judge whether j equals the interleave depth parameter,, then return afterwards step (6) for j the j+1 assignment if be not equal to; If equal, then return step (2);
(8) judge whether j equals the interleave depth parameter,, then j is initialized as 1 and returns step (6) afterwards if equal; If be not equal to, then return afterwards step (6) for j the j+1 assignment.
2. according to the described a kind of high-speed parallel RS interpretation method that is used for space communication of claim 1, it is characterized in that the middle RS223 of use of described step (5) decoding module carries out RS decoding and uses the RS239 decoding module to carry out RS decoding and carry out according to following steps:
(a) data that receive are deposited in the receiving sequence buffer memory wait for correction process, simultaneously, the described data that receive with Horner algorithm computation syndrome S, are entered step (b) afterwards;
(b) use the RiBM algorithm to try to achieve error location polynomial and improper value multinomial, enter step (c) afterwards by the syndrome S that obtains in the step (a);
(c) utilize the error location polynomial that obtains in the step (b) to make the searching algorithm mistake in computation position of spending money, utilize the improper value multinomial that obtains in the step (b) to use Forney algorithm computation improper value simultaneously, according to described errors present and improper value the data of waiting for correction process in the receiving sequence buffer memory in the step (a) are carried out correction process and output afterwards.
3. according to the described a kind of high-speed parallel RS interpretation method that is used for space communication of claim 2, it is characterized in that employed multiplication calculates according to following formula and realizes in described Horner algorithm, RiBM algorithm, money searching algorithm and the Forney algorithm:
C=AB=d+Q Te=Lb+Q TUb,
Wherein, C is the product of A and B,
Figure FSA00000291227300021
Figure FSA00000291227300022
The vector representation of A is a=[a 0, a 1..., a M-1] TThe vector representation of B is b=[b 0, b 1..., b M-1] T,
Figure FSA00000291227300023
Figure FSA00000291227300024
Q is for satisfying α The matrix of=Q α modp (α), p (α) is GF (2 m) primitive polynomial in territory, α is the root of primitive polynomial, α =[α m, α M+1..., α 2m-1] T
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CN102361460A (en) * 2011-07-28 2012-02-22 航天恒星科技有限公司 General high speed parallel cycle interleaving Viterbi decoding method
CN102361460B (en) * 2011-07-28 2013-10-16 航天恒星科技有限公司 General high speed parallel cycle interleaving Viterbi decoding method
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CN103795425A (en) * 2014-01-27 2014-05-14 中国电子科技集团公司第十研究所 Code rate compatible RS code decoder
CN103929209A (en) * 2014-04-09 2014-07-16 西安电子科技大学 High-performance combined RS processor based on FPGA
CN114499767A (en) * 2022-04-14 2022-05-13 苏州联讯仪器有限公司 Data transmission system and RS (Reed-Solomon) coding device and method thereof
CN116881183A (en) * 2023-09-06 2023-10-13 北京融为科技有限公司 Method and device for processing decoded data

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