CN101478670A - Network real-time video collecting apparatus developed based on FPGA chip and DSP chip - Google Patents
Network real-time video collecting apparatus developed based on FPGA chip and DSP chip Download PDFInfo
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Abstract
The present invention discloses a network real-time video collecting device based on FPGA chip and DSP chip development. The device of the invention comprises a video collecting module, a video signal processing module, a network control module, a handshake control module of press button switch and network protocol and an upper machine terminal alternation module. The device realizes the high-speed real-time collection and network transmission to analog video signal/analog television signal or high resolution computer signal. Based on the network handshake protocol between the upper machine and video collecting device which are developed independently on the video collection hardware platform, the specific data in the negotiation package can be flexibly set for controlling the working state of collecting device and realizing the network intelligent control of a plurality of video collecting devices. The device is composed of small-capability FPGA chip and intermediate-performance DSP chip, and can be widely used for the fields of enterprise/family guarding system, real-time video monitoring of operating interface of computer device, visual auxiliary drive of intelligent vehicle, etc.
Description
Technical field:
The invention belongs to wireless communication technology field, relate to a kind of network real-time video collecting apparatus, especially a kind of network real-time video collecting apparatus based on fpga chip and dsp chip exploitation.
Background technology
Video acquisition is the problem of obtaining that solves video information.Because digitized signal is convenient to storage and is handled, the video acquisition process is generally obtained analog video signal/anolog TV signals CVBS/S-Video (PAL/NTSC standard) by CCD or CMOS camera, export the digital luminance signal Y that meets the ITU601 standard by analog video decoder device analog video decoder chip (Decoder) 110 decodings, more digital brightness signal Y is carried out operations such as Digital Image Processing, storage, Network Transmission.Wherein the field rate of pal mode is 25fps, and resolution is 720 * 288; The field rate of TSC-system formula is 30fps, and resolution is 720 * 240.Common video acquisition device can only be supported the analog video signal of PAL/NTSC is gathered, exist the resolution gathered not high, do not support computer VGA interface collection of video signal, do not support problem such as real-time network transmission, fail to satisfy fields such as security protection, industry, automobile assistant driving and require high-resolution acquisition, implement a difficult problem such as processing.How to design and realize a kind ofly can gathering analog video signal, gathering high-resolution computer VGA interface vision signal again, can become one of research focus of network real-time video collecting apparatus exploitation to satisfy field application demands such as security protection, industry, automobile assistant driving by the network real-time video collecting apparatus of Ethernet real-time Transmission again simultaneously.
Summary of the invention
The objective of the invention is to, a kind of network real-time video collecting apparatus based on fpga chip and dsp chip exploitation is provided, can gather analog video signal PAL/NTSC, can gather the computer VGA interface vision signal of multiple resolution again, be real-time transmitted to long-range server receiving terminal by Ethernet simultaneously.The cost of whole device is not high, area is less than 20cm * 40cm, is fit to use in batches.The real time video collection of the highest support SXGA1280 * 1024 resolution, the video data of the highest support of the video input interface of Video processing dsp chip 130 80MHz receives, dsp chip 130 maximum operating frequencies that adopted can reach that 720MHz, disposal ability can reach 5760MIPS, integrated image is gathered special-purpose peripheral hardware video/audio input/output interface (Video_Port is abbreviated as VP) and network control module 300 ethernet control chips (EMAC) 140, can satisfy real-time processing requirements of the present invention.
This video acquisition device operation principle: being converted to digital luminance signal Y by analog video decoder chip (Decoder) 110 collection analog video signal CVBS or anolog TV signals S-Video, is the digital rgb signal by modulus conversion chip (video sampling chip) ADC collecting computer conversion of signals; Digital luminance signal Y directly delivers to dsp chip 130, and the digital rgb signal is changed through the chrominance space of fpga chip 210 and fallen line frequency and handle output digital luminance signal Y to dsp chip 130; By dsp chip 130 by the procotol encapsulation after, data are sent to the server receiving terminal in real time by Ethernet; Receiving terminal extracts the brightness signal Y of original video data by agreement.But server receiving terminal Intelligence Selection analog video or computer acquisition passage, and can give the distribution network address sequence SN respectively of a plurality of video acquisition devices in the consolidated network, promptly each video acquisition device obtains oneself an IP address and a MAC Address.
To achieve these goals, the present invention has taked following technical scheme:
Network real-time video collecting apparatus based on fpga chip and dsp chip exploitation is characterized in that: this network real-time video collecting apparatus comprises that video acquisition module 100, video signal processing module 200, network control module 300, button switch and the shake hands control module and the host computer terminal interaction module of procotol; Video acquisition module 100 is used to gather vision signal; Video signal processing module 200 is used for vision signal and handles; Network control module 300 is used for Control Network; Button switches and the control module of shaking hands of procotol is used to control computer standard or analog video signal standard; What host computer terminal interaction module was used to realize 300 of host computer and network control modules communicates by letter, shows in real time the video data that receives, video format, the stored video data that Control Network control module 300 is gathered; Vision signal by camera or the input of computer VGA interface, convert the digital rgb signal to through video acquisition module 100, carry out chrominance space conversion, down conversion process and data rearrangement by 200 pairs of digital rgb signals of video signal processing module, again brightness signal Y is delivered to dsp chip 130, through passing through external network control chip 310 transmission video datas to host computer by dsp chip 130 according to the request and the procotol of host computer after the storage of outside SDRAM.
Described video acquisition module 100 comprises analog video decoder chip 110, video/audio input/output interface and modulus conversion chip 120, analog video decoder chip 110 and modulus conversion chip 120 are carried out the initialization setting of chip by total line traffic control by dsp chip 130, analog video decoder chip 110 is gathered analog video signal and analog video signal is converted to digital luminance signal Y, modulus conversion chip collecting computer signal also is converted to the digital rgb signal with Computer signal, and digital luminance signal Y directly delivers to dsp chip 130.
Described video signal processing module 200 is by detection module 230, identification module 220, chrominance space modular converter 210, brightness enhancement algorithms module 240 and the row deposit data module 250 that reorders constitutes, the digital rgb signal is after module 230 detects after testing, detect the standard of input Computer signal by identification module 220, realize of the chrominance space conversion of digital rgb signal by chrominance space modular converter 210 then to digital luminance signal Y, realize that by brightness enhancement algorithms module 240 contrast to input picture strengthens and brightness strengthens again, by module 250 realizations of reordering of row deposit data data line is deposited control at last, data rearrangement, clock two divided-frequency and down conversion process.
Described detection module 230 detects the stability of input Computer signal, comprises that the computer interface plug detects and unexpected detection of power loss; Described identification module 220 detects the standard of input Computer signal; Described chrominance space modular converter 210 is realized the chrominance space conversion of digital rgb signal to digital luminance signal Y; Described brightness enhancement algorithms module 240 realizes the contrast of input picture is strengthened and the brightness enhancing; The module 250 of reordering described capable deposit data realizes data line is deposited control, data rearrangement, clock two divided-frequency and down conversion process, adopts two row to deposit into road wheel stream and sends and storage, original 8 brightness signal Y is expanded to 16 brightness signal Y export.
Described network control module 300, form by ethernet control chip 140 and data management interface two parts, wherein ethernet control chip 140 is the network data passage, data management interface is the state and the control interface of ethernet control chip 140, comprises a configuration register in network control module.
Described button switches the control module of shaking hands with procotol, comprises the keyboard input controller and the button of expansion, by key control computing mechanism formula or control analog video signal standard.
In the described host computer terminal interaction module, communicating by letter between host computer and the network control module 300 used udp protocol, and utilize multithreading to realize real time data processing in the network service, comprise the broadcasting thread, reply thread, receiving thread, display image thread, data statistics thread, storage thread and data transaction thread.
By above 5 modules, network real-time video collecting apparatus of the present invention is realized real-time collection and the Network Transmission to analog video signal or computer high-resolution signal, and utilize the Handshake Protocol of host computer (server) and slave computer (this device), concrete data in the negotiated packet can be set, control the operating state of this device.
Characteristics of the present invention are to adopt fpga chip 210 and dsp chip 130 to constitute network real-time video collecting apparatus cheaply, realize analog video signal or high resolution computer real-time signal acquisition and Network Transmission.
Compared with the prior art, technique effect of the present invention is embodied in:
1. compare with traditional network video collecting device, video acquisition device of the present invention has enriched the problem of legacy device interface unification, realization can be gathered analog video signal can gather the high resolution computer signal again, simultaneously by Ethernet real-time Transmission video data.
2. the present invention has developed the network Handshake Protocol between a cover host computer (server) and the video acquisition device, agreement is succinctly easy-to-use, and concrete data in the negotiated packet can be set flexibly controlling the operating state of this device, thereby realize the network intelligence control of video acquisition device.
3. the present invention is made of fpga chip and dsp chip, has characteristics cheaply.
Description of drawings
Fig. 1 is a system construction drawing of the present invention.
Fig. 2 is a fpga chip Video processing structure chart of the present invention.
Fig. 3 is a built-in system software design flow diagram of the present invention.
Below in conjunction with accompanying drawing the present invention is described in further detail.
Embodiment
Referring to Fig. 1, network real-time video collecting apparatus is made of fpga chip 210 and dsp chip 130, comprises that video acquisition module 100, video signal processing module 200, network control module 300, button switch and the shake hands control module and the host computer terminal interaction module of procotol.Wherein primary processor is a dsp chip 130, and this dsp chip 130 has video/audio input/output interface (VP) and Ethernet interface.To vision signal by camera or the input of computer VGA interface, convert the digital rgb signal to through analog video decoder chip (Decoder) 110 and modulus conversion chip (ADC) 120, carry out chrominance space conversion, down conversion process and data rearrangement by 210 pairs of digital rgb signals of fpga chip, again brightness signal Y is delivered to dsp chip 130, through passing through the corresponding video data of external network control chip 310 transmissions to host computer by dsp chip 130 according to the request and the procotol of last seat in the plane after the storage of outside SDRAM.Dsp chip 130 control programs are solidificated in the Flash chip, and the function of the keyboard input controller of expansion is realized that by the CPLD500 chip controlled function of shaking hands of procotol is realized by dsp chip 130.
Utilize analog video decoder device chip Decoder that analog video signal/anolog TV signals CVBS/S-Video is decoded, export the digital luminance signal Y data of 8 ITU656 standard digital brightness signal Y 4:2:2 forms, directly deliver to the video/audio input/output interface (VP) of dsp chip 130, analog video decoder chip (Decoder) 110 carried out the initialization setting of chip by total line traffic control (I2C) by dsp chip 130.
Utilize 120 couples of computer VGA of modulus conversion chip (ADC) interface vision signal to carry out analog-to-digital conversion, export digital rgb signal and capable, the clock signal of 3 road 8bits, directly deliver to the input port of fpga chip 210.Modulus conversion chip (ADC) 120 carried out the initialization setting of chip by total line traffic control (I2C) by dsp chip 130.
Referring to Fig. 2, video signal processing module 200 realizes that by fpga chip 210 functional module of its realization has: detection (detective) module 230, identification (recognition) module 220, chrominance space are changed (rgb2y) module 210, brightness enhancement algorithms (y_magnify) module 240, the deposit data of going reorders 250 5 submodules of (resort) module.Directly be transferred to the video/audio input/output interface (VP) of dsp chip 130 by the Y data after fpga chip 210 processing, and be stored in respectively in dsp chip 130 corresponding first memory spaces (capChaAYSpace), second memory space (vgaYBuffer1), the 3rd memory space (vgaYBuffer2).
Detect (detective) module 230 and realize that the computer interface plug detects, unexpected detection of power loss.When detection had the signal input less than computer interface, output valid signal was put low.
Identification (recognition) module 220 is used for the standard of detection computations machine interface input signal, internal register vcount zero clearing when detecting field synchronization leader will, vcount=vcount+1 when beginning count detection to the row synchronous head.When detecting field synchronization leader will, vtotal=vcount.Judge the standard of input signal according to the numerical value of vtotal.
500＜vtotal＜550 o'clock mode_rec output 001 is the input of vga signal.
600＜vtotal＜650 o'clock mode_rec output 010 is the input of svga signal.
780＜vtotal＜820 o'clock mode_rec output 011 is the input of xga signal.
1030＜vtotal＜1090 o'clock mode_rec output 100 is the input of sxga signal.
The function of chrominance space conversion (rgb2y) module 210 is that the digital rgb signal is transferred to digital luminance signal Y, realizes chrominance space conversion: Y=0.299*R+0.587*G+0.114*B.Extract luminance signal and gather through dsp chip 130, extract gray level image at host computer, Y is a luminance signal.
The function of brightness enhancement algorithms (y_magnify) module 240 is to realize that brightness strengthens, and adopts respective algorithms to realize that the contrast of image strengthens according to picture feature.
Reorder (resort) module 250 of row deposit data reduces high-speed sampling and the processing of data frequency to satisfy dsp chip 130) function realizes that row is deposited, data rearrangement, frequency reducing.Input resolution reaches SXGA (1280*1024), and clock rate is up to 108MHz after modulus conversion chip (ADC) 120 decodings.Can only support 80MHz but the VP clock rate of dsp chip 130 is the highest.Therefore must lower clock frequency.Adopt 16 these characteristics of YC pattern in conjunction with capture program, eight Y data after changing to digital luminance signal Y chrominance space through the digital rgb signal are lined up 16 export to dsp chip 130 again, clock rate just can be reduced to original half like this.Model 8 bit data collections are no problem routinely theoretically, but frame data for SXGA (1280*1024) resolution, the Dot Clock frequency reaches the highest frequency acquisition 80MHZ of video/audio input/output interface (VP) that 108MHZ is higher than dsp chip 130, the video of being gathered for head it off and unlikely dsp chip 130 has dislocation phenomenon, has proposed following method for designing:
8 brightness signal Y of video flowing are write the capable the inside of depositing after the chrominance space modular converter comes out.Row deposit A write full after, the next line data are then write toward going to deposit in the B if begin to arrive.Starting the A data simultaneously sends toward dsp chip 130.The bit wide that sends data flow is 16, and corresponding clock is dclk_div2.Send after the data among the A, B just in time writes full, and conversion sends the storage relation again---switch to B from A.So move in circles, just can finish the work of frequency reducing.Be in order to utilize the advantage of buffer memory like this: can be placed on fpga chip 210 the insides to ordering work and finish by hardware.16 bit data are input to the video/audio input/output interface (VP) of dsp chip 130, comprise video/audio input/output interface 1 (VP1) and video/audio input/output interface 2 (VP2).Video/audio input/output interface 0 (VP0) keeps for the ITU656 video data of decoder output to use.Resulting data result is, the buffer data that dsp chip 130 collects need not sort and just be following order: the resolution of supposing input video is 1280*1024, the least-significant byte data are input to video/audio input/output interface 1 (VP1), dsp chip 130 collects Y1buffer district Y1, Y2, Y3, Y4, Y5 ... Y640; The most-significant byte data are input to video/audio input/output interface 2 (VP2), and dsp chip 130 collects Y2buffer district Y641, Y642, and Y643, Y644, Y645 ... Y1280; So do not need to go to adjust the order of brightness signal Y data taking dsp chip 130 resources, can directly be linked into an Ethernet bag and send.Could realize that like this dsp chip 130 sends the purpose of high-resolution video in real time.
Utilize advantage recited above, obviously requirement is deposited when the video/audio input/output interface (VP) of dsp chip 130 is sent out data from fpga chip 210 row and is wanted elder generation reasonable the sending order arrangement.Need to solve following problem in the implementation procedure: with respect to the row synchronous head, when begin deposit data, when begin to send data to port, when dsp chip 130 programs from beginning to adopt data.These three problems are correlated with.
In the actual exploitation, will regulate at first that dsp chip 130 begins to gather and FIFO begins dateout and matches, it is more and more littler that the process of Tiao Zhenging can find to misfit the hangover (later half district) that causes gradually.To adjust the moment that FIFO begins deposit data then, make capture area cover the zone of available point just, can find in the adjustment process that the first black surround of row is more and more littler.Dsp chip 130 begins to gather and FIFO begins dateout and fixes one earlier.In case the unanimity of adjusting will be constant to all resolution.Because FIFO begins deposit data along with standard changes, this just requires fpga chip 210 at first can discern the standard of input automatically.
Video acquisition device can be by button to gathering the selection of input command and standard.Press under the key control the video acquisition device integral reset at SW2.Button switches the control module of shaking hands with procotol, the keyboard input controller (DM642_KEY) and the button that comprise expansion, the keyboard input controller (DM642_KEY) of expansion (0x90080068) reflects button operation, selects computer access, pickup camera passage according to button; Select, control the selection of analog video signal (CVBS) standard by key control computing mechanism formula.Procotol is controlled at data packets transmitted in the Ethernet, must follow unified format.Ethernet frame format commonly used is an Ethernet II type.At first initiate link (LINK) bag by host computer (server), give in the network and initiate broadcast packet, video acquisition device detects the bag in the network, judges whether link (LINK) bag of initiating into host computer according to corresponding check digit.Video acquisition device therefrom extracts SN sequence number and the MAC Address that host computer distributes to video acquisition device after receiving correct link (LINK) bag.The data acquisition of video acquisition device is finished, and register is finished and gathered the mark position height.Video acquisition device sends protocol package, comprises the video information of collection in the protocol package, comprises video formats, frame number, resolution.Host computer is judged check digit response protocol bag, and the operation of next frame is selected in the concurrent order of losing one's life: the selection of retransmission flag resend, passage and standard, reseting mark.
Network control module (control module) 300 is made up of ethernet control chip (EMAC) 140 (10/100Mb/s Ethernet MAC) and data management interface (MDIO) (Management DataInput/0utput) two parts.Wherein ethernet control chip (EMAC) 140 is the network data passage, and data management interface (MDIO) is the state and the control interface of ethernet control chip (EMAC) 140.In network control module (control module) 300, exist a configuration register (descriptor memory).Per 4 word lengths of this piece configuration register (descriptor memory) are as a descriptor (descriptor), and descriptor is the data structure that is used for describing an Ethernet bag (packet) in the internal memory.Application program sends as submitting to an Ethernet bag (packet), then need to apply for a descriptor (descriptor), concrete conditions such as size according to this Ethernet bag (packet) are filled corresponding description entry, add then in descriptor (descriptor) transmit queue that is suspended to ethernet control chip (EMAC) 140.Ethernet control chip (EMAC) 140 will be handled current one after sending the corresponding Ethernet bag (packet) of a descriptor (descriptor) automatically, till formation is sky.
Referring to Fig. 3, host computer (server) terminal interaction module realizes communicating by letter of 300 of network control modules in host computer and the video acquisition device, and can show the video data that receives in real time, the video format that simultaneously all right Control Network control module 300 is gathered, and with specific form stored video data.Communicating by letter between host computer and the network control module 300 used udp protocol, and utilize multithreading to realize real time data processing in the network service, comprise the broadcasting thread, reply thread, receiving thread, display image thread, data statistics thread, storage thread and data transaction thread.Host computer is created above-mentioned each thread immediately after starting, broadcast thread then and just begin to send link (LINK) bag to network.After receiving thread receives the response of network video collecting device to broadcast packet, host computer will suspend the broadcasting thread, and begin to have the SN sequence number of this device and the link bag of mac address information to the network video collecting device transmission by replying thread.After receiving thread receives the protocol package that harvester sends over, this thread will be analyzed information such as the standard, frame number, resolution of the video in this protocol package, dispose accordingly; And, will select corresponding response packet form according to the form of protocol package: the selection of retransmission flag resend, passage and standard, reseting mark etc., and reply by replying thread.After receiving thread receives corresponding video data, will notify the display image thread that the associated picture data are shown, utilize the storage threads store to receive data accordingly simultaneously as required.The data transaction thread can realize receiving the conversion of data type, and the data statistics thread will be added up related data information in the whole receiving course.
Video acquisition device adopts the FLASH bootstrapping that powers on, and is after system's operation, first to dsp chip 130 hardware initialization, interrupt vector initialization, ethernet control chip (EMAC) 140 initialization.The configuration to ethernet control chip (EMAC) 140 is mainly finished in ethernet control chip (EMAC) 140 initialization, initialization data buffering area, packet, state area are provided with the configuration structure of ethernet control chip (EMAC) 140 and open ethernet control chip (EMAC) 140 resources.Disable interrupts, wait for that host computer sends link (LINK) bag, trial connects, what this moment, receiving terminal did not stop sends link (LINK) bag to network, after video acquisition device receives this link (LINK) bag, extract in link (LINK) bag ip address, initial acquisition channel selecting and the system flag bit of warm reset whether of distributing to sequence number, the host computer of network video collecting device by host computer, and send a link (LINK) to host computer and wrap the response that has received and wrap and notify video acquisition device to stop to send broadcast packet.If system restarts after the warm reset to attempt connecting, then extract corresponding key information in link (LINK) bag, finish standard initialization to VGA interface vision signal and the input of analog video signal CVBS interface; If connect for the first time, the then manual input operation of finishing button.Carry out the I2C bus initialization, by I2C bus initialization analog video decoder chip and modulus conversion chip.
Open video/audio input/output interface 0 (VP0), the video that is set to the BT656 form is finished analog video signal CVBS interface collection of video signal; Open video/audio input/output interface 1 (VP1), be set to the last hemistich that 16 YC patterns are gathered VGA interface vision signal; Open video/audio input/output interface 2 (VP2), be set to the following hemistich that 16 YC patterns are gathered VGA interface vision signal, the beginning can each video/audio input/output interface (VP).According to " initial acquisition channel selecting " position that extracts, judge that next step carries out that input channel video information collection.
Enter into VGA interface collection of video signal and send circulation if this position is 1, the state that carries out is gathered in elder generation's inquiry, and the operation a downwards if image frame grabber is finished is carried out state otherwise continue to inquire about to gather.GPIO interface by dsp chip 130 reads VGA interface vision signal and whether effectively indicates the valid value, if it is invalid that valid=0 then imports this moment, the valid value is read in circulation after waiting for certain hour, up to the valid value is 1 o'clock, network video collecting device sends a reset packet to host computer, the sequence number that comprises this device in this reset packet, the ip address of host computer, and button is to VGA interface vision signal and analog video signal CVBS interface input standard initialization information, harvester carries out warm reset, after receiving reset packet, extracts receiving terminal useful information, again send link (LINK) bag to this device, comprise the initialization information that from reset packet, extracts in this link (LINK) bag, so just avoided manual once more the sequence number of receiving terminal to it, the input of information such as the ip address of host computer, on this device, also avoid using button once more to the selection of VGA interface vision signal and analog video signal CVBS standard, reduced manual intervention; If valid=1 then carries out downwards, hold consultation with host computer, do the preparation of reception, according to the sequence number and the host computer ip that distribute, and image information is filled negotiated packet, populated back sends negotiated packet to host computer, host computer receives after the negotiated packet to send it back to harvester and answers negotiated packet to finish to shake hands, comprise that in responding negotiated packet next frame is gathered VGA interface vision signal or analog video signal CVBS selects information such as position, harvester receives the command word of consulting to return after response is wrapped host computer, stay the next transmission that is not responded to interrupt simultaneously, if consult overtime then negotiation again, from the host computer command word of returning, extract the next frame relevant information, the transmission that is not responded that permission stays is above interrupted sending the interruption application to cpu, begin to send, host computer receives the storage of general data bag, turns back to judgement " acquisition channel selection " position after sending a two field picture once more, carries out circle collection and sends.
When " acquisition channel selection " position is 0, enter into the collection and transmission circulation of analog video signal CVBS, at first judge whether be arranged in first this moment, if after then waiting for certain hour, judge once more, otherwise carry out the state that inquiry collection is carried out downwards, continue inquiry collection if an image frame grabber is not finished and carry out state, otherwise hold consultation with host computer, ensuing other operating procedure is the same with the operation of VGA interface channel video signal.
Above content is to further describing that the present invention did in conjunction with concrete preferred implementation; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of being submitted to.
Claims (7)
1, based on the network real-time video collecting apparatus of fpga chip and dsp chip exploitation, it is characterized in that: this network real-time video collecting apparatus comprises that video acquisition module (100), video signal processing module (200), network control module (300), button switch and the shake hands control module and the host computer terminal interaction module of procotol; Video acquisition module (100) is used to gather vision signal; Video signal processing module (200) is used for vision signal and handles; Network control module (300) is used for Control Network; Button switches and the control module of shaking hands of procotol is used to control computer standard or analog video signal standard; Host computer terminal interaction module is used to realize communicate by letter, show in real time the video data that receives, video format, the stored video data that Control Network control module (300) is gathered between host computer and network control module (300); Vision signal by camera or the input of computer VGA interface, convert the digital rgb signal to through video acquisition module (100), by video signal processing module (200) digital rgb signal is carried out chrominance space conversion, down conversion process and data rearrangement, again brightness signal Y is delivered to dsp chip (130), through passing through external network control chip (310) transmission video data to host computer by dsp chip (130) according to the request and the procotol of host computer after the storage of outside SDRAM.
2, network real-time video collecting apparatus based on fpga chip and dsp chip exploitation according to claim 1, it is characterized in that: described video acquisition module (100) comprises analog video decoder chip (110), video/audio input/output interface and modulus conversion chip (120), analog video decoder chip (110) and modulus conversion chip (120) are carried out the initialization setting of chip by total line traffic control by dsp chip (130), analog video decoder chip (110) is gathered analog video signal and analog video signal is converted to digital luminance signal Y, modulus conversion chip collecting computer signal also is converted to the digital rgb signal with Computer signal, and digital luminance signal Y directly delivers to dsp chip (130).
3, network real-time video collecting apparatus based on fpga chip and dsp chip exploitation according to claim 1, it is characterized in that: described video signal processing module (200) is by detection module (230), identification module (220), chrominance space modular converter (210), brightness enhancement algorithms module (240) and the row deposit data module (250) that reorders constitutes, the digital rgb signal is after module (230) detects after testing, detect the standard of input Computer signal by identification module (220), realize of the chrominance space conversion of digital rgb signal by chrominance space modular converter (210) then to digital luminance signal Y, realize that by brightness enhancement algorithms module (240) contrast to input picture strengthens and brightness strengthens again, by module (250) realization of reordering of row deposit data data line is deposited control at last, data rearrangement, clock two divided-frequency and down conversion process.
4, the network real-time video collecting apparatus based on fpga chip and dsp chip exploitation according to claim 3, it is characterized in that: described detection module (230) detects the stability of input Computer signal, comprises that the computer interface plug detects and unexpected detection of power loss; Described identification module (220) detects the standard of input Computer signal; Described chrominance space modular converter (210) is realized the chrominance space conversion of digital rgb signal to digital luminance signal Y; Described brightness enhancement algorithms module (240) realizes the contrast of input picture is strengthened and the brightness enhancing; The module (250) that reorders described capable deposit data realizes data line is deposited control, data rearrangement, clock two divided-frequency and down conversion process, adopts two row to deposit into road wheel stream and sends and storage, and original 8 brightness signal Y are expanded to 16 brightness signal Y outputs.
5, the network real-time video collecting apparatus based on fpga chip and dsp chip exploitation according to claim 1, it is characterized in that: described network control module (300), form by ethernet control chip (140) and data management interface two parts, wherein ethernet control chip (140) is the network data passage, data management interface is the state and the control interface of ethernet control chip (140), comprises a configuration register in network control module (300).
6, the network real-time video collecting apparatus based on fpga chip and dsp chip exploitation according to claim 1, it is characterized in that: described button switches the control module of shaking hands with procotol, the keyboard input controller and the button that comprise expansion are by key control computing mechanism formula or control analog video signal standard.
7, the network real-time video collecting apparatus based on fpga chip and dsp chip exploitation according to claim 1, it is characterized in that: in the described host computer terminal interaction module, communicating by letter between host computer and the network control module (300) used udp protocol, and utilize multithreading to realize real time data processing in the network service, comprise the broadcasting thread, reply thread, receiving thread, display image thread, data statistics thread, storage thread and data transaction thread.
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| CN102186011A (en) * | 2011-05-13 | 2011-09-14 | 合肥埃科光电科技有限公司 | Digital high-definition camera based on full hardware |
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2008
- 2008-12-30 CN CN2008102365387A patent/CN101478670B/en not_active Expired - Fee Related
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| CN101651828B (en) * | 2009-09-07 | 2011-03-30 | 哈尔滨工程大学科技园发展有限公司 | Radar image collection card based on DSP and FPGA |
| CN102567280B (en) * | 2010-12-17 | 2015-01-21 | 西安奇维科技股份有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
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| CN102989121B (en) * | 2012-11-23 | 2015-06-24 | 安徽寰智信息科技股份有限公司 | Action recognition-based Alzheimer's disease preventing and rehabilitation training system |
| CN103096035B (en) * | 2012-12-27 | 2017-02-15 | 潮州响石智能技术有限公司 | Monitor with video optimization function |
| CN103096035A (en) * | 2012-12-27 | 2013-05-08 | 广东响石数码科技有限公司 | Monitor with video optimization function |
| CN103353725A (en) * | 2013-03-19 | 2013-10-16 | 中国科学院声学研究所 | PCI interface protocol based array expandable data collection system realized by adopting FPGA (field programmable gate array) |
| CN103647902A (en) * | 2013-12-25 | 2014-03-19 | 广州中国科学院软件应用技术研究所 | Video image processing method, video image processing device and video image processing system |
| CN110740478A (en) * | 2018-07-18 | 2020-01-31 | 成都鼎桥通信技术有限公司 | Video resolution negotiation method and device |
| CN110231295A (en) * | 2019-06-28 | 2019-09-13 | 中国计量大学 | A kind of image acquisition and processing system of portable colloidal gold CCD readout instrument |
| CN110266961A (en) * | 2019-07-23 | 2019-09-20 | 江苏鼎速网络科技有限公司 | Image generating method, system and image forming apparatus |
| CN112305961A (en) * | 2020-10-19 | 2021-02-02 | 武汉大学 | Novel signal detection and acquisition equipment |
| CN114125343A (en) * | 2021-11-30 | 2022-03-01 | 成都逐飞智能设备有限公司 | Video storage module based on singlechip |
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