CN101030587A - Pixel structure and its production - Google Patents
Pixel structure and its production Download PDFInfo
- Publication number
- CN101030587A CN101030587A CN 200710091389 CN200710091389A CN101030587A CN 101030587 A CN101030587 A CN 101030587A CN 200710091389 CN200710091389 CN 200710091389 CN 200710091389 A CN200710091389 A CN 200710091389A CN 101030587 A CN101030587 A CN 101030587A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- pattern dielectric
- electrode
- patterned semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention is concerned with pixel structures and its production. The said pixel structures is on base plant and relates to grid, pattern dielectric layer, pattern metal layer, flatness layer and transparent pixel pole. Grid and pattern dielectric layer covering the grid both set on base plant. The pattern semiconductor layer on the pattern dielectric layer relates to channel layer on top of grid and some protruding blocks. The pattern metal layer relates to source, drain and reflecting pixel pole connecting with drain. Source and drain each cover part of channel layer and the reflecting pixel pole covers the protruding block. The grid, pattern dielectric layer, pattern semiconductor layer and pattern metal layer make of transistor, while the flatness layer on transistor uncovers part of touching window of the reflecting pixel pole. The transparent pixel pole on flatness layer connects with reflecting pixel pole through touching window. The produced pixel structures can use the gap of the single LC cell to make half penetrating and half reflecting LCD.
Description
Technical field
The invention relates to a kind of dot structure and manufacture method thereof, particularly relevant for a kind of dot structure and manufacture method thereof with reflecting electrode.
Background technology
Universalness along with LCD, many portable type electronic products also little by little improve for the requirement of the Presentation Function of LCD, particularly portable type electronic product for example mobile phone (mobilephone), personal digital assistant (Personal Digital Assistant, PDA) or palmtop computer (PocketPC) etc.These portable type electronic products not only have good picture display effect at indoor needs, also need keep suitable picture quality simultaneously under outdoor or the environment of high light.
Therefore, how to allow LCD under the environment of high light, possess good display quality, just become one of the important trend of the technical development of LCD.For these reasons, prior art develops and a kind of semi-penetrated semi-reflected liquid crystal display (transflective LCD), and this semi-penetrated semi-reflected liquid crystal display is out of doors under the bright light environments and have display effect clearly under the indoor environment equally.
In existing semi-penetrated semi-reflected liquid crystal display, dot structure has and is suitable for the reflecting electrode of external light source reflection is constituted the echo area.The display effect that presents in order to make in the echo area can be consistent with the display effect that penetrating region presented that does not have reflecting electrode; usually can utilize a bed hedgehopping layer with the reflecting electrode bed hedgehopping, to form the semi-penetrated semi-reflected liquid crystal display in double liquid-crystal box gap (dual cell gap).In addition, also usually under reflecting electrode, dispose a plurality of photoresist projections (bump) in the existing dot structure, to promote the reflectivity of reflective pixel electrode.Yet reflecting electrode on bed hedgehopping layer, the bed hedgehopping layer and photoresist projection (bumps) are comparatively complicated on making, and expend cost.From the above, make the manufacturing technology steps of dot structure of semi-penetrated semi-reflected liquid crystal display simple, cheap can to take into account its quality again real in being difficult for for cost of manufacture.
Summary of the invention
The present invention provides a kind of dot structure, can use single liquid crystal box gap (single cell gap) technology, makes semi-penetrated semi-reflected liquid crystal display.
The present invention provides a kind of one pixel structure process method in addition, with under the prerequisite of simplifying processing step, makes reflectivity height and the preferable dot structure of quality.
The present invention proposes a kind of dot structure, is suitable for being disposed on the substrate (substrate).This dot structure comprises grid, pattern dielectric layer (patterned dielectric layer), patterned semiconductor layer, patterned metal layer, flatness layer (overcoat layer) and transparent pixels electrode (transparent pixelelectrode).Gate configuration is on substrate, and pattern dielectric layer is disposed on the substrate with cover gate.Patterned semiconductor layer is disposed on the pattern dielectric layer, and patterned semiconductor layer comprises channel layer and a plurality of projection that is disposed at the grid top.In addition, patterned metal layer comprises source electrode, drain electrode and the reflective pixel electrode that is connected with drain electrode, wherein source electrode and drain electrode cover the subregion of channel layer respectively, and reflective pixel electrode covers projection and grid, pattern dielectric layer, patterned semiconductor layer and patterned metal layer transistor formed.Flatness layer is disposed on the transistor, and wherein flatness layer has contact hole (contacthole), to expose the subregion of reflective pixel electrode.The transparent pixels electrode is disposed on the flatness layer, and is electrically connected (electrically connect) with reflective pixel electrode by contact hole.
In one embodiment of this invention, the superiors of above-mentioned patterned semiconductor layer, available deposition or doping way form an ohmic contact layer, and wherein ohmic contact layer is disposed between source electrode and the channel layer and between drain electrode and the channel layer, in order to form a thin-film transistor.
In one embodiment of this invention, pattern dielectric layer has identical pattern with patterned semiconductor layer, and pattern dielectric layer is between substrate and patterned semiconductor layer.
In one embodiment of this invention, be not patterned the pattern dielectric layer that semiconductor layer covers and have one first thickness, and the pattern dielectric layer that patterned semiconductor layer covered has one second thickness.First thickness for example be less than or equal second thickness.
In one embodiment of this invention, above-mentioned pattern dielectric layer only is distributed between patterned semiconductor layer and the substrate.
In one embodiment of this invention, dot structure also comprises protective layer, is disposed between flatness layer and the transistor.
In one embodiment of this invention, the dielectric coefficient of above-mentioned flatness layer for example is 2 to 7, and the thickness of flatness layer for example is to be 0.5 micron to 6 microns.
In one embodiment of this invention, the pattern dielectric layer of above-mentioned projection and this projection below is defined as projection, and the thickness of projection is 0.1 micron to 1.5 microns.
In one embodiment of this invention, dot structure also comprises the common electrode wire that is disposed on the substrate, and wherein common electrode wire constitutes storage capacitors with the reflective pixel electrode that is positioned at its top.
The present invention proposes a kind of one pixel structure process method in addition.At first, provide substrate, and form grid on substrate.Then, form pattern dielectric layer on substrate, and the pattern dielectric layer cover gate.Then, form patterned semiconductor layer on pattern dielectric layer, and patterned semiconductor layer comprises channel layer and a plurality of projection that is disposed at the grid top.Subsequently, form patterned metal layer on substrate, patterned metal layer comprises source electrode, drain electrode and the reflective pixel electrode that is connected with drain electrode.Source electrode and drain electrode cover the subregion of channel layer respectively, and reflective pixel electrode covers projection and grid, pattern dielectric layer, patterned semiconductor layer and patterned metal layer transistor formed.Afterwards, form flatness layer on transistor, and on flatness layer, make contact hole, to expose the subregion of reflective pixel electrode.Then, form the transparent pixels electrode on flatness layer, the transparent pixels electrode is electrically connected with reflective pixel electrode by contact hole.
In one embodiment of this invention, pattern dielectric layer has identical pattern with patterned semiconductor layer, and pattern dielectric layer is between substrate and patterned semiconductor layer.
In one embodiment of this invention, be not patterned the pattern dielectric layer that semiconductor layer covers and have one first thickness, and the pattern dielectric layer that patterned semiconductor layer covered has one second thickness.First thickness for example be less than or equal second thickness.
In one embodiment of this invention, above-mentioned pattern dielectric layer only is distributed between patterned semiconductor layer and the substrate.
In one embodiment of this invention, after the above-mentioned formation patterned metal layer, also comprise forming protective layer with covering transistor.
In one embodiment of this invention, the dielectric coefficient of above-mentioned flatness layer is 2 to 7, and its thickness for example is to be 0.5 micron to 6 microns.
In one embodiment of this invention, the pattern dielectric layer of above-mentioned projection and this projection below is defined as projection, and the thickness of projection is 0.1 micron to 1.5 microns.
In one embodiment of this invention, when forming grid, also comprise forming common electrode wire on substrate, and common electrode wire constitutes storage capacitors with the reflective pixel electrode that is positioned at its top.
In the one pixel structure process method of the present invention, when forming patterned semiconductor layer, form a plurality of projections and reflective pixel electrode is covered on the projection,, the reflectivity of reflective pixel electrode is improved by control projection angle and thickness.In addition, in the dot structure of the present invention, flatness layer can be covered on the reflecting electrode, to adjust the electric field of reflective pixel electrode top, and then make the semitransparent and half-reflective liquid crystal display of using this dot structure when the demonstration of pattern of penetrating and reflective-mode, have identical display effect.
Description of drawings
Figure 1A to Fig. 1 E be one embodiment of the invention dot structure manufacturing process on look schematic diagram.
Fig. 2 A is respectively the profile that hatching line AA ', hatching line BB ' along Figure 1A to Fig. 1 E and hatching line CC ' are illustrated to Fig. 2 E.
Fig. 3 A is the three-dimensional structure diagram of the liquid crystal panel of one embodiment of the invention.
Fig. 3 B is the three-dimensional structure diagram of the liquid crystal panel of another embodiment of the present invention.
Drawing reference numeral
100,312: dot structure
100a: echo area
100b: penetrating region
110: substrate
120: grid
122: common electrode wire
124: scan line
126: the drive circuit connection gasket
130: pattern dielectric layer
140: patterned semiconductor layer
142: channel layer
142a, 144a: ohmic contact layer
144: projection
150: patterned metal layer
152: source electrode
154: drain electrode
156: reflective pixel electrode
158: data wire
160: transistor
172: protective layer
174: flatness layer
176: contact hole
180: the transparent pixels electrode
300A, 300B: liquid crystal panel
310A, 310B: first substrate
320: the second substrates
330: liquid crystal layer
Embodiment
In general, in dot structure, dispose reflective pixel electrode, this dot structure had make the ability of light reflection, if in dot structure, dispose the zone outside the reflective pixel electrode simultaneously, configuration transparent pixels electrode, then this dot structure display mode that can have penetrating simultaneously and reflect.By the description of prior art as can be known; desire to make this type of dot structure to have good quality; usually can in dot structure, make the bed hedgehopping layer of reflective pixel electrode bed hedgehopping and the photoresist projection that improves reflectivity; but this practice will cause the making flow process of dot structure to become numerous and diverse, make output and product yield descend.For this reason, the present invention proposes a kind of one pixel structure process method, with under the prerequisite that can simplify process complexity, makes the good dot structure of quality.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Figure 1A is the top view of the one pixel structure process method of one embodiment of the invention to Fig. 1 E, and Fig. 2 A is respectively the profile that hatching line AA ', hatching line BB ' along Figure 1A to Fig. 1 E and hatching line CC ' are painted to Fig. 2 E.Please, provide substrate 110, and on substrate 110, form grid 120 earlier simultaneously with reference to Figure 1A and Fig. 2 A.The mode that forms grid 120 for example is to form gate material layers (not illustrating) on substrate 110 with sputtering technology, subsequently by etching technics with gate material layers (not illustrating) patterning, to form grid 120.In the step of patterning grid material layer (not illustrating), can on substrate 110, form common electrode wire 122, the scan line 124 that is connected with grid 120 and drive circuit connection gasket 126 simultaneously.
In the selection of material, substrate 110 can be transparent substrates such as glass substrate, plastic base, and the material of gate material layers (not illustrating) can be to be applied to any conductive material of grid 120 making or the combination of multiple conductive material in the technical field of the invention.For example, the material of gate material layers (not illustrating) for example is aluminium (Al), copper (Cu), molybdenum (Mo), silver (Ag), gold (Au), or alloy that these metals constituted or complex metal layer.
Then, please on substrate 110, form pattern dielectric layer 130 simultaneously with reference to Figure 1B and Fig. 2 B, and on pattern dielectric layer 130, form patterned semiconductor layer 140.At this moment, pattern dielectric layer 130 cover gate 120, and patterned semiconductor layer 140 comprises channel layer 142 and a plurality of projection 144 that is disposed at grid 120 tops.
In detail, the method for formation pattern dielectric layer 130 and patterned semiconductor layer 140 may further comprise the steps.At first, dielectric materials layer (not illustrating) is formed on the substrate 110, then semiconductor material layer is formed on the dielectric materials layer by another depositing operation by a depositing operation.In addition, the superiors of semi-conducting material are an ohmic contact layer, and its available deposition or doping way form.Then, carry out Patternized technique to remove partly dielectric materials layer and semiconductor material layer, for example, dielectric materials layer and semiconductor material layer can be removed simultaneously, to form pattern dielectric layer 130 and patterned semiconductor layer 140.Wherein, the material of pattern dielectric layer 130 for example is dielectric materials such as silicon dioxide, silicon nitride or silicon oxynitride, and the material of patterned semiconductor layer 140 for example is amorphous silicon or polysilicon.
In detail, after carrying out above-mentioned Patternized technique, can above grid 120, form channel layer 142 and ohmic contact layer 142a.In the present embodiment, the thickness of pattern dielectric layer 130 for example is 2500 dust to 5000 dusts or thinner, and the thickness of channel layer 142 for example is 500 dust to 2000 dusts or thinner, and the thickness of ohmic contact layer 142a for example is 200 dust to 700 dusts or thinner.
Specifically, when carrying out above-mentioned Patternized technique, for example be to carry out etching technics as shielding, to form patterned semiconductor layer 140 by a patterning photoresist.Then, utilize identical patterning photoresist or serve as that etching technics is proceeded in shielding, to form pattern dielectric layer 130 with patterned semiconductor layer 140.At this moment, pattern dielectric layer 130 has identical pattern with patterned semiconductor layer 140, and pattern dielectric layer 130 is between substrate 110 and patterned semiconductor layer 140.Therefore, shown in Fig. 2 B, the pattern dielectric layer 130 under projection 144 and the projection 144 for example can form projection.
In the middle of other embodiment, the number that can be removed with the control dielectric materials layer by the manufacturing conditions of adjusting Patternized technique.So, the pattern dielectric layer 130 that is covered by projection 144 can not have first thickness, and the pattern dielectric layer 130 that projection 144 is covered then has second thickness.Wherein, the missionary society of second thickness and first thickness influences the projection thickness variation.In brief, Tu Qi thickness is adjustable.In fact, Tu Qi thickness for example is 0.1 micron to 1.5 microns.In addition, the projection 144 or the side of projection and the angle of substrate 110 upper surfaces also can be adjusted at 5 ° to 45 ° by the control of Patternized technique.
Then, please on substrate 110, form patterned metal layer 150 simultaneously with reference to Fig. 1 C and Fig. 2 C.The mode that forms patterned metal layer 150 for example is to form metal level on substrate 110, and carries out Patternized technique with metal layer patternization.Patterned metal layer 150 comprise source electrode 152, the drain electrode 154 and with the drain electrode 154 reflective pixel electrodes that are connected 156, wherein source electrode 152 and drain electrode 154 cover the subregion of channel layer 142 respectively, and reflective pixel electrode 156 covers projection 144 (or projection), and ohmic contact layer 144a is between reflective pixel electrode 156 and projection 144.Simultaneously, when forming patterned metal layer 150, the part ohmic contact layer 142a that also can remove grid 120 tops is to expose the part channel layer 142 of grid 120 tops.At this moment, grid 120, pattern dielectric layer 130, patterned semiconductor layer 140 and patterned metal layer 150 meeting transistor formeds 160.In addition, when forming patterned metal layer 150, also can in same step, form the data wire 158 that is connected with source electrode 152.
In the present embodiment, patterned metal layer 150 can constitute reflective pixel electrode 156 with the ambient light line reflection.Simultaneously, patterned metal layer 150 covers the reflection efficiency that then helps to improve reflective pixel electrode 156 on the projection 144.In brief, among the present invention reflective pixel electrode 156 is covered on the projection 144 (or projection), can promotes the reflective surface area and the reflectivity of reflective pixel electrode 156.In addition, in the present embodiment, the angle of projection 144 (or projection) side and substrate 110 upper surfaces can be adjusted between 5 ° to 45 ° by technology controlling and process, so that reflective pixel electrode 156 has good reflectivity.In fact, the superiors' material of reflective pixel electrode 156 for example is silver (Ag), an aluminium (Al) or other has the electric conducting material of good reflection rate.
Form after the patterned metal layer 150, for example can on substrate 110, form a protective layer 172, so that transistor 160 is covered.The mode that forms protective layer 172 for example is to form dielectric film layers such as silicon dioxide, silicon nitride or silicon oxynitride with chemical vapor deposition method, with protective transistor 160, and makes it keep excellent electrical property.
Thereupon, please form flatness layer 174 on transistor 160 simultaneously with reference to Fig. 1 D and Fig. 2 D, and on flatness layer 174, make contact hole 176, to expose the subregion of reflective pixel electrode 156.The mode that forms flatness layer 174 for example is that the organic dielectric materials layer is coated on the transistor 160, and utilize little shadow (photolithography) technology with form flatness layer 174 with and on contact hole 176.For instance, organic dielectric materials for example is acryl resin or photoresist material etc.In fact, the dielectric coefficient of flatness layer 174 for example is 2 to 7, and its thickness for example is 0.5 micron to 6 microns.
Then, please form transparent pixels electrode 180 on flatness layer 174 simultaneously with reference to Fig. 1 E and Fig. 2 E, wherein transparent pixels electrode 180 is electrically connected with reflective pixel electrode 174 by contact hole 176.The generation type of transparent pixels electrode 180 can be to form electrically conducting transparent materials such as indium tin oxide or indium-zinc oxide on flatness layer 174, and with electrically conducting transparent material patterning to form transparent pixels electrode 180.
At this moment, the dot structure 100 that is disposed on the substrate 110 comprises grid 120, pattern dielectric layer 130, patterned semiconductor layer 140, patterned metal layer 150, flatness layer 174 and transparent pixels electrode 180.Grid 120 is disposed on the substrate 110, and pattern dielectric layer 130 is disposed on the substrate 110 with cover gate 120.Patterned semiconductor layer 140 is disposed on the pattern dielectric layer 130.Patterned semiconductor layer 140 comprises channel layer 142 and a plurality of projection 144 that is disposed at grid 120 tops.In addition, patterned metal layer 150 comprise source electrode 152, the drain electrode 154 and with the drain electrode 154 reflective pixel electrodes that are connected 156, wherein source electrode 152 and drain electrode 154 cover the subregion of channel layer 142 respectively, and reflective pixel electrode 156 covers projection 144 (or projection), and grid 120, pattern dielectric layer 130, patterned semiconductor layer 140 and patterned metal layer 150 transistor formeds 160.Flatness layer 174 is disposed on the transistor 160, and wherein flatness layer 174 has contact hole 176, to expose the subregion of reflective pixel electrode 156.Transparent pixels electrode 180 is disposed on the flatness layer 174, and is electrically connected with reflective pixel electrode 156 by contact hole 176.
By Fig. 1 E as can be known, dot structure 100 has allows the transparent pixels electrode 180 of light penetration and with the reflective pixel electrode 156 of light reflection, and two kinds of pixel electrodes 156,180 are electrically connected to each other by contact hole 176.Therefore, dot structure 100 is a transflective pixel structure.In dot structure 100, flatness layer 174 can influence the electric field of reflective pixel electrode 156 tops, makes that the electric field of reflective pixel electrode 156 tops is different with the electric field of transparent pixels electrode 180 tops.Therefore, dot structure 100 is applied on the LCD, then can makes the reflective display region at reflective pixel electrode 156 places and the viewing area that penetrates at transparent pixels electrode 180 places present roughly the same display effect by the thickness adjustment of flatness layer 174.In other words, when dot structure 100 is applied to semi-penetrated semi-reflected liquid crystal display, be not easy to penetrate the unbalanced phenomenon of display frame between viewing area and the reflective display region.
At present, mostly the design of most semi-penetrated semi-reflected liquid crystal display is to adopt the configuration of bed hedgehopping layer, forms double liquid-crystal box gap (dual cell gap), so that penetrate display frame uniformity between viewing area and the reflective display region.In comparison, the design of dot structure 100 of the present invention, can be by adjusting flatness layer thickness or material (dielectric coefficient), under single cel-gap (single cell gap) structure, reach and penetrate display frame uniformity between viewing area and the reflective display region, therefore the manufacturing process of dot structure 100 is comparatively simple, and manufacturing cost is also comparatively cheap.Further say, in the existing semi-penetrated semi-reflected liquid crystal display with double liquid-crystal box gap, edge at the bed hedgehopping layer, the ordered state of liquid crystal molecule is not easy to be controlled, there is the phenomenon of light leak to produce easily, and then makes the display quality of semi-penetrated semi-reflected liquid crystal display glide.Relatively, because the dot structure 100 of present embodiment has single cel-gap, therefore be difficult for having the phenomenon of light leak to produce.
In addition, Fig. 3 A and Fig. 3 B illustrate the three-dimensional structure diagram of the liquid crystal panel of two kinds of embodiment of the present invention.Please earlier with reference to Fig. 3 A, liquid crystal panel 300A comprises the first substrate 310A, second substrate 320 and liquid crystal layer 330.Wherein, the first substrate 310A comprises the described dot structure 100 of the foregoing description of a plurality of arrayed, and second substrate 320 and the first substrate 310A subtend are provided with.330 of liquid crystal layers are arranged between the first substrate 310A and second substrate 320.
What deserves to be mentioned is that each dot structure 100 has an echo area 100a and a penetrating region 100b.Please be simultaneously with reference to Fig. 1 E and Fig. 3 A, the dot structure 100 of present embodiment for example is a transflective pixel structure 100, wherein reflective pixel electrode 156 is positioned at echo area 100a and transparent pixels electrode 180 is positioned at penetrating region 100b.
On the other hand, among the liquid crystal panel 300B, the dot structure 312 of the first substrate 310B can be a reflective pixel structure (as the dot structure 312 of Fig. 3 B).In detail, in the dot structure 312, reflective pixel electrode can be distributed in the whole viewing area.
In sum, dot structure of the present invention and manufacture method thereof have the advantage of the following stated at least:
1. in the dot structure of the present invention, projection is to utilize that existing rete is made in the transistor, and therefore the making of projection need not increase extra processing step.
2. in the dot structure of the present invention, the thickness and the external form of projection can change by control of process condition, and then improve the reflectivity that is covered in the reflective pixel electrode on the projection more efficiently.
3. dot structure of the present invention has single cel-gap, so be difficult for having the phenomenon of light leak to produce.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (20)
1. a dot structure is suitable for being disposed on the substrate, it is characterized in that, described dot structure comprises:
One grid is disposed on the described substrate;
One pattern dielectric layer is disposed on the described substrate to cover described grid;
One patterned semiconductor layer is disposed on the described pattern dielectric layer, and described patterned semiconductor layer comprises that one is disposed at channel layer and a plurality of projection of described grid top;
One patterned metal layer, comprise one source pole, a drain electrode and a reflective pixel electrode that is connected with this drain electrode, wherein said source electrode and described drain electrode cover the subregion of described channel layer respectively, and described reflective pixel electrode covers described these projections, and described grid, described pattern dielectric layer, described patterned semiconductor layer, described source electrode and described drain electrode constitute a transistor;
One flatness layer is disposed on the described transistor, and wherein said flatness layer has a contact hole, to expose the subregion of described reflective pixel electrode; And
One transparent pixels electrode is disposed on the described flatness layer, and is electrically connected with described reflective pixel electrode by described contact hole.
2. dot structure according to claim 1 is characterized in that wherein said patterned semiconductor layer also comprises an ohmic contact layer, is disposed between described source electrode and the described channel layer and between described drain electrode and the described channel layer.
3. dot structure according to claim 1, it is characterized in that, wherein said pattern dielectric layer has identical pattern with described patterned semiconductor layer, and described pattern dielectric layer is between described substrate and described patterned semiconductor layer.
4. dot structure according to claim 1, it is characterized in that, wherein do not had one first thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and had one second thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and described first thickness is less than or equal to described second thickness.
5. dot structure according to claim 1 is characterized in that, wherein said pattern dielectric layer only is distributed between described patterned semiconductor layer and the described substrate.
6. dot structure according to claim 1 is characterized in that described dot structure also comprises a protective layer, is disposed between described flatness layer and the described transistor.
7. dot structure according to claim 1 is characterized in that the dielectric coefficient of wherein said flatness layer is about 2 to 7.
8. dot structure according to claim 1 is characterized in that, the thickness of wherein said flatness layer is about 0.5 micron to 6 microns.
9. dot structure according to claim 1 is characterized in that, the described pattern dielectric layer under wherein said projection and this projection forms a projection, and the thickness of described projection is about 0.1 micron to 1.5 microns.
10. dot structure according to claim 1, it is characterized in that, described dot structure comprises that also one is disposed at the common electrode wire on the described substrate, and wherein said common electrode wire constitutes a storage capacitors with the described reflective pixel electrode that is positioned at its top.
11. an one pixel structure process method is characterized in that, described one pixel structure process method comprises:
One substrate is provided;
Form a grid on described substrate;
Form a pattern dielectric layer on described substrate, and described pattern dielectric layer covers described grid;
Form a patterned semiconductor layer on described pattern dielectric layer, and described patterned semiconductor layer comprises that one is disposed at channel layer and a plurality of projection of described grid top;
Form a patterned metal layer on described substrate, described patterned metal layer comprises one source pole, a drain electrode and a reflective pixel electrode that is connected with described drain electrode, wherein said source electrode and described drain electrode cover the subregion of described channel layer respectively, and described reflective pixel electrode covers described these projections, and described grid, described pattern dielectric layer, described patterned semiconductor layer, described source electrode and described drain electrode constitute a transistor;
Form a flatness layer on described transistor;
On described flatness layer, make a contact hole, to expose the subregion of described reflective pixel electrode; And
Form a transparent pixels electrode on described flatness layer, described transparent pixels electrode is electrically connected with described reflective pixel electrode by described contact hole.
12. one pixel structure process method according to claim 11, it is characterized in that, the step that wherein forms described patterned semiconductor layer comprises and forms a semi-conductor layer and an ohmic contact layer in regular turn, and wherein said ohmic contact layer is disposed between described source electrode and the described channel layer and between described drain electrode and the described channel layer.
13. one pixel structure process method according to claim 11, it is characterized in that, wherein said pattern dielectric layer has identical pattern with described patterned semiconductor layer, and described pattern dielectric layer is between described substrate and described patterned semiconductor layer.
14. one pixel structure process method according to claim 11, it is characterized in that, do not had one first thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and had one second thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and described first thickness is less than or equal to described second thickness.
15. one pixel structure process method according to claim 11 is characterized in that, wherein said pattern dielectric layer only is distributed between described patterned semiconductor layer and the described substrate.
16. one pixel structure process method according to claim 11 is characterized in that, wherein forms after the described patterned metal layer, also comprises forming a protective layer to cover described transistor.
17. one pixel structure process method according to claim 11 is characterized in that, the thickness of wherein said flatness layer is about 0.5 micron to 6 microns.
18. one pixel structure process method according to claim 11 is characterized in that, the described pattern dielectric layer under wherein said projection and the described projection forms a projection, and the thickness of described projection is about 0.1 micron to 1.5 microns.
19. one pixel structure process method according to claim 11, it is characterized in that, when wherein forming described grid, also comprise forming a common electrode line on described substrate, and described common electrode wire constitutes a storage capacitors with the described reflective pixel electrode that is positioned at its top.
20. one pixel structure process method according to claim 11 is characterized in that, the step that wherein forms described pattern dielectric layer and form described patterned semiconductor layer comprises:
Form a dielectric materials layer and semiconductor material layer in regular turn on described substrate and cover described grid; And
Described dielectric materials layer of patterning and described semiconductor material layer are to form described pattern dielectric layer and described patterned semiconductor layer simultaneously, wherein said pattern dielectric layer covers described grid, and described patterned semiconductor layer comprises described channel layer and described these projections that are disposed at described grid top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100913895A CN100499140C (en) | 2007-03-30 | 2007-03-30 | Pixel structure and its production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100913895A CN100499140C (en) | 2007-03-30 | 2007-03-30 | Pixel structure and its production |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101030587A true CN101030587A (en) | 2007-09-05 |
| CN100499140C CN100499140C (en) | 2009-06-10 |
Family
ID=38715786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100913895A Active CN100499140C (en) | 2007-03-30 | 2007-03-30 | Pixel structure and its production |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100499140C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7713797B2 (en) | 2007-12-27 | 2010-05-11 | Au Optronics Corporation | Pixel structure and manufacturing method thereof |
| CN101217152B (en) * | 2008-01-09 | 2010-06-16 | 友达光电股份有限公司 | Pixel structure and its making method |
| CN101295095B (en) * | 2008-06-02 | 2010-07-28 | 友达光电股份有限公司 | Semi-penetrating semi-reflective liquid crystal display device and manufacturing method thereof |
| US8035782B2 (en) | 2008-05-12 | 2011-10-11 | Au Optronics Corp. | Transflective liquid crystal display panel |
| CN102221759A (en) * | 2011-07-19 | 2011-10-19 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal alignment architecture |
| CN102707432A (en) * | 2011-10-18 | 2012-10-03 | 京东方科技集团股份有限公司 | Electrowetting display panel and method for producing same |
| CN103995381A (en) * | 2014-04-17 | 2014-08-20 | 上海天马微电子有限公司 | Pixel structure, liquid crystal display panel and technique thereof |
| WO2015043255A1 (en) * | 2013-09-27 | 2015-04-02 | 京东方科技集团股份有限公司 | Tft array substrate, liquid crystal display panel, and display apparatus |
-
2007
- 2007-03-30 CN CNB2007100913895A patent/CN100499140C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7713797B2 (en) | 2007-12-27 | 2010-05-11 | Au Optronics Corporation | Pixel structure and manufacturing method thereof |
| CN101217152B (en) * | 2008-01-09 | 2010-06-16 | 友达光电股份有限公司 | Pixel structure and its making method |
| US8035782B2 (en) | 2008-05-12 | 2011-10-11 | Au Optronics Corp. | Transflective liquid crystal display panel |
| US8072566B2 (en) | 2008-05-12 | 2011-12-06 | Au Optronics Corp. | Method of forming transflective liquid crystal display panel |
| CN101295095B (en) * | 2008-06-02 | 2010-07-28 | 友达光电股份有限公司 | Semi-penetrating semi-reflective liquid crystal display device and manufacturing method thereof |
| CN102221759A (en) * | 2011-07-19 | 2011-10-19 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal alignment architecture |
| CN102707432A (en) * | 2011-10-18 | 2012-10-03 | 京东方科技集团股份有限公司 | Electrowetting display panel and method for producing same |
| WO2015043255A1 (en) * | 2013-09-27 | 2015-04-02 | 京东方科技集团股份有限公司 | Tft array substrate, liquid crystal display panel, and display apparatus |
| CN103995381A (en) * | 2014-04-17 | 2014-08-20 | 上海天马微电子有限公司 | Pixel structure, liquid crystal display panel and technique thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100499140C (en) | 2009-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101030587A (en) | Pixel structure and its production | |
| CN1854834A (en) | Display device and method for producing same | |
| CN1794048A (en) | Liquid crystal display panel and method of fabricating the same | |
| CN101075030A (en) | Panel assembly | |
| CN1892394A (en) | Liquid crystal display device and fabricating method thereof | |
| CN1932622A (en) | Transflective liquid crystal display device and method of fabricating the same | |
| CN109860224B (en) | Display substrate, manufacturing method thereof, display panel and display device | |
| CN1595271A (en) | Display device and method of manufacturing same | |
| CN1538227A (en) | Transreflection-type liquid crystal display device and method of fabricating the same | |
| CN1598651A (en) | Liquid crystal display apparatus | |
| CN1797150A (en) | Liquid crystal display device and fabricating method thereof | |
| CN1614742A (en) | Thin film transistor substrate with horizontal electric field and its manufacture | |
| CN101047200A (en) | Organic electroluminescent display device and fabrication methods thereof | |
| WO2017121008A1 (en) | Manufacturing method for ips tft-lcd array substrate, and ips tft-lcd array substrate | |
| CN101047157A (en) | Conducting pad system and its making method | |
| CN1675581A (en) | Liquid crystal display device | |
| CN1782843A (en) | Liquid crystal display device and fabricating method thereof | |
| CN101059612A (en) | Semi-penetration semi-reflection type liquid crystal panel and positive element array substrate production method | |
| CN1479144A (en) | Method for manufacturing liquid crystal display device | |
| CN1652296A (en) | Pixel structure, film transistor and mfg. method thereof | |
| CN1607443A (en) | Liquid crystal display panel device and method of fabricating the same | |
| US7855382B2 (en) | Pixel structure | |
| CN1847947A (en) | Manufacturing method of reflective layer of display device, reflective LCD device and transflective lcd device | |
| CN101217152B (en) | Pixel structure and its making method | |
| CN1292295C (en) | Displaying device and its mfg. method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |